KR20130051741A - Array substrate for in-plane switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: An array substrate for an in-plane switching mode liquid crystal display device is provided to prevent the extension of the load of a common electrode by connecting a common line to a sub common pattern through a second common contact hole. CONSTITUTION: A first common contact hole(131) exposes the outermost common electrode(109). A second common contact hole(133) exposes a common line(107). A sub common pattern(120) is connected to the outermost common electrode through the first common contact hole and is connected to the common line through the second common contact hole. A common voltage is applied to the sub common pattern from the common line through the second common contact hole. The common voltage is transferred to the outermost common electrode through the first common contact hole.

Description

Array substrate for in-plane switching mode liquid crystal display device

The present invention relates to a transverse electric field liquid crystal display device, and more particularly, to an array substrate for a transverse electric field liquid crystal display device capable of reducing distortion of a common voltage.

Liquid crystal display devices (LCDs), which are used for TVs and monitors due to their high contrast ratio and are advantageous for displaying moving images, are characterized by optical anisotropy and polarization of liquid crystals. The principle of image implementation by

Such a liquid crystal display is an essential component of a liquid crystal panel bonded through a liquid crystal layer between two side-by-side substrates, and realizes a difference in transmittance by changing an arrangement direction of liquid crystal molecules with an electric field in the liquid crystal panel. do.

Recently, an active matrix liquid crystal display device that drives liquid crystal with an electric field formed up-down has been widely used because of its excellent resolution and video performance. However, liquid crystal driving due to an electric field that is applied up-down has a disadvantage in that the viewing angle characteristics are inferior.

Accordingly, various methods have been proposed in order to overcome the disadvantage that the viewing angle is narrow. Among them, a liquid crystal driving method by a transverse electric field is attracting attention.

1 is a cross-sectional view schematically showing a liquid crystal panel of a general transverse electric field type liquid crystal display device.

As shown in the figure, the lower substrate 1, which is an array substrate, and the upper substrate 3, which is a color filter substrate, are spaced apart from each other and face each other. A liquid crystal layer 5 is interposed between the upper and lower substrates 1, .

A common electrode 21 and a pixel electrode 25 are formed on the same plane on the lower substrate 1. The liquid crystal layer 5 is formed by a common electric field 21 and a horizontal electric field L by the pixel electrode 25, Lt; / RTI >

As described above, the horizontal field type liquid crystal display device forms a common electrode 21 and a pixel electrode 25 on the lower substrate 1, and generates a horizontal electric field L between the two electrodes 21 and 25 to form a liquid crystal molecule. By arranging parallel to the horizontal electric field L parallel to the substrates 1 and 3, the viewing angle of the liquid crystal display device can be widened.

On the other hand, the common electrode 21 is formed in a direction parallel to the gate wiring (not shown), since the pixels of one horizontal line are simultaneously applied with the data voltage by the scan pulse, the common electrode 21 facing the pixels The load of becomes large.

The load of the common electrode 21 is defined as an RC delay defined by the product of the line resistance and the parasitic capacitance of the common electrode 21. When the RC delay is high, the image quality is deteriorated due to crosstalk. Done.

Therefore, in order to reduce the RC delay, the line resistance of the common electrode 21 should be reduced, but the current structure of the common electrode 21 has a limitation in reducing the line resistance.

As a result, the common voltage is not maintained at a constant value, and as shown in FIG. This ripple of the common voltage is a major factor causing horizontal crosstalk when a specific data voltage is applied.

In addition, since the line resistance of the common electrode 21 increases from the left and right regions of the panel toward the middle region of the panel, in-plane variation of the common voltage is caused. This in-plane variation of the common voltage causes up and down brightness difference, flicker, and afterimage.

The present invention has been made to solve the above problems, and a first object of the present invention is to reduce the line resistance of the common electrode.

Accordingly, a second object of the present invention is to provide a transverse electric field type liquid crystal display device which prevents distortion of the common voltage and has excellent display quality.

In order to achieve the object as described above, the present invention comprises a gate wiring and a data wiring to form a plurality of pixel regions by crossing each other with a gate insulating film on the substrate; A common wiring formed to be spaced apart from the gate wiring; A thin film transistor connected to the gate line and the data line; An outermost common electrode connected to the common wiring and formed at an outermost portion of each pixel area in parallel with the data wiring; A plurality of pixel electrodes connected to the thin film transistors in the pixel areas and spaced apart from each other in parallel with the data lines; A first common contact hole exposing the outermost common electrode; A second common contact hole exposing the common wiring; And formed in each of the pixel regions, and electrically connected to each other to form a plurality of mesh structures, connected to the outermost common electrode through the first common contact hole, and through the second common contact hole. An auxiliary common pattern connected to the common wiring; A plurality of central common electrodes branched from the auxiliary common pattern and alternately arranged in parallel with the plurality of pixel electrodes, and a common voltage is transferred from the common wiring to the auxiliary common pattern through the second common contact hole; The common voltage transferred to the auxiliary common pattern provides a vertical line common voltage path structure that is transferred to the outermost common electrode through the first common contact hole.

In this case, the common wiring and the outermost common electrode are made of the same material in the same layer as the gate wiring, and the common wiring and the outermost common electrode are made of copper (Cu) or a copper alloy (Cu alloy).

The auxiliary common pattern and the central common electrode may be formed of any one of indium tin oxide (ITO) and indium zinc oxide (IZO), and the auxiliary common pattern may be parallel to the gate wiring and may be connected to the data wiring. It overlaps with the outermost common electrode to form a mesh structure with the common wiring.

The first common contact hole and the second common contact hole are adjacent to each other with the gate wiring interposed therebetween, and an auxiliary pixel pattern connecting all ends of the pixel electrode is spaced apart from the gate wiring. do.

In addition, the data line, the pixel electrode, and the outermost and center common electrodes form a symmetrically bent structure with respect to the center of each pixel region, and the thin film transistor is left or right in the neighboring pixel region. Alternately located.

As described above, according to the present invention, the common wiring and the auxiliary common pattern are formed through the second common contact hole near the region where the outermost common electrode and the common wiring formed of copper (Cu) or copper alloy are separated. In this way, the load of the common electrode can be prevented from increasing as compared with the conventional formation of the common voltage pass structure of the vertical line through only the auxiliary common pattern, which is a transparent conductive material. Therefore, there is an effect that the deterioration in image quality due to crosstalk can be prevented.

In addition, there is an effect that can prevent the occurrence of the vertical brightness difference, flicker and afterimage due to the in-plane deviation of the common voltage.

In addition, by increasing the means for applying the common voltage to the common electrode through the second common contact hole without lowering the aperture ratio, the in-plane variation in the common voltage can be greatly reduced, thereby greatly reducing the load of the common electrode. It has an effect.

1 is a cross-sectional view schematically showing a liquid crystal panel of a general transverse electric field type liquid crystal display device.
2 is a view showing that a ripple occurs due to a line resistance of a common voltage of a general transverse electric field type liquid crystal display device;
3 is a plan view schematically showing an array substrate for a transverse electric field type liquid crystal display device according to a first embodiment of the present invention;
4 is a plan view illustrating a vertical line common voltage path structure of an array substrate for a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention.
5 is a plan view illustrating a vertical line common voltage path structure of an array substrate for a transverse electric field type liquid crystal display device according to a second exemplary embodiment of the present invention.
6 is a cross-sectional view taken along the line VI-VI of FIG. 5.
FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 5. FIG.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

- First Embodiment -

3 is a plan view schematically illustrating an array substrate for a transverse electric field type liquid crystal display device according to a first embodiment of the present invention.

 In this case, an enlarged view of one pixel area P including the switching device is illustrated for more detailed description.

As shown, the array substrate 101 for a transverse electric field type liquid crystal display device according to the first embodiment of the present invention extends vertically and horizontally to the lower and upper portions thereof with a gate insulating film (not shown) interposed therebetween, thereby forming a pixel region. A plurality of gate wirings 103 and data wirings 105 defining (P) are formed.

The common wiring 107 is formed through the pixel region P and spaced apart from the gate wiring 103.

In addition, each pixel region P is connected to the gate wiring 103 and the data wiring 105, and includes a gate electrode 111, a gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon, A semiconductor layer (not shown) including an ohmic contact layer (not shown) of impurity amorphous silicon and a thin film transistor Tr including source and drain electrodes 117 and 119 spaced apart from each other are formed.

In this case, although the thin film transistor Tr is shown as an example of forming a 'U' in the channel, the thin film transistor Tr may be modified in various forms.

Here, the outermost common electrode 109 is formed in each pixel region P in a form branched from the common wiring 107 in parallel with the data wiring 105. The outermost common electrode 109 and the common wiring 107 are made of the same material in the same layer in which the gate wiring 103 and the gate electrode 111 are formed.

In this case, the common wiring 107 and the outermost common electrode 109 made of the same material on the same layer as the gate wiring 103 and the gate electrode 111 may be made of copper (Cu) or a copper alloy (Cu alloy). Do.

Copper (Cu) or copper alloy (Cu alloy) used as the common wiring 107 and the outermost common electrode 109 has a lower resistance value than a transparent conductive material such as ITO, and relatively molybdenum (Mo) It also has a low resistance characteristic that is better than aluminum (Al).

In addition, an auxiliary common pattern 120 that receives a common voltage from the outermost common electrode 109 is formed in each pixel region P, and branches from the auxiliary common pattern 120 to form the outermost common electrode 109. In parallel with each other, a plurality of central common electrodes 121 are formed at regular intervals.

At this time, the auxiliary common pattern 120 is formed so as to overlap these components corresponding to the data wiring 105 and the outermost common electrode 109 adjacent to each other at the boundary of each pixel region P. As shown in FIG.

Therefore, the auxiliary common pattern 120 forms a mesh structure together with the common wiring 107.

The auxiliary common pattern 120 includes the first common contact hole 131 in which the auxiliary common pattern 120 formed in one pixel area P among three pixel areas P adjacent to each other in a horizontal line in consideration of a decrease in aperture ratio. In contact with the outermost common electrode 109 through), a common voltage is applied.

In addition, an auxiliary pixel pattern 123 connected to the drain electrode 119 of the thin film transistor Tr through the drain contact hole 118 is formed in parallel with the common wiring 107 in each pixel area P. A plurality of pixel electrodes 125 are formed by branching from the auxiliary pixel pattern 123.

In this case, the auxiliary common pattern 120, the central common electrode 121, and the auxiliary pixel pattern 123 and the pixel electrode 125 are made of the same material in the same layer.

Here, the common electrodes 109 and 121 and the pixel electrode 125 formed in each pixel region P may form a virtual line CL in parallel with the gate wiring 103 at the center of each pixel region P. At this time, it has a structure symmetrically bent with respect to the virtual line CL.

That is, each common electrode 109 and 121 and the pixel electrode 125 have a predetermined angle bent in a clockwise or counterclockwise direction from a direction perpendicular to the virtual line CL based on the virtual line CL. .

Accordingly, the upper and lower portions of the upper and lower portions of the pixel region P are changed in directions of the common electrodes 109 and 121 and the pixel electrode 125 to form different domain regions.

In this case, in the transverse type liquid crystal display, the movement of liquid crystals located in different domains in one pixel region P is different, and finally, the arrangement of the long axes of the liquid crystal molecules is changed, thereby causing color shift at a specific azimuth angle. Will be reduced.

That is, for convenience of description, if the region configured above the virtual line within each pixel region P is defined as the first domain region D1 and the region configured below the second domain region D2, The azimuth angle at which the color shift occurs in the first domain region D1 and the azimuth angle at which the color shift occurs in the second domain region D2 are different, so that each domain region compensates for the color shift phenomenon. The shift phenomenon can be reduced.

In this case, the predetermined angle may be 7 degrees to 10 degrees, and ± 7 degrees to ± 10 degrees with respect to the direction in which the outermost and central common electrodes 109 and 121 and the pixel electrode 125 are perpendicular to the virtual line CL. If the structure is bent at a larger angle, more reliable domain separation is possible in one pixel region P, but the driving voltage is increased and the overall white luminance is decreased due to the VT curve characteristics. 121 and the pixel electrode 125 may have a bent structure having an angle of about ± 7 degrees to ± 10 degrees with respect to the direction perpendicular to the virtual line CL.

Here, the outermost and central common electrodes 109 and 121 and the pixel electrodes 125 have a bent configuration so that the data wiring 105 is also symmetrically bent with respect to the center of each pixel region P. FIG. Since the data line 105 is not separately formed for each pixel area P but has a configuration connected to the entire display area, the data line 105 is bent based on the center of each pixel area P in the display area. Zigzag form.

Meanwhile, the common wiring 107 is formed to have a wider width than the other regions in the vicinity of the thin film transistor Tr formed in each pixel region P to form a first storage electrode, and the gate is formed on the first storage electrode. A second storage electrode is formed in which the drain electrode 119 extends through an insulating film (not shown). In this case, the first and second storage electrodes overlapping each other with the gate insulating layer interposed therebetween form a storage capacitor StgC.

Here, the most characteristic configuration in the first embodiment of the present invention is a configuration in which the common wiring 107 is connected to the auxiliary common wiring 120 through the second common contact hole 133.

As a result, the load of the common electrodes 109 and 121 may be prevented from increasing, and thus the degradation of the image quality due to crosstalk may be prevented. In addition, it is possible to prevent the up and down brightness difference, flicker, and afterimage caused by in-plane variations of the common voltage.

In more detail, the outermost common electrode 109 branched from the common wiring 107 and the common wiring 107 is made of the same material in the same layer as the gate wiring 103 and the outermost common electrode 109. The auxiliary common pattern 120 and the central common electrode 121 contacting each other through the first common contact hole 131 are made of the same material on the same layer as the pixel electrode 125.

In this case, the common wiring 107 and the outermost common electrode 109 are made of copper (Cu) or copper alloy (Cu alloy), and the auxiliary common pattern 120 and the central common electrode 121 are indium tin oxide. (ITO), indium-zinc-oxide (IZO) or molybdenum (MoTi).

The array substrate 101 for a transverse electric field type liquid crystal display device having such a configuration forms a common voltage path structure through a common wiring 107 in a horizontal line and is common through an auxiliary common pattern 120 in a vertical line. The voltage path structure is formed.

Here, the transparent conductive material has a relatively large resistance compared to metal materials such as copper (Cu) or copper alloy (Cu alloy), and causes nonuniformity of the common voltage path structure of the horizontal line and the common voltage path of the vertical line.

That is, the auxiliary common pattern 120 made of the transparent conductive material of the vertical line and the central common electrode 121 have a high resistance value, and the vertical line generates a load of the common voltage, and the in-plane deviation of the common voltage is generated. Will be generated.

In particular, the common wiring 107 and the outermost common electrode 109 have a lower resistance value than the transparent conductive material and have a lower resistance characteristic than molybdenum (Mo) and aluminum (Al). As the alloy is made of Cu alloy, the nonuniformity of the common voltage path structure of the horizontal line and the common voltage path of the vertical line is generated more.

In order to prevent such unevenness of the common voltage path, the auxiliary common pattern 120 made of a transparent conductive material and the central common electrode 121 may also be formed, such as copper (Cu) or copper alloy (Cu alloy), in addition to the vertical common line. It is preferable to form a common voltage path through the common wiring 107 and the outermost common electrode 109 made of a metal material, but as mentioned above, the common wiring 107 and the outermost common electrode 109 may be formed of a gate wiring. As formed in the same layer as 103, the common line 107 and the outermost common electrode 109 are formed by cutting the region in the region corresponding to the position where the gate line 103 is formed.

That is, the common wiring 107 and the outermost common electrode 109 remain connected to both horizontal lines, but are separated from the vertical lines by the gate wiring 103.

Accordingly, in the first embodiment of the present invention, the second common contact hole 133 exposing the common wiring 107 is further formed, and the common wiring 107 and the auxiliary common wiring are formed through the second common contact hole 133. The 120 is connected to each other, so that the common wiring 107 separated through the auxiliary common wiring 120 is connected, so that the vertical lines are made of a metal material such as copper (Cu) or copper alloy (Cu alloy). To form a common voltage path.

Through this, it is possible to prevent the path unevenness of the common voltage between the vertical line and the horizontal line, and to prevent the load of the common electrodes 109 and 121 from increasing to the vertical line, thereby preventing crosstalk. ) Can be prevented from occurring. In addition, it is possible to prevent the up and down brightness difference, flicker and afterimage caused by in-plane variations of the common voltage.

In this case, the second common contact hole 133 is positioned adjacent to the first common contact hole 131 where the auxiliary common pattern 120 and the outermost common electrode 109 are electrically connected to each other, thereby providing a vertical line common voltage path. It is preferable that the structure is formed through the common wiring 107 and the outermost common electrode 109 as much as possible.

4 is a plan view illustrating a vertical line common voltage path structure of an array substrate for a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention.

As shown, the array substrate 101 for a transverse electric field type liquid crystal display device according to the first embodiment of the present invention is formed with a plurality of gate wirings 103 extending in a first direction, and a plurality of gate wirings 103 ), A plurality of data lines 105 extending in the second direction to define the plurality of pixel regions P are formed.

The common wiring 107 is formed through the pixel region P and spaced apart from the gate wiring 103.

In addition, a thin film transistor Tr is formed at a portion where each gate line 103 and each data line 105 cross each other, and is electrically connected to the drain electrode 119 of the thin film transistor Tr and the data line 105. In parallel with the pixel electrode 125 is formed.

The pixel electrode 125 is formed by branching from the auxiliary pixel pattern 123 formed to be parallel to the common wiring 107.

The common electrodes 109 and 121, which are electrically connected to each other through the common wiring 107 and the first common contact hole 131, are formed to be parallel to the pixel electrode 125. A central common electrode formed to be parallel to the pixel electrode 125 by branching from the outermost common electrode 109 and the auxiliary common pattern 120 and the auxiliary common pattern 120 parallel to the common wiring 107. It consists of 121.

In this case, the common wiring 107 and the outermost common electrode 109 are made of the same material on the same layer as the gate wiring 103, and the auxiliary common pattern 120 and the central common electrode 121 are the pixel electrode 125. And made of the same material in the same layer.

Therefore, the auxiliary common pattern 120 is electrically connected to the outermost common electrode 109 through the first common contact hole 131. In this case, three pixels adjacent to each other among the pixel regions P of the horizontal line are adjacent to each other. The auxiliary common pattern 120 of the pixel region P positioned in the center of the region P is electrically connected to the outermost common electrode 109 through the first common contact hole 131.

The first common contact hole is disposed in the pixel area P adjacent to the pixel area P where the outermost common electrode 109 and the auxiliary common pattern 120 are connected to each other through the first common contact hole 131. A second common contact hole 133 is formed to expose the common wiring 107 adjacent to the 131, and the common wiring 107 and the auxiliary common pattern 120 are electrically connected to each other through the second common contact hole 133. Connected.

Therefore, the array substrate 101 for a transverse electric field type liquid crystal display device according to the first embodiment of the present invention has a vertical line common voltage path through the outermost common electrode 109, the common wiring 107, and the auxiliary common pattern 120. To form a structure.

Through this, it is possible to prevent the path unevenness of the common voltage between the vertical line and the horizontal line, and to prevent the load of the common electrodes 109 and 121 from increasing to the vertical line, thereby preventing crosstalk. ) Can be prevented from occurring. In addition, it is possible to prevent the up and down brightness difference, flicker, and afterimage caused by in-plane variations of the common voltage.

That is, the common voltage is applied to the common wiring 107 through the outermost common electrode 109 of the first pixel region P1 of the first column in the vertical direction, and the common voltage transferred to the common wiring 107 is The second common contact hole 133 is transferred to the auxiliary common pattern 120 of the first pixel region P2 in the second column.

The common voltage transferred to the auxiliary common pattern 120 of the first pixel region P2 of the second column is directly transferred to the outermost common electrode 109 through the first common contact hole 131 and the outermost common electrode. The common voltage transferred to 109 is transferred to the common wiring 107, and the common voltage transferred to the common wiring 107 is applied to the first pixel region P3 of the third column through the second common contact hole 133. It is transmitted to the auxiliary common pattern (120).

Thus, the common voltage pass structure of the vertical line is completed.

In this case, since the outermost common electrode 109 and the common wiring 106 are made of a metal material such as copper (Cu) or copper alloy (Cu alloy) having a relatively low resistance compared to the transparent conductive material, It is possible to prevent the load of the common electrodes 109 and 121 from increasing as compared with the conventional formation of the common voltage path structure of the vertical line through only the auxiliary common pattern 120, so that the image quality is reduced by crosstalk. Can be prevented from occurring.

In addition, it is possible to prevent the up and down brightness difference, flicker, and afterimage caused by in-plane variations of the common voltage.

Here, since the second common contact hole 133 is formed on the common wiring 106, the second common contact hole 133 does not contribute to the reduction of the aperture ratio, and thus the common voltage is transmitted through the second common contact hole 133 without the aperture ratio. By increasing the means for applying to 121, through this it is also possible to significantly reduce the common voltage in-plane variation, it is possible to significantly reduce the load of the common electrodes (109, 121).

That is, the first common contact hole 131 is formed only in the pixel region P positioned among the three pixel regions P adjacent to each other, so that the auxiliary common pattern 120 is formed from the outermost common electrode 109. Although it was a 1/3 type structure receiving a common voltage, the array substrate 101 for a transverse electric field type liquid crystal display device according to the first embodiment of the present invention further includes a second common contact hole 133, thereby providing a 2/3 type. Structure.

Accordingly, the common voltage can be better transmitted to the auxiliary common pattern 120 and the central common electrode 121, thereby significantly reducing the in-plane variation of the common voltage, and greatly reducing the load of the common electrodes 109 and 121. will be.

- Second Embodiment -

5 is a plan view illustrating a vertical line common voltage path structure of an array substrate for a transverse electric field type liquid crystal display device according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the cutting line VI-VI of FIG. 5. 7 is a cross-sectional view taken along the line VII-VII of FIG. 5.

For convenience of description, an area in which the thin film transistor Tr, which is a switching element, is formed is defined as a switching area TrA, and an area in which the storage capacitor StgC is formed is defined as a storage area StgA.

As shown, the array substrate 101 for a transverse electric field type liquid crystal display device according to the second embodiment of the present invention is formed with a plurality of gate wirings 103a and 103b extending in a first direction, and a plurality of gate wirings. A plurality of data wirings 105a and 105b are formed extending in the second direction to intersect the 103a and 103b to define the plurality of pixel regions P. As shown in FIG.

The common wiring 107 is formed through the pixel region P and spaced apart from the gate wirings 103a and 103b.

In addition, the gate wirings 103a and 103b and the data wirings 105a and 105b are connected to the switching region TrA of each pixel region P, and the gate electrode 111, the gate insulating film 113, A semiconductor layer 115 including an active layer 115a of pure amorphous silicon and an ohmic contact layer 115b of impurity amorphous silicon, and a thin film transistor Tr including source and drain electrodes 117 and 119 spaced apart from each other are formed. It is.

At this time, the gate wirings 103a and 103b are themselves part of the gate wirings 111.

Here, in the drawing, although the thin film transistor Tr shows that the region constituting the channel forms a 'U' as an example, it may be modified in various forms.

Here, the most characteristic configuration in the second embodiment of the present invention is that the thin film transistor Tr is formed in a zigzag shape.

That is, the thin film transistor Tr formed in the plurality of pixel regions P of the first column is formed at the intersection of the gate wiring 103a and the data wirings 105a and 105b on the left side of the pixel region P. The thin film transistor Tr formed in the plurality of pixel regions P in the second column is formed at a portion where the gate wiring 103b and the data wirings 105a and 103b on the right side of the pixel region P cross each other.

Therefore, the first thin film transistor Tr1 of the first pixel P1 of the first column is connected to the first gate line 103a and the first data line 105a and is formed of the first pixel P2 of the second column. The second thin film transistor Tr is connected to the second gate line 103b and the second data line 105b.

As described above, by forming the thin film transistor Tr in a zigzag shape, it is possible to prevent the moiré phenomenon in which the display quality is degraded due to the interference phenomenon in the non-display area.

The pixel electrode is electrically connected to the drain electrode 119 of the thin film transistor Tr and parallel to the data lines 105a and 105b.

The pixel electrode 125 is formed by branching from the auxiliary pixel pattern 123 formed to be parallel to the common wiring 107.

In addition, the auxiliary common pattern 120 electrically connected to the outermost common electrode 109 and the first common contact hole 131 extending from the common wiring 107 is positioned parallel to the gate wiring 103. The central common electrode 121 is formed in parallel with the pixel electrode 125 by branching from the auxiliary common pattern 120.

In this case, the auxiliary common pattern 120 is formed so as to overlap these components in correspondence with the data wirings 105a and 105b and the outermost common electrode 109 adjacent to each pixel region P. FIG.

Therefore, the auxiliary common pattern 120 forms a mesh structure together with the common wiring 107.

In addition, the outermost and central common electrodes 109 and 121 and the pixel electrodes 125 formed in the pixel areas P are arranged in parallel with the gate wirings 103a and 103b at the center of each pixel area P. FIG. When (CL of FIG. 3) is attached, it has a structure symmetrically bent with respect to an imaginary line (CL of FIG. 3).

In this case, in the storage area StgA in each pixel area P, the common wiring 107 is formed to have a wider width than other areas in the vicinity of the thin film transistor Tr, thereby forming the first storage electrode 107a. A second storage electrode 119a is formed on the first storage electrode 107a with the drain electrode 119 extending through the gate insulating layer 113. In this case, the first and second storage electrodes 107a and 119a overlapping each other with the gate insulating layer 113 interposed therebetween form a storage capacitor StgC.

Here, the common wiring 107 and the outermost common electrode 109 are made of the same material in the same layer as the gate wiring 103, and the common wiring 107 and the outermost common electrode 109 are made of copper (Cu) or It is preferably made of a copper alloy (Cu alloy).

Copper (Cu) or copper alloy (Cu alloy) used as the common wiring 107 and the outermost common electrode 109 has a lower resistance value than the transparent conductive material, and relatively molybdenum (Mo) or aluminum ( It has a good low resistance characteristic compared to Al).

The auxiliary common pattern 120 and the central common electrode 121 are made of the same material in the same layer as the pixel electrode 125.

Therefore, the auxiliary common pattern 120 is electrically connected to the outermost common electrode 109 through the first common contact hole 131. In this case, three pixels adjacent to each other among the pixel regions P of the horizontal line are adjacent to each other. The auxiliary common pattern 120 of the pixel region P positioned in the center of the region P is electrically connected to the outermost common electrode 109 through the first common contact hole 131.

The first common contact hole is disposed in the pixel area P adjacent to the pixel area P where the outermost common electrode 109 and the auxiliary common pattern 120 are connected to each other through the first common contact hole 131. A second common contact hole 133 is formed to expose the common wiring 107 adjacent to the 131, and the common wiring 107 and the auxiliary common pattern 120 are electrically connected to each other through the second common contact hole 133. Connected.

Accordingly, the array substrate 101 for a transverse electric field type liquid crystal display device according to the second embodiment of the present invention has a vertical line common voltage path through the outermost common electrode 109, the common wiring 107, and the auxiliary common pattern 120. To form a structure.

Through this, it is possible to prevent the path unevenness of the common voltage between the vertical line and the horizontal line, and to prevent the load of the common electrodes 109 and 121 from increasing to the vertical line, thereby preventing crosstalk. ) Can be prevented from occurring. In addition, it is possible to prevent the up and down brightness difference, flicker, and afterimage caused by in-plane variations of the common voltage.

That is, the common voltage is applied to the common wiring 107 through the outermost common electrode 109 of the first pixel region P1 of the first column in the vertical direction, and the common voltage transferred to the common wiring 107 is The second common contact hole 133 is transferred to the auxiliary common pattern 120 of the first pixel region P2 in the second column.

The common voltage transferred to the auxiliary common pattern 120 of the first pixel region P2 of the second column is directly transferred to the outermost common electrode 109 through the first common contact hole 131 and the outermost common electrode. The common voltage transferred to 109 is transferred to the common wiring 107, and the common voltage transferred to the common wiring 107 is applied to the first pixel region P3 of the third column through the second common contact hole 133. It is transmitted to the auxiliary common pattern (120).

Thus, the common voltage pass structure of the vertical line is completed.

In this case, since the outermost common electrode 109 and the common wiring 106 are made of a metal material such as copper (Cu) or copper alloy (Cu alloy) having a relatively low resistance compared to the transparent conductive material, It is possible to prevent the load of the common electrodes 109 and 121 from increasing as compared with the conventional formation of the common voltage path structure of the vertical line through only the auxiliary common pattern 120, so that the image quality is reduced by crosstalk. Can be prevented from occurring.

In addition, it is possible to prevent the up and down brightness difference, flicker, and afterimage caused by in-plane variations of the common voltage.

Here, since the second common contact hole 133 is formed on the common wiring 106, the second common contact hole 133 does not contribute to the reduction of the aperture ratio, and thus the common voltage is transmitted through the second common contact hole 133 without the aperture ratio. By increasing the means for applying to 121, through this it is also possible to significantly reduce the common voltage in-plane variation, it is possible to significantly reduce the load of the common electrodes (109, 121).

That is, the first common contact hole 131 is formed only in the pixel region P positioned among the three pixel regions P adjacent to each other, so that the auxiliary common pattern 120 is formed from the outermost common electrode 109. Although it was a 1/3 type structure receiving a common voltage, the array substrate 101 for a transverse electric field type liquid crystal display device according to the first embodiment of the present invention further includes a second common contact hole 133, thereby providing a 2/3 type. Structure.

Accordingly, the common voltage can be better transmitted to the auxiliary common pattern 120 and the central common electrode 121, thereby significantly reducing the in-plane variation of the common voltage, and greatly reducing the load of the common electrodes 109 and 121. will be.

Table (1) shows the vertical line common voltage pass structure of a general horizontal field type liquid crystal display array substrate and the vertical line common voltage pass structure of a horizontal field type liquid crystal display array substrate 101 according to the second embodiment of the present invention. Experimental results of comparing and measuring the resistance of.

Sample 1 Sample 2 Resistance (Ω) 3.46E + 01 7.07E + 02 Resistance ratio One 20.43 (↑)

Here, Sample1 is an experimental result of measuring the resistance value of the vertical line common voltage pass structure of the array substrate 101 for a transverse electric field liquid crystal display device according to the second embodiment of the present invention, and Sample 2 is a general transverse electric field liquid crystal display device. This is a test result of measuring the resistance of the vertical line common voltage path structure of the array array substrate.

That is, Sample1 further forms a second common contact hole 133 exposing the common wiring 107 near the region where the first common contact hole 131 is formed, thereby forming copper (Cu) or copper alloy (Cu alloy). The resistance value of the vertical line common voltage path structure from the outermost common electrode 109 to the common wiring 107 and through the auxiliary common pattern 120 made of the transparent conductive material and back to the outermost common electrode 109 is measured. Sample 2 is an experimental result to measure the resistance of the vertical line common voltage pass structure consisting of only the auxiliary common pattern 120 made of a transparent conductive material.

Referring to Table (1), it can be seen that Sample 1 has a 20.43% lower resistance than Sample 2.

That is, according to the second embodiment of the present invention, the vertical line common voltage path structure has a lower resistance value than that of the transparent conductive material, and copper (Cu) having low resistance characteristics even better than that of molybdenum (Mo) and aluminum (Al). Alternatively, using the common wiring 107 and the outermost common electrode 109 made of Cu alloy can lower the resistance of the common voltage path structure compared to using the auxiliary common pattern 120 made of only a transparent conductive material. It can be seen that.

As described above, the array substrate 101 for a transverse electric field type liquid crystal display device of the present invention is formed by separating the outermost common electrode 109 and the common wiring 107 formed of copper (Cu) or copper alloy (Cu alloy). The common wiring 107 and the auxiliary common pattern 120 are directly connected to each other through the second common contact hole 133 near the area, and thus, the common lines of the vertical lines are formed only through the auxiliary common pattern 120 which is a transparent conductive material. The load of the common electrodes 109 and 121 can be prevented from increasing as compared with the conventional formation of the voltage path structure, thereby preventing the degradation of image quality due to crosstalk.

In addition, it is possible to prevent the up and down brightness difference, flicker, and afterimage caused by in-plane variations of the common voltage.

Since the second common contact hole 133 is formed on the common wiring 107, the second common contact hole 133 does not contribute to the reduction of the aperture ratio. Therefore, the common voltage is transmitted through the second common contact hole 133 without the decrease of the aperture ratio. By increasing the means for applying to 121, through this it is also possible to significantly reduce the common voltage in-plane variation, it is possible to significantly reduce the load of the common electrodes (109, 121).

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

103a, 103b: gate wiring, 105a, 105b: data wiring,
107: common wiring, 109: outermost common electrode
111: gate electrode, 117: source electrode, 118: drain contact hole, 119: drain electrode
120: common auxiliary pattern, 121: common electrode in the center, 123: auxiliary pixel pattern, 125: pixel electrode
131: first common contact hole, 133: second common contact hole
P: pixel area, Tr: thin film transistor

Claims (9)

Gate wiring and data wiring intersecting each other with a gate insulating film interposed therebetween to form a plurality of pixel regions on a substrate;
A common wiring formed to be spaced apart from the gate wiring;
A thin film transistor connected to the gate line and the data line;
An outermost common electrode connected to the common wiring and formed at an outermost portion of each pixel area in parallel with the data wiring;
A plurality of pixel electrodes connected to the thin film transistors in the pixel areas and spaced apart from each other in parallel with the data lines;
A first common contact hole exposing the outermost common electrode;
A second common contact hole exposing the common wiring;
And formed in each of the pixel regions, and electrically connected to each other to form a plurality of mesh structures, connected to the outermost common electrode through the first common contact hole, and through the second common contact hole. An auxiliary common pattern connected to the common wiring;
A plurality of central common electrodes branched from the auxiliary common pattern and alternately arranged in parallel with the plurality of pixel electrodes.
The common voltage is transferred from the common wiring to the auxiliary common pattern through the second common contact hole, and the common voltage transferred to the auxiliary common pattern is the outermost common through the first common contact hole. An array substrate for a transverse electric field type liquid crystal display device having a vertical line common voltage pass structure delivered to an electrode.
The method of claim 1,
And the common wiring and the outermost common electrode are made of the same material in the same layer as the gate wiring.
The method of claim 2,
And the common wiring and the outermost common electrode are formed of copper (Cu) or copper alloy (Cu alloy).
The method of claim 1,
The auxiliary common pattern and the central common electrode are formed of any one of indium tin oxide (ITO) and indium zinc oxide (IZO).
The method of claim 1,
And the auxiliary common pattern is parallel to the gate line and overlaps the data line and the outermost common electrode to form a mesh structure with the common line.
The method of claim 1,
And the first common contact hole and the second common contact hole are adjacent to each other with the gate wiring interposed therebetween.
The method of claim 1,
And an auxiliary pixel pattern connecting both ends of the pixel electrode to be spaced apart from the gate wiring in parallel to each other.
The method of claim 1,
And the data line, the pixel electrode, and the outermost and center common electrodes are symmetrically bent with respect to the center of each pixel area.
The method of claim 1,
And the thin film transistors are alternately positioned left or right in the neighboring pixel areas.

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