KR20130051701A - Thin film transistor substrate having metal oxide semiconductor and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor substrate having metal oxide semiconductor and a manufacturing method thereof are provided to form a semiconducting channel layer and a pixel anode layer which are made of the same material, and to perform a selective process using six masks. CONSTITUTION: A gate insulating layer(GI) covers a gate element formed on a substrate(SUB). A thin film transistor(T) includes a channel layer(A) including metal oxide semiconductor. The channel layer is overlapped with a part of the gate element on the gate insulating layer. A pixel electrode(PXL) is horizontally separated from the channel layer on the gate insulating layer, and is connected to the thin film transistor. The pixel electrode includes the metal oxide semiconductor.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate including a metal oxide semiconductor,

The present invention relates to a thin film transistor (TFT) substrate for a flat panel display including a metal oxide semiconductor and a method of manufacturing the same. In particular, the present invention relates to a thin film transistor substrate for a flat panel display in which a semiconductor channel layer and a pixel layer are formed by selectively treating a metal oxide and a method for manufacturing the same.

The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device which are actively driven, the thin film transistor substrate includes thin film transistors arranged in pixel regions arranged in a matrix manner. BACKGROUND ART Liquid crystal display devices (LCDs) display images by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is divided into a vertical electric field type and a horizontal electric field type in accordance with the direction of the electric field driving the liquid crystal.

A vertical electric field type liquid crystal display device drives a liquid crystal of a TN (Twisted Nematic) mode by a vertical electric field formed between a pixel electrode and a common electrode arranged opposite to upper and lower substrates. Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is narrow to about 90 degrees.

The horizontal electric field type liquid crystal display device forms a horizontal electric field between a pixel electrode and a common electrode arranged in parallel to a lower substrate to drive an in plane switching (IPS) mode liquid crystal. Such an IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. Specifically, in the IPS mode liquid crystal display device, in order to form the in-plane field, the interval between the common electrode and the pixel electrode is formed to be wider than the interval between the upper and lower substrates. In order to obtain an electric field of proper intensity, The electrodes are formed in a band shape having a constant width. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal above the pixel electrode and the common electrode. That is, the liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain the initial alignment state. The liquid crystal that maintains the initial state can not transmit light, which causes a decrease in aperture ratio and transmittance.

A fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed to overcome the disadvantage of the IPS mode liquid crystal display device. The FFS-type liquid crystal display device has a common electrode and a pixel electrode in each pixel region with an insulating film interposed therebetween. The interval between the common electrode and the pixel electrode is narrower than the interval between the upper and lower substrates, To form a parabolic fringe field. The liquid crystal molecules interposed between the upper and lower substrates are operated by the fringe field, so that the aperture ratio and the transmittance can be improved.

1 is a plan view showing a thin film transistor (TFT) substrate having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along a cutting line I-I '.

The thin film transistor substrate shown in FIGS. 1 and 2 includes a gate wiring 13 and a data wiring 23 intersecting each other with a gate insulating film 11 interposed therebetween on a lower substrate 1, and a thin film transistor 7). The thin film transistor substrate defines a pixel region with an intersection structure of the gate wiring 13 and the data wiring 23. The pixel region includes a pixel electrode 45 and a common electrode 55 formed with a protective film 11 therebetween so as to form a fringe field. The pixel electrode 45 has a substantially rectangular shape corresponding to the pixel region, and the common electrode 55 is formed into a plurality of parallel strips.

The common electrode 55 is connected to the common wiring 53 arranged in parallel with the gate wiring. The common electrode 55 is supplied with a reference voltage (or a common voltage) for liquid crystal driving through the common wiring 53.

The thin film transistor 7 responds to the gate signal of the gate wiring 13 so that the pixel electrode 45 is charged with the pixel signal of the data wiring 23. For this, the thin film transistor 7 opposes the gate electrode 15 branched from the gate wiring 13, the source electrode 25 branched from the data line 23, and the source electrode 25, And a semiconductor layer 37 which overlaps the gate electrode 15 on the gate insulating film 11 and forms a channel between the source electrode 25 and the drain electrode 35. [ The semiconductor layer 37 and the drain electrode 35 may further include an ohmic contact layer for ohmic contact between the semiconductor layer 37 and the source electrode 25 and between the semiconductor layer 37 and the drain electrode 35. [

Particularly, when the semiconductor layer 37 is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper (ES) for protecting the upper surface from the etchant in order to secure the stability of the device. Specifically, it is preferable that an etch stopper ES is formed to protect the semiconductor layer 37 from the etching liquid flowing through the separated portion between the source electrode 25 and the drain electrode 35. [

One end of the gate wiring 13 includes a gate pad 17 for receiving a gate signal from the outside. The gate pad 17 is in contact with the gate pad terminal 19 through the gate pad contact hole 71 penetrating the gate insulating film 11 and the protective film 41. On the other hand, at one end of the data line 23, a data pad 27 for receiving a pixel signal from the outside is included. The data pad 27 is in contact with the data pad terminal 29 through the data pad contact hole 73 penetrating the protective film 41. [

The pixel electrode 45 is connected to the drain electrode 35 on the gate insulating film 11. The common electrode 55 is formed so as to overlap the pixel electrode 45 with a protective film 41 covering the pixel electrode 45 interposed therebetween. An electric field is formed between the pixel electrode 45 and the common electrode 55, and the liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

Hereinafter, a process for fabricating an FFS-type thin film transistor substrate including an oxide semiconductor according to the prior art will be described. FIGS. 3A to 3G are cross-sectional views taken along line I-I 'of FIG. 1, and show a process of manufacturing a thin film transistor substrate of a fringe field method according to the prior art.

A gate metal is deposited on the transparent lower substrate (1). The gate metal is patterned in a first mask process to form gate elements. The gate element includes a gate wiring 13, a gate electrode 15 that branches off from the gate wiring 13, and a gate pad 17 formed at one end of the gate wiring 13. (Fig. 3A)

The gate insulating film 11 is entirely coated on the substrate 1 on which the gate materials are formed. The oxide semiconductor material is then deposited. In the second mask process, the oxidized semiconductor material is patterned to form the semiconductor layer 37. (Figure 3b)

An insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is applied over the entire surface of the substrate on which the semiconductor layer 37 is formed. An insulating material is patterned by a third mask process to form an etch stopper (ES). It is preferable that the etch stopper ES is formed so as to be located at the central portion of the semiconductor layer 37 to be formed on the gate electrode 15. [ (Figure 3c)

A source-drain metal is deposited on the substrate 1 on which the semiconductor layer 37 is formed. In a fourth mask process, the source-drain metal is patterned to form source-drain elements. The source-drain element is connected to the data line 23 perpendicularly intersecting the gate line 13, the data pad 27 formed at one end of the data line 23 and the data line 23, And a drain electrode 35 which is in contact with the other side of the semiconductor layer 37 and faces the source electrode 25. Particularly, although the source electrode 25 and the drain electrode 35 are physically separated from each other, the source electrode 25 and the drain electrode 35 are connected via the semiconductor layer 37 overlapping the gate electrode 15 with the gate insulating film 11 therebetween. . Although not shown in the drawing, an active layer that forms a channel between the source electrode and the drain electrode is formed in a portion of the surface of the semiconductor layer 37 that is not covered with the etch stopper ES, and a source electrode and a drain electrode, And may further include an ohmic contact layer for allowing ohmic contact.

The semiconductor layer 37 is etched by the etchant etching between the source electrode 25 and the drain electrode 35 in the process of patterning the source electrode 25 and the drain electrode 35 A back etch phenomenon occurs. In the case where the semiconductor layer 37 includes an amorphous semiconductor material, even if a back-etch occurs, the characteristics of the device are not greatly affected. However, in the case where the semiconductor layer 37 includes an oxidized semiconductor material, if the back etch occurs, the stability of the device may be deteriorated. Therefore, it is preferable to include an etch stopper (ES) when forming a channel layer with an oxidized semiconductor material. (Fig. 3d)

A transparent conductive material such as ITO (Indium Tin Oxide) is deposited on the entire surface of the substrate 1 on which the source-drain element is formed. In the fifth mask process, a transparent conductive material is patterned to form the pixel electrode 45. [ The pixel electrode 45 is formed so as to cover and cover a part of the drain electrode 35. The pixel electrode 45 is preferably formed in a substantially rectangular shape in the pixel region formed by intersecting the gate wiring 13 and the data wiring 23. [ (Fig. 3E)

The protective film 41 is applied to the entire surface of the substrate 1 on which the pixel electrode 45 is formed. In the sixth mask process, the protective film 41 is patterned to form a data pad contact hole 73 exposing a part of the data pad 27. [ At the same time, the protective film 41 and the gate insulating film 11 are patterned to form a gate pad contact hole 71 exposing a part of the gate pad 17. (Figure 3f)

A transparent conductive material such as ITO is again deposited on the protective film 41. In the seventh mask process, the transparent conductive material is patterned to form the common electrode 55, the gate pad terminal 19, and the data pad terminal 29. The common electrode 55 is formed so as to overlap the pixel electrode 45 with the protective film 41 therebetween. In particular, they are formed as bars arranged in parallel at regular intervals. The gate pad terminal 19 contacts the gate pad 17 exposed through the gate pad contact hole 71. The data pad terminal 29 is in contact with the data pad 27 exposed through the data pad contact hole 73. (Figure 3g)

Though not shown in the drawing, the thin film transistor substrate on which the pixel electrode 55 and the common electrode 55 are formed is transferred to the alignment film processing chamber to apply the alignment film. Then, the liquid crystal layer is coated and adhered to the color filter substrate to complete the liquid crystal display panel.

In this manner, seven mask processes are used to fabricate a thin film transistor substrate for an FFS type liquid crystal display including an oxide semiconductor. Even when fabricating an FFS type thin film transistor substrate including an amorphous semiconductor which does not require an etch stopper ES, at least six mask processes are required. The more the mask process is performed, the more complicated the manufacturing process becomes, and the higher the possibility of occurrence of defects becomes. Therefore, it is an important problem to simplify the process of manufacturing the thin film transistor substrate which includes the largest number of components in the liquid crystal display device.

It is an object of the present invention to provide a method of manufacturing a thin film transistor substrate including an oxide semiconductor by a six mask process and a thin film transistor substrate including the oxide semiconductor by the method. It is another object of the present invention to provide a method of simplifying a manufacturing process of a thin film transistor substrate of a fringe field switching type by selectively processing an oxide semiconductor layer to form a channel layer and a pixel electrode layer by a single mask process, And a fringe field switching type thin film transistor substrate including a semiconductor.

In order to accomplish the object of the present invention, a thin film transistor substrate including an oxide semiconductor layer according to the present invention includes a substrate; A gate element formed over the substrate; A gate insulating film covering the gate element; A thin film transistor including a channel layer comprising a metal oxide semiconductor material formed to overlap with a portion of the gate element above the gate insulating layer; And a pixel electrode formed on the gate insulating layer and spaced apart from the channel layer in the horizontal direction and connected to the thin film transistor, the pixel electrode including the metal oxide semiconductor material.

And the semiconductor channel layer and the pixel electrode are formed on the same layer on the gate insulating film.

The metal oxide semiconductor material may include at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

The thin film transistor includes: a gate electrode which branches off from the gate wiring; The channel layer overlapping the gate wiring above the gate insulating film; An etch stopper covering an upper central portion of the channel layer; A source electrode in contact with one side of the channel layer exposed by the etch stopper; And a drain electrode which is in contact with the other side of the channel layer, which is opposed to the source electrode and is exposed to the etch stopper, and which is in contact with the pixel electrode.

Wherein the drain electrode is in contact with the upper surface and the etching side of the other side of the channel layer and the other side is in contact with the etched side surface and the upper surface of the one side of the pixel electrode.

A protective film covering the thin film transistor and the pixel electrode; A common electrode overlapping the pixel electrode on the protective film and having a plurality of segment shapes; And a common wiring connecting the common electrode and proceeding in parallel with the gate wiring.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate including an oxide semiconductor layer, the method comprising: forming a gate element on a substrate by a first mask process; Forming a gate insulating film covering the gate element; Forming a channel layer and a pixel electrode by patterning the metal oxide semiconductor material on the gate insulating layer and performing a second mask process; And forming a thin film transistor including the channel layer on the gate insulating layer.

The metal oxide semiconductor material may include at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

The second mask process includes a first photoresist having a first thickness corresponding to the size of the channel layer by applying a photoresist on the metal oxide semiconductor material and patterning with a halftone mask and a second photoresist corresponding to the size of the pixel electrode Forming a second photoresist having a second thickness that is thinner than the first photoresist; Ashing the first and second photoresist so that all of the second photoresist is removed and the first photoresist remains a part of the thickness; Wherein the channel layer is protected by the first photoresist so as to selectively conduct only the exposed pixel electrodes while maintaining a semiconductor state.

The step of selectively conducting only the pixel electrode includes at least one of a plasma treatment and an ultraviolet treatment.

The forming of the thin film transistor may include forming an etch stopper covering the central portion of the channel layer by applying an insulating material on the channel layer and patterning the substrate by a third mask process; A source electrode is formed on the etch stopper and is patterned by a fourth mask process. The source electrode is in contact with one side of the channel layer exposed by the etch stopper. The source electrode is opposed to the source electrode, And forming a drain electrode in contact with the other side of the channel layer exposed to the pixel electrode and in contact with the pixel electrode.

Applying a protective film covering the thin film transistor and the pixel electrode, and patterning the gate insulating film and the protective film by a fifth mask process to expose a part of the gate element and a part of the source-drain element; And forming a common electrode having a plurality of rod shapes overlapping the pixel electrode by applying a transparent conductive material on the protective film and patterning the sixth mask process.

The thin film transistor substrate including the oxide semiconductor according to the present invention includes six mask processes by forming the semiconductor channel layer and the pixel electrode layer using the same material and using a selective process. The number of mask processes is reduced as compared with the conventional technique, the manufacturing cost is low, and the manufacturing time is shortened. Further, by using the same material for the channel layer and the pixel electrode, it is easier to supply and receive the material, and the cost can be reduced. In the fringe field type thin film transistor substrate having a structure in which the auxiliary storage capacity is increased in proportion to the size of the pixel, the oxide semiconductor capable of driving the large capacity auxiliary storage in a small size is used, There is an advantage that a display device can be provided.

1 is a plan view showing a thin film transistor substrate included in a conventional fringe field type liquid crystal display device.
FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the cutting line I-I '. FIG.
FIGS. 3A to 3G are cross-sectional views taken along line I-I 'of FIG. 1, illustrating a process for fabricating a fringe field type thin film transistor substrate according to a conventional technique.
4 is a plan view showing a thin film transistor substrate included in a fringe field type liquid crystal display device including an oxide semiconductor channel layer according to the present invention.
5 is a cross-sectional view of the thin film transistor substrate shown in FIG. 4 taken along a perforated line II-II ';
FIGS. 6A to 6G are cross-sectional views illustrating a process of fabricating a fringe field type thin film transistor substrate including an oxide semiconductor channel layer according to the present invention, taken along line II-II 'of FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings 4, 5, and 6A to 6G. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

4 is a plan view of a thin film transistor substrate included in a fringe field type liquid crystal display device including an oxide semiconductor layer according to the present invention. FIG. 5 is a cross-sectional view of the thin film transistor substrate shown in FIG. 4 taken along a perforated line II-II '.

4 and 5, the thin film transistor substrate according to the present invention includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB, And a thin film transistor T formed thereon. Further, the thin film transistor substrate defines a pixel region with an intersection structure of a gate line GL and a data line DL. The pixel region includes a pixel electrode PXL and a common electrode COM formed with a protective film PAS therebetween so as to form a fringe field. Here, the pixel electrode PXL has a substantially rectangular shape corresponding to the pixel region, and the common electrode COM is formed into a plurality of parallel strips.

The common electrode COM branches off from the common line CL arranged in parallel with the gate line GL. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T opposes the source electrode S and the source electrode S branched from the gate electrode G branched from the gate line GL, the data line DL, and the pixel electrode PXL, And an oxide semiconductor channel layer A which overlaps the gate electrode G on the gate insulating film GI and forms a channel between the source electrode S and the drain electrode D do.

The oxide semiconductor material preferably further includes an etch stopper (ES) for protecting the upper surface from the etchant to ensure stability of the device. More specifically, it is preferable to form the etch stopper ES so as to protect the oxide semiconductor channel layer A from the etchant flowing through the separated portion between the source electrode S and the drain electrode D.

The source electrode S is in contact with one side of the oxide semiconductor channel layer A exposed by the etch stopper ES. The drain electrode D has a structure in which one side portion is in contact with the upper surface and the etching side of the other side of the oxide semiconductor channel layer A and the other side is in contact with the etched side surface and the upper surface on one side of the pixel electrode PXL .

At one end of the gate wiring GL, a gate pad GP for receiving a gate signal from the outside is formed. The gate pad GP contacts the gate pad terminal GPT through the gate pad contact hole GPH passing through the gate insulating film GI and the protective film PAS. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the protective film PAS.

The pixel electrode PXL is formed in the same layer as the semiconductor channel layer A. [ In particular, the pixel electrode PXL basically includes the same metal oxide material as the semiconductor channel layer A. For example, materials such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). However, the semiconductor channel layer (A) and the pixel electrode (PXL) have different properties. The semiconductor channel layer (A) has a property that the carrier concentration is contained in the metal oxide semiconductor material at the level of the semiconductor material. On the other hand, the pixel electrode PXL has a characteristic in which the carrier concentration is increased to the level of the conductor through a process of selectively plasma-oxidizing the metal oxide material or ultraviolet light (UV).

Therefore, the pixel electrode PXL is formed on the gate insulating film GI. And a drain electrode D which is formed after that and in contact with the upper surface of the other side of the semiconductor channel layer A has a structure in which the drain electrode D is in direct contact with the etched side surface and the upper surface of one side of the pixel electrode PXL.

On the other hand, the common electrode COM is formed so as to overlap the pixel electrode PXL with the protective film PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode (PXL) and the common electrode (COM), and the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate rotate due to dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

Particularly, when the semiconductor channel layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to its high charge mobility. Furthermore, in the case of the fringe field method, the region where the pixel electrode PXL overlaps with the common electrode COM forms the storage capacitor, and as the size of the pixel increases, the storage capacitor increases in proportion thereto. Therefore, the fringe field type thin film transistor substrate including the oxide semiconductor according to the present invention has an advantage of providing a high-definition flat panel display device having a large surface.

Hereinafter, a process for fabricating a fringe field type thin film transistor substrate including an oxide semiconductor according to the present invention will be described. 6A to 6G are cross-sectional views taken along line II-II 'of FIG. 4, and show a process of manufacturing a thin film transistor substrate of a fringe field type according to the present invention.

A gate metal is deposited on a transparent substrate (SUB). The gate metal includes a low-resistance metal material such as aluminum (Al) or copper (Cu). The gate metal is patterned in a first mask process to form gate elements. The gate element includes a gate wiring GL extending in the lateral direction on the substrate SUB, a gate electrode G branching from the gate wiring GL to the pixel region, and a gate pad (not shown) formed at one end of the gate wiring GL GP). (Fig. 6A)

An insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is applied on the entire surface of the substrate SUB on which the gate element is formed to form the gate insulating film GI. Then, a metal oxide semiconductor layer (MO) is applied over the entire surface of the gate insulating film (GI). The metal oxide semiconductor layer MO is patterned by the second mask process to form the semiconductor channel layer A and the pixel electrode PXL. The semiconductor channel layer A is formed so as to overlap the gate electrode G on the gate insulating film GI. The pixel electrode PXL preferably has a polygonal shape corresponding to the size and shape of the pixel region formed by intersecting the gate line GL and the data line DL.

This process will be described in detail as follows. A photoresist is applied on the metal oxide semiconductor layer MO and a first photoresist PR1 corresponding to the size of the semiconductor channel layer A is formed using a half-tone mask and a first photoresist PR1 corresponding to the size of the pixel electrode PXL The second photoresist PR2 corresponding to the size of the second photoresist PR2 is formed. At this time, the first photoresist PR1 should be thicker than the second photoresist PR2. For example, it is preferable that the first photoresist PR1 has a thickness at least about 1.5 times as thick as the second photoresist PR2. (Fig. 6B)

The metal oxide semiconductor layer MO is patterned using the first photoresist PR1 and the second photoresist PR2 as a mask to form the semiconductor channel layer A and the pixel electrode PXL. Then, the first photoresist PR1 and the second photoresist PR2 are processed by an ashing process. When the ashing process is performed until all the second photoresist PR2 is removed, the first photoresist PR1 remains only on the semiconductor channel layer A, and the pixel electrode PXL is exposed. In this state, the pixel electrode PXL exposed by plasma or ultraviolet rays is processed. Then, the oxygen contained in the metal oxide semiconductor material escapes from the pixel electrode PXL, and oxygen deficiency is induced. As a result, the pixel electrode PXL is turned into a transparent conductor. That is, although the semiconductor channel layer A and the pixel electrode PXL are formed of a metal oxide semiconductor material, a process of selectively conducting only the pixel electrode PXL may be accomplished in the second mask process. (Fig. 6C)

After the first photoresist PR1 is removed, an insulating material is deposited on the substrate SUB including the semiconductor channel layer A and the pixel electrode PXL. The insulating material may comprise silicon oxide (SiOx) or silicon nitride (SiNx). An insulating material is patterned by a third mask process to form an etch stopper (ES) covering a part of the center of the semiconductor channel layer (A). The etch stopper (ES) protects the semiconductor channel layer (A) from damaging the etchant in the process of forming the source-drain electrode formed in the next process. (Fig. 6D)

The source-drain metal is entirely coated on the substrate SUB on which the etch stopper ES is formed. The source-drain metal is patterned by a fourth mask process to form source-drain elements. The source-drain element includes a data line DL crossing the gate line GL vertically with a gate insulating film GI therebetween, a data pad DP formed at one end of the data line DL, DL and a drain electrode D which is in contact with the other side of the semiconductor channel layer A and opposes the source electrode S, do. Although the source electrode S and the drain electrode D are physically separated from each other, the structure in which the source electrode S and the drain electrode D are connected via the semiconductor channel layer A overlapping the gate electrode G with the gate insulating film GI interposed therebetween . The source electrode S is in contact with one side of the semiconductor channel layer A exposed by the etch stopper ES. Particularly, in the drain electrode D, one side is in contact with the upper surface and the etching side of the other side of the semiconductor channel layer A, and the other side is in direct contact with the etched side surface and the upper surface of the side of the pixel electrode PXL Structure. (Fig. 6E)

In the process of patterning the source electrode S and the drain electrode D described below, if the etch stopper ES is not provided, the semiconductor layer A (A) is etched by the etchant between the source electrode S and the drain electrode D, ) Is etched, a back etch phenomenon occurs. When the semiconductor layer (A) contains an amorphous semiconductor material, even if a back etch occurs, the characteristics of the device are not greatly affected. However, when the semiconductor layer (A) includes a metal oxide semiconductor material, if the back etch occurs, the stability of the device may be problematic. Therefore, it is preferable to include an etch stopper (ES) when the channel layer is formed of a metal oxide semiconductor material.

A protective film PAS is deposited on the entire surface of the substrate SUB on which the source-drain element is formed, using a material such as silicon nitride (SiNx) or silicon oxide (SiOx). A passivation film PAS is patterned by a fifth mask process to form a data pad contact hole DPH exposing the data pad DP. Subsequently, the gate insulating film GI under the protective film PAS is patterned to form a gate pad contact hole GPH exposing the gate pad GP. (Figure 6f)

A transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is deposited on the substrate SUB on which the contact holes GPH and DPH are formed. In the sixth mask process, the transparent conductive material is patterned to form the common electrode COM and the common wiring CL. It is preferable that the common electrode COM is formed so that a plurality of rod-like electrodes parallel to each other in a pixel region formed by intersecting the gate wiring GL and the data wiring DL are arranged at regular intervals. At the same time, a gate pad terminal GPT in contact with the gate pad GP through the gate pad contact hole GPH and a data pad terminal DPT in contact with the data pad DP through the data pad contact hole DPH, ). The common wiring CL runs in parallel with the gate wiring GL and is formed so as to traverse one side or the central portion of the pixel region. The common electrodes COM arranged in a plurality of line segments are connected to the common line CL to receive a common voltage. (Fig. 6G)

In the embodiment of the present invention described above, the shape of the pixel electrode PXL is described in the form of a rectangle. However, if necessary, the shape of the pixel electrode PXL may have a rectangular shape with a central portion coupled with a rectangle of two planar implants. In this case, the common electrode COM preferably has a structure in which a plurality of rod electrodes having a broken line shape corresponding to the bent shape of the pixel electrode PXL are arranged in parallel.

Since the metal oxide semiconductor material has a high charge mobility, it can be applied not only to the case of driving a high capacity auxiliary capacitor such as a thin film transistor for a fringe field type liquid crystal display, but also to an organic light emitting display device requiring a large current driving.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

7, T: thin film transistor 1, SUB: substrate
13, GL: gate wiring 53, CL: common wiring
23, DL: data line 45, PXL: pixel electrode
55, COM: common electrode 17, GP: gate pad
27, DP: data pad 19, GPT: gate pad terminal
29, DPT: Data pad terminal 71, GPH: Gate pad contact hole
73, DPH: Data pad contact hole
15, G: gate electrode 25, S: source electrode
35, D: drain electrode 37, A: semiconductor channel layer
11, GI: gate insulating film 41, PAS: protective film
ES: Etch stopper MO: Metal oxide

Claims (12)

Board;
A gate element formed over the substrate;
A gate insulating film covering the gate element;
A thin film transistor including a channel layer comprising a metal oxide semiconductor material formed to overlap with a portion of the gate element above the gate insulating layer; And
And a pixel electrode formed on the gate insulating layer and spaced apart from the channel layer in a horizontal direction and connected to the thin film transistor, the pixel electrode including the metal oxide semiconductor material.
The method according to claim 1,
Wherein the semiconductor channel layer and the pixel electrode are formed on the same layer over the gate insulating film.
The method according to claim 1,
Wherein the metal oxide semiconductor material comprises at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).
The thin film transistor according to claim 1,
A gate electrode that branches off from the gate wiring;
The channel layer overlapping the gate wiring above the gate insulating film;
An etch stopper covering an upper central portion of the channel layer;
A source electrode in contact with one side of the channel layer exposed by the etch stopper; And
And a drain electrode which is in contact with the other side of the channel layer which is exposed to the etch stopper and faces the source electrode, and which is in contact with the pixel electrode.
5. The method of claim 4,
Wherein the drain electrode is in contact with the upper surface and the etching side of the other side of the channel layer and the other side is in contact with the etched side surface and the upper surface of the one side of the pixel electrode.
The method according to claim 1,
A protective film covering the thin film transistor and the pixel electrode;
A common electrode overlapping the pixel electrode on the protective film and having a plurality of segment shapes; And
And a common wiring connecting the common electrode and proceeding in parallel with the gate wiring.
Forming a gate element in a first mask process on the substrate;
Forming a gate insulating film covering the gate element;
Forming a channel layer and a pixel electrode by patterning the metal oxide semiconductor material on the gate insulating layer and performing a second mask process; And
And forming a thin film transistor including the channel layer on the gate insulating layer.
8. The method of claim 7,
Wherein the metal oxide semiconductor material comprises at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).
8. The method of claim 7,
A first photoresist having a first thickness corresponding to a size of the channel layer, the first photoresist corresponding to the size of the pixel electrode and the second photoresist corresponding to the size of the pixel electrode; Forming a second photoresist having a thin second thickness;
Ashing the first and second photoresist so that the second photoresist is all removed and the first photoresist remains a part of the thickness;
Wherein the channel layer is selectively protected by the first photoresist so as to selectively conduct only the exposed pixel electrode while maintaining a semiconductor state.
10. The method of claim 9,
Wherein the step of selectively conducting only the pixel electrode comprises at least one of a plasma treatment and an ultraviolet ray treatment.
8. The method of claim 7, wherein forming the thin film transistor comprises:
Applying an insulating material on the channel layer and patterning the mask layer by a third mask process to form an etch stopper covering a central portion of the channel layer; And,
A source electrode that is in contact with one side of the channel layer exposed by the etch stopper and a source electrode that is opposite to the source electrode and is exposed to the etch stopper; And forming a drain electrode in contact with the other side of the channel layer and in contact with the pixel electrode.
12. The method of claim 11,
Applying a protective film covering the thin film transistor and the pixel electrode, and patterning the gate insulating film and the protective film by a fifth mask process to expose a part of the gate element and a part of the source-drain element; And
Applying a transparent conductive material on the passivation layer, and patterning the sixth mask process to form a common electrode having a plurality of rod shapes overlapping the pixel electrode.

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