KR102022523B1 - Thin Film Transistor Substrate Having Metal Oxide Semiconductor And Method For Manufacturing The Same - Google Patents

Thin Film Transistor Substrate Having Metal Oxide Semiconductor And Method For Manufacturing The Same Download PDF

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KR102022523B1
KR102022523B1 KR1020120053796A KR20120053796A KR102022523B1 KR 102022523 B1 KR102022523 B1 KR 102022523B1 KR 1020120053796 A KR1020120053796 A KR 1020120053796A KR 20120053796 A KR20120053796 A KR 20120053796A KR 102022523 B1 KR102022523 B1 KR 102022523B1
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electrode
source
etch stopper
drain
gate electrode
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KR1020120053796A
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KR20130129723A (en
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남승희
류순성
송태준
김남국
문태형
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엘지디스플레이 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention relates to a thin film transistor substrate for a flat panel display device having a metal oxide semiconductor and a method of manufacturing the same. A thin film transistor substrate including an oxide semiconductor layer according to the present invention includes a gate electrode formed on the substrate; A gate insulating film covering the gate electrode; A semiconductor channel layer overlapping the gate electrode on the gate insulating layer; An etch stopper overlapping a portion of a central portion of the gate electrode on the semiconductor channel layer; A first source electrode in contact with one side wall of the etch stopper and in contact with one side of the semiconductor channel layer; And a first drain electrode facing the first source electrode and in contact with the other side wall of the etch stopper and in contact with the other side of the semiconductor channel layer.

Description

Thin Film Transistor Substrate Having Metal Oxide Semiconductor And Method For Manufacturing The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) substrate for a flat panel display device having a metal oxide semiconductor and a method of manufacturing the same. In particular, the present invention relates to a thin film transistor substrate for a flat panel display including a metal oxide semiconductor having a parasitic capacitance between the gate electrode and the source electrode minimized by matching the side boundary of the etch stopper with the boundary of the source and drain electrodes. It is about.

The field of display devices has rapidly changed to thin, light and large-area flat panel display devices (FPDs), replacing bulky cathode ray tubes (CRTs). Flat panel displays include Liquid Crystal Display Devices (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Display Devices (OLEDs), and Electrophoretic Display Devices. : ED).

The active liquid crystal display, the organic light emitting display, and the electrophoretic display include a thin film transistor substrate on which thin film transistors are arranged in a pixel region arranged in a matrix manner. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field for driving the liquid crystal.

The vertical field type liquid crystal display drives a liquid crystal of TN (Twistred Nematic) mode by a vertical electric field formed between a pixel electrode and a common electrode disposed to face the upper and lower substrates. Such a vertical field type liquid crystal display device has an advantage of large aperture ratio, but has a disadvantage that the viewing angle is as narrow as 90 degrees.

In a horizontal field type liquid crystal display, a horizontal electric field is formed between a pixel electrode and a common electrode disposed in parallel to a lower substrate to drive a liquid crystal in an in-plane switching (IPS) mode. The IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. Specifically, in the IPS mode liquid crystal display, the gap between the common electrode and the pixel electrode is wider than the gap between the upper and lower substrates in order to form an in-plane field, and the common electrode and the pixel are used to obtain an electric field having an appropriate intensity. The electrode is formed in the form of a strip having a constant width. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal on the pixel electrode and the common electrodes having the width. That is, the liquid crystal molecules on the pixel electrode and the common electrode are not driven and maintain their initial arrangement. Liquid crystals that maintain their initial state do not transmit light, which causes a decrease in the aperture ratio and transmittance.

In order to improve the disadvantage of the IPS mode liquid crystal display device, a fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed. A FFS type liquid crystal display device includes a common electrode and a pixel electrode with an insulating film interposed therebetween in each pixel region, and the gap between the common electrode and the pixel electrode is formed to be narrower than the gap between the upper and lower substrates. To form a parabolic fringe field. All of the liquid crystal molecules interposed between the upper and lower substrates by the fringe field may operate to obtain an improved aperture ratio and transmittance.

Hereinafter, an FFS thin film transistor substrate will be described with reference to FIGS. 1 and 2. 1 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device. FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II ′.

1 and 2 include a gate line GL and a data line DL intersecting each other with a gate insulating layer GI interposed therebetween on a lower substrate SUB, and a thin film transistor formed at each intersection thereof. T). In addition, the thin film transistor substrate defines a pixel area with a cross structure of the gate line GL and the data line DL. The pixel region includes the pixel electrode PXL and the common electrode COM formed with the passivation layer PAS therebetween to form a fringe field. The pixel electrode PXL has a substantially rectangular shape corresponding to the pixel area, and the common electrode COM is formed in a plurality of parallel band shapes.

The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL.

The thin film transistor T keeps the pixel signal of the data line DL charged in the pixel electrode PXL in response to the gate signal of the gate line GL. To this end, the thin film transistor T faces the gate electrode G branched from the gate line GL, the source electrode S branched from the data line DL, and the source electrode S, and faces the pixel electrode PXL. And a drain electrode D connected to the gate electrode and a semiconductor layer A overlapping the gate electrode G on the gate insulating layer GI and forming a channel between the source electrode S and the drain electrode D.

When the semiconductor layer A is formed of an oxide semiconductor material, it is advantageous to a large area thin film transistor substrate having a large charge capacity due to its high charge mobility property. However, the oxide semiconductor material preferably further includes an etch stopper (ES) on the upper surface of the oxide semiconductor material to protect the etching solution. Specifically, it is preferable that the etch stopper ES is formed to protect the semiconductor layer A from the etching liquid flowing through the separated portion between the source electrode S and the drain electrode D. FIG.

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad terminal GPT through the gate pad contact hole GPH passing through the gate insulating layer GI and the passivation layer PAS. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the passivation layer PAS.

The pixel electrode PXL is connected to the drain electrode D on the gate insulating film GI. The common electrode COM is formed to overlap the pixel electrode PXL with the passivation layer PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode PXL and the common electrode COM, and the liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate by dielectric anisotropy. In addition, light transmittance through the pixel region varies according to the degree of rotation of the liquid crystal molecules, thereby implementing grayscale.

A portion in which the thin film transistor T is formed in the thin film transistor substrate having such a structure will be described in more detail. 3 is an enlarged cross-sectional view of a portion of a thin film transistor in an FFS thin film transistor substrate.

Referring to FIG. 3, a gate insulating film GI, a semiconductor channel layer A, and an etch stopper ES are interposed between the gate electrode G and the source electrode S. In particular, the etch stopper ES is to prevent the semiconductor channel layer A from being damaged by the etchant in the process of separating the source electrode S and the drain electrode D from each other. Therefore, one end portion of the source electrode S is formed to overlap one side of the etch stopper ES. The size of the parasitic capacitance between the source electrode S and the gate electrode G and the size of the Cgs are determined according to the size of the overlap region GS1 of the source electrode S and the gate electrode G. Similarly, the size of the parasitic capacitance Cgd between the drain electrode D and the gate electrode G is determined according to the size of the overlap region GD1 of the drain electrode D and the gate electrode G. FIG.

The size of the region where the gate electrode G and the source electrode S overlap in the FFS thin film transistor will be described in comparison with the overlap region in the IPS thin film transistor. 4 is an enlarged cross-sectional view of a portion of a thin film transistor in an IPS thin film transistor substrate.

Referring to FIG. 4, an etch stopper ES is not formed in the thin film transistor T formed on the IPS thin film transistor substrate. The oxide semiconductor used in the FFS method uses an etch stopper because it is sensitive to the source-drain etchant, but the amorphous silicon used in the IPS method does not use an etch stopper because it is not sensitive to the source-drain etchant. As shown in FIG. 4, the gate electrode G and the source electrode S are interposed with a gate insulating film GI and a semiconductor channel layer A interposed therebetween. One end portion of the source electrode S is formed to overlap one side of the gate electrode G. The source electrode S is formed according to the size of the overlapping region GS2 of the source electrode S and the gate electrode G. FIG. The size of the parasitic capacitance Cgs between the gate electrode and the gate electrode G is determined. Similarly, the size of the parasitic capacitance Cgd between the drain electrode D and the gate electrode G is determined according to the size of the overlap region GD2 of the drain electrode D and the gate electrode G. FIG.

As can be seen by comparing FIG. 3 with FIG. 4, the size of the overlapping region GS1 of the source electrode S and the gate electrode G in the FFS method is the source electrode S and the gate electrode G in the IPS method. It can be seen that the size is larger than the size of the overlap region GS2. That is, the parasitic capacitance between the source electrode S and the gate electrode G in the FFS method, the size of Cgs is larger than the parasitic capacitance between the source electrode S and the gate electrode G in the IPS method, and the size of Cgs. Big.

As such, when the parasitic capacitance between the source electrode S and the gate electrode G increases, the driving voltage applied between the pixel electrode PXL and the common electrode COM may increase, which may adversely affect image quality. In other words, the FFS method has an etch stopper (ES), which is more stable than the IPS method, but the parasitic capacitance between the gate electrode (G) and the source electrode (G) and Cgs are increased due to the etch stopper (ES). Can have

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor substrate including a thin film transistor having an etch stopper and a self-aligned source-drain electrode, and a method of manufacturing the same. Another object of the present invention is to provide a thin film transistor substrate including a thin film transistor formed to self-align the etch stopper and the source-drain electrode to minimize parasitic capacitance between the gate electrode and the source electrode, and a method of manufacturing the same. It is still another object of the present invention to provide a thin film transistor substrate manufacturing method for self-aligning and manufacturing an etch stopper and a source-drain electrode without an additional mask process.

In order to achieve the object of the present invention, a thin film transistor substrate comprising an oxide semiconductor layer according to the present invention, the gate electrode formed on the substrate; A gate insulating film covering the gate electrode; A semiconductor channel layer overlapping the gate electrode on the gate insulating layer; An etch stopper overlapping a portion of a central portion of the gate electrode on the semiconductor channel layer; A first source electrode in contact with one side wall of the etch stopper and in contact with one side of the semiconductor channel layer; And a first drain electrode facing the first source electrode and in contact with the other side wall of the etch stopper and in contact with the other side of the semiconductor channel layer.

A second source electrode stacked on the first source electrode at a distance from the sidewall of the etch stopper; And a second drain electrode stacked on the first drain electrode at a predetermined distance from the other sidewall of the etch stopper.

The size of an area where the first source electrode and the gate electrode overlap with the semiconductor channel layer therebetween is not larger than an area of the gate electrode that does not overlap outwardly from the sidewall of the etch stopper. .

The size of the region where the first drain electrode and the gate electrode overlap with the semiconductor channel layer interposed therebetween is not larger than the region of the gate electrode that does not overlap outwardly from the other sidewall of the etch stopper. .

In addition, a method of manufacturing a thin film transistor substrate including an oxide semiconductor layer according to the present invention includes the steps of depositing a gate metal on the substrate and patterning with a first mask to form a gate electrode; Stacking a gate insulating film and a semiconductor material to cover the gate electrode, and patterning the semiconductor material with a second mask to form a semiconductor channel layer overlapping the gate electrode; Depositing an insulating material over the semiconductor channel layer and patterning with a third mask to form an etch stopper overlying a portion of the central portion of the gate electrode on the semiconductor channel layer, leaving a first photoresist on the etch stopper; A first source metal and a second source metal stacked on the gate insulating layer, the semiconductor channel layer, the etch stopper, and the first photoresist, and patterned with a fourth mask to be in contact with one side of the semiconductor channel layer. Forming a drain electrode in contact with an electrode and the other side of the semiconductor channel layer; And stripping the first photoresist to self-align the source-drain electrodes with the sidewalls of the etch stopper.

The forming of the source-drain electrode may include applying a second photoresist on the second source metal, and patterning the second photoresist to form a fourth mask so that portions except for the shape of the source-drain electrode are completely removed. Forming the second photoresist such that a portion where the intact shape of the source-drain electrode is to be formed has a black tone region and a portion where the portion of the source-drain electrode remains has a half-tone region; Patterning the second source metal and the first source metal using the second photoresist as a mask, and exposing a central portion of the first photoresist between the source and drain electrodes; Ashing the second photoresist to expose the second source metal in the half-tone region of the second photoresist; And removing the exposed second source metal using the ashed second photoresist as a mask.

The half-tone region is a region overlapping a predetermined distance from one end side of the etch stopper toward the center at the one side where the source electrode is located, and the contacting source electrode at the one end side of the etch stopper. And an intermediate region between one end side of the semiconductor channel layer.

The half-tone region is in contact with the drain electrode at the other end side of the etch stopper, the region overlapping a distance from the other end side of the etch stopper toward the center at the other side where the drain electrode is located. It further comprises an intermediate region between the other end side of the semiconductor channel layer.

In the step of stripping the first photoresist,

The first source metal overlapped with the first photoresist is removed by a lift-off method, so that the first source metal of the source-drain electrode is self-aligned with the sidewall of the etch stopper.

Forming a drain contact hole exposing a portion of the drain electrode by applying a passivation layer covering the source-drain electrode and patterning it with a fifth mask; And forming a pixel electrode in contact with the drain electrode through the drain contact hole by applying a transparent conductive material on the passivation layer and patterning it with a sixth mask.

The thin film transistor substrate including the oxide semiconductor according to the present invention has a shape in which one end of the source-drain electrode is self-aligned with the edge of the etch stopper. In other words, the source-drain electrode has a structure overlapping the gate electrode with the semiconductor channel layer interposed therebetween without overlapping the etch stopper. Therefore, the overlapping area of the gate electrode and the source electrode can be minimized. As a result, the parasitic capacitance formed between the gate electrode and the source electrode can be limited to a minimum, so that the load on the data wiring can be reduced. In addition, since the magnitude of the voltage difference driving the pixel can be reduced, a flicker characteristic can be improved to provide a high quality screen. In the present invention, a half-tone mask is used for self-aligning the etch stopper and the source-drain electrode, and a lift-off process is used so that no additional mask process is required. That is, a higher quality thin film transistor substrate can be obtained with the same process yield and the same process time.

1 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device.
FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II ′.
3 is an enlarged cross-sectional view of a portion of a thin film transistor in an FFS thin film transistor substrate;
4 is an enlarged cross-sectional view of a portion of a thin film transistor in an IPS type thin film transistor substrate;
5A to 5J are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1 and 5A to 5J. Like numbers refer to like elements throughout. In the following description, when it is determined that the detailed description of the known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In the case of the present invention, the shape seen from the plane does not differ significantly from that of the prior art. Therefore, the top view of the present invention refers to FIG. 1 as it is. Features of the present invention are shown in the cross-sectional views of FIGS. 5A-5H. 5A to 5H are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device according to the present invention.

A gate metal material is coated on the transparent substrate SUB. The gate metal includes a low resistive metal material such as aluminum (Al) or copper (Copper) Cu. The gate metal material is patterned to form a gate element including the gate electrode G by using a first mask process. The gate element may include a gate line GL running in a horizontal direction on the substrate SUB, a gate electrode G branching from the gate line GL to a pixel region, and a gate pad formed at one end of the gate line GL. GP). In FIG. 5A, only the portion of the thin film transistor T is enlarged for convenience. (FIG. 5A)

On the substrate SUB on which the gate element is formed, an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is coated on the entire surface to form a gate insulating film GI. Subsequently, a metal oxide semiconductor layer is coated on the entire surface of the gate insulating film GI. In the second mask process, the metal oxide semiconductor layer is patterned to form the semiconductor channel layer A. FIG. It is preferable that the semiconductor channel layer A has a shape covering the gate electrode G. FIG. (FIG. 5B)

An insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is coated on the entire surface of the substrate on which the semiconductor channel layer A is formed. The etch stopper ES is formed by patterning an insulating material in a third mask process using the first photoresist PR1 and the third mask. The etch stopper ES is preferably formed so as to be located at the center of the semiconductor channel layer A formed on the gate electrode G. Here, after the etch stopper ES is formed by photolithography, the first photoresist PR1 is left without being removed. (FIG. 5C)

The source-drain metal is applied to the entire surface of the substrate SUB on which the etch stopper ES is formed, particularly in a state where the first photoresist PR1 on which the etch stopper ES is formed remains. In particular, the first source-drain metal S1 and the second source-drain metal S2 are laminated and coated. The first source-drain metal S1 includes copper (Copper). The second source-drain metal S2 includes molybdenum (Mo), titanium (Ti), indium tin oxide (ITO), or indium zinc oxide (IZO). The second photoresist PR2 is coated on the second source-drain metal S2, and the second photoresist PR2 is patterned using a fourth mask.

In this case, the surface of the substrate on which the second photoresist PR2 is formed is preferably formed to be divided into three regions. For example, a white-tone region that is a region ⓛ from which the source electrode S and the drain electrode D are completely removed, and a black that is a region ② in which the source electrode S and the drain electrode D remain intact. It is divided into a tone region and a half-tone region in which the source electrode S and the drain electrode D partially remain. Therefore, it is preferable to use a half-tone mask for the fourth mask. Here, the range of the area ③ is important. The region ③ includes a portion overlapping a distance from one end side of the etch stopper ES toward the center, and one end side of the semiconductor channel layer A in the same direction from the one end side of the etch stopper ES. It is preferable to include an intermediate region in between. (FIG. 5D)

The second source-drain metal S2 and the first source-drain metal S1 are etched using the second photoresist PR2 formed according to the fourth mask pattern as a mask. Then, a source-drain element is formed that includes the source electrode S and the drain electrode D. FIG. Since the first photoresist PR1 covering the etch stopper ES is left, the first photoresist PR1 covering the etch stopper ES is exposed even after the source-drain electrodes S and D are formed. Left. (FIG. 5E)

The second photoresist PR2 is ashed. In particular, the ashing is performed only until all of the second photoresist PR2 covering the region ③ in which the source electrode S and the drain electrode D remain. As a result, as shown in FIG. 5E, the second photoresist PR2 remains only in the region ② in which the source electrode S and the drain electrode D remain intact. At this time, the first photoresist PR1 remaining on the etch stopper ES is also partially removed by the ashing process. If the thickness of the first photoresist PR1 is thicker than the second photoresist PR2 in the region ③, it will remain to some extent. Otherwise, the source-drain electrodes S and D and the etch stopper ES overlap with each other. The first photoresist PR1 remains only in the portion. (FIG. 5F)

The second source metal S2 constituting the source-drain electrodes S and D is etched using the remaining second photoresist PR2 as a mask. In this case, it is important to select the etching solution to selectively remove only the second source metal S2 without damaging the first source metal S1. (Fig. 5g)

The remaining first photoresist PR1 and second photoresist PR2 are removed to complete the source-drain element. Then, the first source metal S1 of the source-drain electrodes S and D covering the first photoresist PR1 is lifted off and removed together. As a result, the first source metal S1 constituting the source-drain electrodes S and D is self-aligned with the boundary of the etch stopper ES, and has a structure in which the side edges of each other are butted together. On the other hand, the second source metal S2 is removed from the region ③ of the second photoresist PR2 so that a part of the end portions of the source-drain electrodes S and D include only the first source metal S1. Have (FIG. 5H)

The source-drain element may include a data line DL perpendicularly intersecting with the gate line GL with a gate insulating layer GI interposed therebetween, a data pad DP formed at one end of the data line DL, and data. A source electrode S branching from the wiring DL and contacting one side of the semiconductor channel layer A, and a drain electrode D contacting the other side of the semiconductor channel layer A and facing the source electrode S. It includes. The source electrode S and the drain electrode D are physically separated from each other, but have a structure connected under the semiconductor channel layer A overlapping the gate electrode G with the gate insulating layer GI therebetween. Have In this state, the source electrode S contacts only one side of the semiconductor channel layer A exposed by the etch stopper ES. Similarly, the drain electrode D also has a structure in contact with only the upper surface of the other side of the semiconductor channel layer A. FIG.

Thereafter, a protective film covering the entire surface of the substrate SUB on which the source-drain electrodes S and D are formed is coated. The passivation layer PAS is patterned in the fifth mask process to form a drain contact hole DH exposing a part of the drain electrode D. FIG. (FIG. 5i)

A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is coated on the passivation layer PAS and patterned in a sixth mask process to contact the drain electrode D through the drain contact hole DH. The electrode PXL is formed. This completes the thin film transistor substrate including the oxide semiconductor channel layer. In the present invention, the method for minimizing the overlapping area of the source-drain electrodes S and D and the gate electrode G by the etch stopper ES is focused. Therefore, after the thin film transistor T is completed, the pixel electrode ( PXL) and detailed descriptions up to the formation of the common electrode are omitted. (FIG. 5J)

Referring back to FIG. 5H, the source electrode S and the drain electrode D according to the present invention have a structure in which the end faces coincide with each other without overlapping portions with the etch stopper ES. Accordingly, the size of the region GS where the gate electrode G and the source electrode S overlap and the size of the region GD where the gate electrode G and the drain electrode D overlap with each other are determined by the etch stopper ES. It depends on the design value. For example, the size of the region where the first source metal S1 constituting the source electrode S and the gate electrode G overlap with the semiconductor channel layer A interposed therebetween is one side of the etch stopper ES. It protrudes outward from the sidewall and has a size equal to or smaller than the area of the gate electrode G that does not overlap the etch stopper ES. Similarly, the size of the region where the first source metal S1 constituting the drain electrode D and the gate electrode G overlap with the semiconductor channel layer A interposed therebetween is at the other sidewall of the etch stopper ES. It protrudes outward and has a size equal to or smaller than an area of the gate electrode G that does not overlap the etch stopper ES.

5H and 3, the region GS1 overlapping the gate electrode G and the source electrode S occupied by the thin film transistor having the etch stopper according to the related art is the first source metal in FIG. 5G. S1 includes up to the region overlapping the first photoresist PR1. Therefore, the size of the region GS in which the gate electrode G and the source electrode S overlap with each other is larger than the region GS1 in which the gate electrode G and the source electrode S overlap with each other according to the related art. Has a much smaller size. That is, the overlapping region of the source electrode S and the etch stopper ES considering the design margin due to the intervention of the etch stopper ES is not included in the present invention.

On the other hand, in comparison with FIG. 4, the size of the etch stopper ES corresponds to the size of the exposed region without overlapping the source-drain electrodes S and D in the IPS thin film transistor. In the design, the size of the region GS where the gate electrode G and the source electrode S overlap with each other according to the present invention is such that the gate electrode G and the source electrode S of the IPS type thin film transistor overlap each other. The same level as that of the area GS2 can be ensured. That is, according to the present invention, the size of the parasitic capacitance and Cgs between the source electrode S and the gate electrode G in the FFS method can be minimized. In particular, compared with FIG. 4, the parasitic capacitance between the source electrode S and the gate electrode G in the IPS method may be lowered to the same level as the size of the Cgs.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

SUB: Substrate T: Thin Film Transistor
G: gate electrode GI: gate insulating film
S: source electrode D: drain electrode
GL: gate wiring DL: data wiring
GP: gate pad DP: data pad
GPH: Gate Pad Contact Hole DPH: Data Pad Contact Hole
GPT: Gate pad terminal DPT: Data pad terminal
PAS: Protective Film DH: Drain Contact Hole
PXL: pixel electrode ES: etch stopper
COM: common electrode CL: common wiring
GS, GS1, GS2: overlap region of gate electrode and source electrode
GD, GD1, GD2: overlap region of gate electrode and drain electrode
PR1: first photoresist PR2: second photoresist
①: white tone area ②: black tone area
③: halftone area

Claims (10)

A gate electrode formed on the substrate;
A gate insulating film covering the gate electrode;
A semiconductor channel layer overlapping the gate electrode on the gate insulating layer and including a metal oxide semiconductor;
An etch stopper overlapping a portion of a central portion of the gate electrode on the semiconductor channel layer;
A first source electrode in contact with one side wall of the etch stopper without contact with the etch stopper and in contact with one side of the semiconductor channel layer;
A second source electrode stacked on the first source electrode at a distance from the sidewall of the etch stopper and including a material different from the first source electrode;
A first drain electrode in contact with the other side wall of the etch stopper and in contact with the other side of the semiconductor channel layer without being overlapped with the etch stopper;
A second drain electrode stacked on the first drain electrode and spaced apart from the other sidewall of the etch stopper, the second drain electrode including a material different from the first drain electrode,
And a metal oxide semiconductor positioned outside the gate electrode such that the second source electrode does not overlap the gate electrode, and positioned outside the gate electrode so that the second drain electrode does not overlap the gate electrode. A thin film transistor substrate provided.
The method of claim 1,
The lower end of the second source electrode is located at a distance from the upper end of the first source electrode at the side wall side of the etch stopper, and the lower end of the second drain electrode is located at the other side wall of the etch stopper. The thin film transistor substrate having the metal oxide semiconductor, characterized in that located at a predetermined distance from the upper end of the first drain electrode.
The method of claim 1,
The size of the region where the first source electrode and the gate electrode overlap with the semiconductor channel layer interposed therebetween is greater than that of the gate electrode which protrudes outward from the sidewall of the etch stopper and does not overlap the etch stopper. A thin film transistor substrate having a metal oxide semiconductor, which is not large.
The method of claim 1,
The size of the region where the first drain electrode and the gate electrode overlap with the semiconductor channel layer interposed therebetween is greater than that of the gate electrode which protrudes outward from the other sidewall of the etch stopper and does not overlap the etch stopper. A thin film transistor substrate having a metal oxide semiconductor, which is not large.
Depositing a gate metal on the substrate and patterning with a first mask to form a gate electrode;
Stacking a semiconductor material including a gate insulating layer and a metal oxide semiconductor to cover the gate electrode, and patterning the semiconductor material with a second mask to form a semiconductor channel layer overlapping the gate electrode;
Depositing an insulating material over the semiconductor channel layer and patterning with a third mask to form an etch stopper overlying a portion of the central portion of the gate electrode on the semiconductor channel layer, leaving a first photoresist on the etch stopper;
Stacking and patterning a first source-drain metal and a second source-drain metal having different materials on the gate insulating layer, the semiconductor channel layer, the etch stopper, and the first photoresist. Forming a source-drain electrode exposing a central portion; And
Stripping the first photoresist to self-align the first source electrode and the first drain electrode made of the first source-drain metal with the sidewall of the etch stopper;
The forming of the source-drain electrode may include removing a portion of the second source-drain metal overlapping the etch stopper or the first photoresist and spaced apart from the sidewall of the etch stopper by a distance. Forming a second drain electrode,
And a metal oxide semiconductor positioned outside the gate electrode such that the second source electrode does not overlap the gate electrode, and positioned outside the gate electrode so that the second drain electrode does not overlap the gate electrode. The thin film transistor substrate manufacturing method provided.
The method of claim 5, wherein the forming of the source-drain electrode comprises:
Applying a second photoresist material on the second source-drain metal and patterning it with a fourth mask to form a white tone region on a portion other than the shape of the source-drain electrode, and the first and second source-drain metals. Forming a second photoresist to have a black tone region in the remaining portion and a half-tone region in the portion in which the first source-drain metal remains;
Patterning the second source-drain metal and the first source-drain metal by using the second photoresist as a mask to expose the central portion of the first photoresist;
Aching the second photoresist to expose a portion of the second source-drain metal positioned in the half-tone region of the second photoresist and overlapping the etch stopper; And
And removing the exposed portions of the second source-drain metal using the ashed second photoresist as a mask to form the second source electrode and the second drain electrode. A thin film transistor substrate manufacturing method comprising a semiconductor.
The method of claim 6,
The half-tone region is a region overlapping a distance from one end side of the etch stopper toward the center at one side of the semiconductor channel layer, and the one side of the semiconductor channel layer at the one end side of the etch stopper. A method of manufacturing a thin film transistor substrate having a metal oxide semiconductor, comprising a region overlapping a predetermined distance toward the side edge.
The method of claim 7, wherein
The half-tone region is a region overlapping a distance from the other end side of the etch stopper toward the center at the other side of the semiconductor channel layer, and the semiconductor channel layer at the other end side of the etch stopper. A method of manufacturing a thin film transistor substrate having a metal oxide semiconductor, further comprising a region overlapping a predetermined distance toward the other side.
The method of claim 5,
And a metal oxide semiconductor in which the stripping of the first photoresist is performed by a lift-off method.
The method of claim 5,
Applying a passivation layer covering the first and second source electrodes and the first and second drain electrodes, and forming a drain contact hole exposing a portion of the second drain electrode by patterning with a fifth mask; And
And applying a transparent conductive material on the passivation layer, and forming a pixel electrode contacting the second drain electrode through the drain contact hole by patterning with a sixth mask. Thin film transistor substrate manufacturing method.
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