KR20130037523A - Method and apparatus for encoing using state-check code - Google Patents

Abstract

PURPOSE: A coding method and a coding device are provided to reduce a storage space, to improve a calculation speed and performance, and to offer a proper code for parallel calculation by increasing a calculation processing speed through parallel computation. CONSTITUTION: A state-check coding method includes a stage(S110) of receiving one previously un-inputted bit of information bits, a stage(S120) of transitioning from the current state to the next state according to the received bit, a stage(S130) of repeating the receiving stage and the transitioning stage multiple times, a stage(S140) of determining a stage-check bit according to the transitioned stage in the last repetition, and a stage(S150) of generating a code word by combining the information bits and the stage-check bits. [Reference numerals] (AA) Start; (BB) End; (S110) Inputting one of information bits; (S120) Transiting the current state according to the input bit; (S130) Number of times of repeating satisfied?; (S140) Determining SC bits according to the transited state; (S150) Generating a code word by combining the information bits and the SC bits;

Description

Encoding method and encoding apparatus using state-check code {METHOD AND APPARATUS FOR ENCOING USING STATE-CHECK CODE}

The disclosed technique relates to a method of encoding data, and more particularly, but without limitation, relates to a state-check encoding method and a state-check encoding apparatus using state-check codes (SC codes). The state-check code newly proposed in the present specification can speed up encoding and decoding operations, reduce storage space, and improve error correction performance. . Although the technology disclosed herein can be applied to various ranges, it can be utilized to improve the operation speed through parallel processes and to efficiently use storage space, especially in a communication terminal having an enhanced processor.

In communication, encoding is generally used to recover original data at the receiving end despite errors caused by distortion, loss, or the like of the data transmitted from the transmitting side through the communication channel. It means the process of processing the data in the sender to make sure that it is. This is called channel coding, which is distinguished from source coding that reduces the size of original data to facilitate transmission and storage. Decoding is a process of restoring the encoded and transmitted signal to the original data at the receiving side. To encode is usually to make an information sequence of length K (information bits) into a code of length N. In wireless LAN or mobile communication where signal transmission path is unstable, code length N is made significantly larger than information sequence length K. That is, the data to be transmitted is repeatedly repeated in the coded code. In two-way communication, if a receiving side fails to recover data in transmitting data including an information sequence, the transmitting side transmits the data again. Since repetitive transmission of such data causes a drop in transmission speed, channel coding techniques for reducing such repetitive transmission have been studied.

Channel coding is roughly divided into block codes and convolution codes. The block code generates K bits of data sequences into N bits of output codes. The convolution code is a method of using some signals from the past with the current input signal when coding. Turbo codes are further developed through parallel coding and interleaving based on convolutional codes. Turbo codes are one of error correction codes (ECC) based on the idea of keeping the bit error probability of a communication channel to a minimum. The turbo code, proposed by Berrou et al. In 1993, has a relatively simple structure and provides very good error correction performance, and has been applied to a communication system requiring a high performance error correction code method.

Recently, low-density parity-check (LDPC) codes have been applied to communication systems. The LDPC code makes an information sequence of length K a codeword of length N. A parity bit having a length of (NK) excluding an information sequence among codewords may be generated using a parity-check matrix H. The parity check matrix H is (NK) x N in size and has a low density property with more zeros than one. In the encoding method using the LDPC code, how to make the parity check matrix H is the most important factor. Typically, irregular LDPC codes provide better performance than regular LDPC codes. Regular here means that all rows of parity check matrix H used for LDPC code have the same number of 1s and all columns of H have the same number of 1s, otherwise LDPC code Is considered to be irregular. Here the number of 1s in a row or column is referred to as the weight of the row or column. Irregular low-density parity-check (LDPC) codes with block lengths greater than 10 ⁴ have been shown to perform better than turbo codes.

However, since the parity check matrix H has a size of about 1000 × 2000 or more, many operations are required in the encoding and decoding process, implementation is very complicated, and requires a lot of storage space. In other words, as the size of the data block increases, the error correction capability of the LDPC becomes stronger, but there is a problem that the amount of computation and processing space required by the processor also increase. As a technique for solving such a problem, Korean Patent Laid-Open Publication No. 10-2007-0058438 (Encoding, Decoding Method and Apparatus Using Low Density Parity Check Code in a Wireless Communication System).

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an encoding method and an encoding apparatus capable of improving operation speed and performance while reducing storage space. In addition, since the operation processing speed can be increased through parallel operation, the disclosed technology provides a code suitable for parallel operation.

A first aspect of the disclosed technology to achieve the above technical problem is a step of receiving any one of the information bits previously not input; Transitioning from a current state to a next state according to the received bit; Repeating the step of receiving the input and the transitioning a plurality of times; Determining state-check bits according to the state transitioned at the last iteration; And generating a codeword by combining the information bits and the state-check bits.

A second aspect of the disclosed technology to achieve the above technical problem is a state determination unit for determining the encoding state according to the input information bits; A state-check bit determining unit determining state-check bits according to the determined encoding state, and determining, as the state-check bits, values of input bits for causing the determined encoding state to converge to a preset state; And a codeword generator that generates a codeword by combining the information bits and the state-check bits.

Embodiments of the disclosed technique may have effects that include the following advantages. It should be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, since the embodiments of the disclosed technology are not meant to include all such embodiments.

A state-check code (SC code) according to an embodiment of the disclosed technology generates a state-check bit (SC bit) having a larger number of bits than conventional parity bits in one operation. In the case of encoding or decoding using such a state-check code, there is an advantage that the operation speed is high while showing an improved error correction performance than a conventional coding scheme (eg, LDPC code). In addition, the encoding or decoding method using the state-check code has an advantage that the required storage space is smaller than in the related art, and parallel processing is easy.

1 is a flowchart for describing a method of encoding by a encoding apparatus using a state-check code, according to an embodiment of the disclosed technology.
2 is a diagram for describing a process of transitioning an encoding state and a process of determining a state-check bit, according to an embodiment of the disclosed technology.
3 is a block diagram illustrating an apparatus for state-check encoding using a state-check code according to an embodiment of the disclosed technique.
4 is a view for explaining a state determination unit according to an embodiment of the disclosed technology.
FIG. 5 is a diagram for describing a state determiner when the number of encoded states is 4, according to an embodiment of the disclosed technology.
6 is a diagram for describing a method of decoding using a state-check code, according to an embodiment of the disclosed technology.

The description of the disclosed technique is merely an example for structural or functional explanation and the scope of the disclosed technology should not be construed as being limited by the embodiments described in the text. That is, the embodiments may be variously modified and may have various forms, and thus the scope of the disclosed technology should be understood to include equivalents capable of realizing the technical idea.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms " first ", " second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected to the other element, but there may be other elements in between. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that there are no other elements in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "include" or "have" refer to features, numbers, steps, operations, components, parts, or parts thereof described. It is to be understood that the combination is intended to be present, but not to exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

Each step may occur differently from the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed technology belongs, unless otherwise defined. Terms such as those defined in the commonly used dictionaries should be construed as consistent with the meanings in the context of the related art, and should not be construed as having ideal or overly formal meanings unless expressly defined in this application. .

The LDPC code shows better performance than the turbo code when the block length is 10 ⁴ or more, but it has various problems such as requiring a lot of operations in the encoding and decoding process, implementation is very complicated, and requires a lot of storage space. . The disclosed technology proposes an encoding scheme that shows faster error correction performance than conventional LDPC codes and has a faster operation speed and easier parallel processing. In the disclosed technology, a state-check concept corresponding to an existing parity-check concept is newly introduced to perform encoding using a state-check code. Hereinafter, a state-check code newly proposed by the disclosed technology will be described with reference to the accompanying drawings.

1 is a flowchart for describing a method of encoding by a encoding apparatus using a state-check code, according to an embodiment of the disclosed technology. According to the disclosed technique, an encoding state is determined according to input bits, and according to the determined final encoding state, transmission of input bits by determining state-check bits and transmitting together input bits and state-check bits. Allows you to correct errors. Unlike the conventional parity check method of generating one bit parity bit with one operation on input bits, the disclosed technique generates a plurality of state-check bits through one operation on input bits. Can be. Thus, using the state-check code improves the performance and efficiency of error correction as compared to the prior art. The number of state-check bits N _SC is an integer of 2 or more, and may be determined as an appropriate number in consideration of error correction performance, encoding speed, computation speed, storage space required, and the like. Hereinafter, a description will be given focusing on the case where the number of N _SCs is 2, but the present invention is not limited thereto, and the N _SCs may be integers such as 3 and 4.

The encoding apparatus receives any one of the information bits not previously input (S110). As shown in FIG. 1, step S110 is repeated a predetermined number of times with step S120, and a new bit of information bits is input for each iteration. For example, the encoding apparatus may receive one information bit in sequence. As another example, the encoding apparatus may receive one or more predetermined bits selected in advance among information bits to be encoded instead of all the information bits.

The encoding apparatus transitions from the current state to the next state according to the received bit (S120). The number of states that an encoding state can have is N _s . The current state is determined as one of N _s states based on previously input bits. The current state is initialized to Zero State in the first iteration, and the state transitioned from the previous iteration becomes the current state in subsequent iterations. The next state is any one of two states corresponding to the current state, which is determined according to the currently input bit. According to an embodiment, when N _s is 4, a process of transitioning an encoding state according to input bits is illustrated in FIG. 2. In the embodiment of FIG. 2, when the current state is state 0 (S = 0), the next state may be state 0 or state 2 (S = 0 or S = 2). If state 0 and the input bit is 1, the next state is state 2. That is, according to the current state, there are two states that can be the next state, and the encoding apparatus transitions to one state determined according to an input bit among two states corresponding to the current state.

When the current state (state at the k-th iteration, S _k ) and the next state (state at the k + 1 iteration, S _{k +1} ) are expressed as in Equation 1, there is an embodiment between the current state and the next state. Accordingly, a relationship such as Equation 2 or Equation 3 can be established.

When the value of S _k is represented by N bits, d _{N -1, k} represents the most significant bit of the N bits, and d _{0, k} represents the least significant bit of the N bits. Similarly, when the value of S _{k +1} is represented by N bits, d _{N −1, k + 1} represents the most significant bit of the N bits, and d _{0 , k + 1} represents the least significant bit of the N bits.

는 배타적 논리합(exclusive OR, XOR) 연산을 의미하고, d_k 는 d_{0 ,k} 내지 d_{N -1,k}중 선택되는 적어도 하나의 비트를 XOR 연산한 결과 값을 나타낸다. 일례로, d_k 는 d_{0 ,k} 내지 d_{N -1,k} 비트들을 모두 XOR 연산한 결과일 수 있으며, 다른 일례로, d_k 는 d_{0 ,k} 내지 d_{N -1,k} 비트들 중 d_{0 ,k}, d_{2 ,k} 등 홀수 번째 비트들을 XOR 연산한 결과일 수 있다.i _k is the information bit received in the current iteration,

Means an exclusive OR (XOR) operation, and d _k Represents a result of performing an XOR operation on at least one bit selected from d _{0 , k} to d _{N -1, k} . For example, d _k May be the result of performing an XOR operation on all of d _{0 , k} to d _{N −1, k} bits. As another example, d _k May be the result of performing an XOR operation on odd bits, such as d _{0 , k} , d _{2 , k} , among d _{0 , k} to d _{N −1, k} bits.

At this time, a ₁ to a _{N -1} have a value of 0 or 1 _{, and} the coefficient of d _{0 , k} is always 1. The values a ₁ to a _{N -1} may all have a value of 1, depending on the implementation, and some (eg, odd-numbered) may have a value of 0 for the remainder (eg, even-numbered). .

More specifically, a case in which the state transitions as in the embodiment of FIG. 2 from the case where the state number N _s is 4 and the number of state-check bits N _SC is 2 will be described as an example. When the current state at the k th iteration is represented by two bits [d _{1 , k} d _{0 , k} ] and the next state is represented by [d _{1, k + 1} d _{0, k + 1} ], each state The relationship between the bits representing may be represented by Equation 4.

At this time, if the current state value is 0 [00], the next state value is 0 [00] when the input bit is 0 and 2 [10] when the input bit is 1. If the current state value is 1 [01], the next state value is 2 [10] when the input bit is 0, and 0 [00] when the input bit is 1. If the current state value is 2 [10], the next state value is 3 [11] when the input bit is 0 and 1 [01] when the input bit is 1. Finally, if the current state value is 3 [11], the next state value is 1 [01] when the input bit is 0 and 3 [11] when the input bit is 1.

Among the cases where the number of states N _s is 4 and the number of state-check bits N _SC is 2, the state transition rule according to another embodiment may be represented by Equation 5.

The step of receiving the input (S110) and the step of transition (S120) is repeated a plurality of times a predetermined number of times (S130). The preset number of times may be, for example, equal to the number of information bits to be encoded. That is, when all of the information bits to be encoded are sequentially input, one information bit is sequentially input (S110), and each time the information bits are input one by one, state transition is performed (S120), and this process is performed by all information. Since steps are repeated for bits, steps S110 and S120 are repeated by the number of information bits. As another example, the preset number may be smaller than the number of information bits to be encoded. That is, when the predetermined bits of the information bits to be encoded, which are not all the information bits, are sequentially input one by one, steps S110 and S120 are repeated by the number of the selected specific bits.

According to the input of the information bits, the encoding apparatus determines the state-check bits based on the state value transitioned in the last iteration (S140). According to an embodiment, the encoding apparatus determines, as state-check bits, values of input bits that cause the state transitioned at the last iteration to converge to a preset state. For example, the value of the input bits that causes the transitioned state in the last iteration to converge to the Zero State (S = 0) becomes the state-check bit. More specifically, in FIG. 2 where N _S is 4, N _SC is 2, and the state transitions as shown in Equation 4, the state-check bit is determined as follows. If the value of the transitioned state in the last iteration is state 0, the state check bit is [00]; if the value of the transitioned state in the last iteration is state 1, the state check bit is [10], the transition state in the last iteration If the value of is state 2, the state check bit is [11]. If the value of the state transitioned at the last iteration is state 3, the state check bit is [01]. Referring to FIG. 2, when it is assumed that the state-check bit enters the input bit after the last iteration, it can be confirmed that the state transition ends by converging to the zero state, which is a preset state. In FIG. 2 and the above-described example, the case of converging to the zero state has been described, but the converged state is not limited thereto and may be determined to converge to another state. On the other hand, when the number of states is N _S , the number of bits N _SC of the state-check bits is log ₂ N _s .

이 된다.
When the state-check bits are determined, the encoder generates a codeword by combining the information bits and the state-check bits (S150). If the number of bits of the information bits is K and the number of bits of the status-check bits is N _SC , the number of bits of the codeword is K + N _SC , and the code rate of the status-check code is

.

2 is a diagram for describing a process of transitioning an encoding state and a process of determining a state-check bit, according to an embodiment of the disclosed technology. FIG. 2 is a trellis diagram when N _S is 4, N _SC is 2, and a state transitions as shown in Equation 4 as described above. In FIG. 2, an iterative process of transitioning states as information bits are input is unfolded over time. The encoding state according to the input of the information bits is displayed in a circle, and a solid arrow indicates a case where bit 0 is input and a dotted line arrow indicates when bit 1 is input. First, the coding state is initialized to zero state. Then, when the information bit is input, it is transitioned to the next state according to the current state and the value of the input bit. At T = t ₀ , the current state value is state 0, which is an initialization value. Thereafter, when 0 is inputted, the state transitions to 0, and when 1 is inputted, state 2 is entered. Assuming 1 is entered, the current state value at T = t ₁ is state 2. Thereafter, the state transitions to state 3 when 0 is input, and to state 1 when 1 is input. If 0 is entered, the current state value at T = t ₂ is state 3. As the information bits are input as described above, the state transition is repeated. When the information bits are input a predetermined number of times, the state-check bit is determined according to the encoding state in the last iteration. For example, if the state value at T = t _K is 2, the state-check bit is [11]. The state-check bit is determined by the value of the input bit that causes the state at the last iteration to converge to a particular state, that is, a zero state. Referring to FIG. 2, when the state in the last repetition is state 2, it can be confirmed that when bit 1 is inputted, state 1 is input, and when bit 1 is inputted again in state 1, it becomes state 0 (zero state). As described above, since the state-check bit value is determined according to the coding state when the information bit is last input, the reception side can determine whether there is an error in the transmitted data by using the state-check bit.

3 is a block diagram illustrating an apparatus for state-check encoding using a state-check code according to an embodiment of the disclosed technique. The state-check encoding apparatus 300 of FIG. 3 includes a state determiner 310, a state-check bit determiner 320, and a codeword generator 330. Since the state-check encoding apparatus 300 according to the embodiment of FIG. 3 includes an apparatus for state-check encoding according to the encoding method of FIG. 1, the description of FIG. 1 may also be applied to the present embodiment. The state determiner 310 determines an encoding state according to the input information bits. According to an embodiment of the present disclosure, the state determiner 310 repeats a process of updating the current state a plurality of times according to the current state and the currently input bit, and determines the current state updated in the last iteration as the encoding state. In this case, the number of times of repeating the updating process may be, for example, equal to the number of bits of the information bits, and may be smaller than the number of information bits as another example. A detailed description of the state determination unit 310 will be described later with reference to FIG. 4. The state-check bit determiner 320 determines the state-check bits according to the encoding state determined by the state determiner 310. According to an embodiment, the state-check bit determiner 320 determines, as state-check bits, values of input bits for causing the determined encoding state to converge to a preset state. For example, the state-check bit determiner 320 may determine, as state-check bits, values of input bits for causing the determined encoding state to converge to a zero state. The codeword generator 330 combines the information bits and the status-check bits to generate a codeword.

4 is a view for explaining a state determination unit according to an embodiment of the disclosed technology. According to an embodiment, the state determiner 310 may include a register 410 and an operator 420 to determine an encoding state. The register 410 stores bits representing the coding state. The operation unit 420 may include one of bits (information bit i) input to the state determining unit 310 and bits indicating an encoding state (that is, bits stored in a register, d _o , d ₁ ,...) Perform an XOR operation between at least one bit. For example, an XOR operation may be performed between all bits stored in the register 410 and an input bit, and as another example, an XOR operation may be performed between an input bit and a bit stored in the D ₀ register. That is, each storage space D ₀ of the register 410 D _{N -1} is selectively connected to the operation unit 420 to provide the stored bit value to the operation unit 420. In this case, according to an exemplary embodiment, whenever the information bit is input to the state determiner 310, the register 410 moves the stored bits to the lower bit position by one bit, and the operation result performed by the operation unit 420 is changed. It may be a recursive shift register for updating the bits indicating the encoding state by being input to the most significant bit digit. The operation of the register 410 and the operation unit 420 may be expressed as Equation 2 or Equation 3 below.

FIG. 5 is a diagram for describing a state determiner when the number of encoded states is 4, according to an embodiment of the disclosed technology. When the coded state number N _S is 4, the state-check bit number N _SC and the number of bits indicating the coded state are 2, so the register 410 has two storage spaces D ₁ and D ₀ . The operation unit 420 may perform an XOR (exclusive OR) between at least one bit among the bits representing the input bit i and the encoding state, that is, bits d ₁ and d ₀ in which values are stored in the registers D ₁ and D ₀ . Perform the operation. For example, (a) of FIG. 5 performs an XOR operation of input bits i and three bits d ₁ and d ₀ which are bit values stored in a register. This is represented by Equation 4 below. As another example, FIG. 5B performs an XOR operation between input bit i and d ₀ , a bit value stored in a register. This is represented by Equation 5 below.

6 is a diagram for describing a method of decoding using a state-check code, according to an embodiment of the disclosed technology. The state-check code according to the disclosed technique can be decoded using the BCJR algorithm, unlike the conventional LDPC code using the tanh rule for parity check. Hereinafter, for the sake of understanding, the process of decoding the received data using the state-check code of FIG. 2 will be described as an example.

The decoder is provided with a coded signal using a state-check code. The encoded signal is a signal generated by combining the state-check bits generated according to the state transition and state-check bit generation rules of FIG. 2 with information bits. In this case, the encoder may be implemented by using a recursive shift register (RSR) as shown in FIG. Since the transition rule of FIG. 2 or the structure shown in FIG. 5 is information that the transmitting side and the receiving side have in common, the trellis as shown in FIG. 2 may be configured in the same manner as in FIG. 6. The decoder decodes the received signal by applying the BCJR algorithm to the received signal based on the trellis of FIG. 6. According to the BCJR algorithm, a soft decision value of a transmission bit may be obtained by calculating a post probability based on a received bit string. Posterior probability at T = t _k can be computed as the sum of post-transition probability at T = t _k. The posterior probability at T = t _{k is shown} in Equation 6, and the posterior transition probability at T = t _{k is shown} in Equation 7.

Here, the posterior probability P (d _k = d) is a probability that the transmission bit value at T = t _k is d (d is 0 or 1). σ and (s _k, d) the probability of post-transition at _{T = t k, σ (s} k = i, d) is a state i (s _k) state at T = t _k, at T = t _k Means the probability that the transmission bit d _k of d is d. s _k has a value of any one of the given encoding states S, and in this embodiment, has a value of any one of state 0, state 1, state 2, and state 3.

Where α (s _k = i) is T = t _k Given the previous received signal, it represents the probability of staying in state i at T = t _k and is called the forward state metric. β (s _{k + 1} = j) represents the probability of staying in state j at T = t _k when a received signal after T = t _{k +1} is referred to as a backward state metric. γ (s _k , s _{k +1} ) may be expressed as γ (s _k , d) depending on the point of view, and γ (s _k = i, s _{k +1} = j) or γ (s _k = i, d ) is referred to as the branch metric to the probability, given the received signal at t = T _k, and state i at T = t _k, the transmission bit d. At this time, the transmission bit d is a bit value for transitioning from s _k = i to s _k = j. When s _k = i, if the input bit is d, s _{k +1} = j.

The decoder calculates branch metrics corresponding to each branch constituting the trellis, based on the trellis diagram of FIG. 6. The branch metric γ (s _k = i, d) is calculated using the probability density function of the received signal when the prior probability and the transmission bit are d. For example, in FIG. 6, it is assumed that the branch metric γ (s _k = i, d) has both a probability that d _k = 0 and a probability that d _k = 1 are 0.5, and the probability that s _k is in each encoding state is the same. In this case, it can be calculated as a value corresponding to the received signal at a given probability density function.

The decoder calculates the forward state metric and the reverse state metric based on the initial state value, the final state value, and the branch metric value. The forward state metric is calculated sequentially from α (s ₀ ) to α (s _N ) by Forward Recursion. In the case of FIG. 6, since it is known that the initial state value is state 0 (s ₀ = 0), α (s ₀ ) is 1 when s ₀ = 0, and 0 when the remaining s ₀ = 1, 2, 3 It is initialized. α _(k = s i) is the forward of s _{k -1,} which for all kinds leading to the state s _k value of i from _k-1 s has an arbitrary state value, and the branch metric for each state of It is calculated as the sum of the products of the metric. This can be expressed as an equation (8).

For example, in FIG. 6, α (s ₃ = 1) is calculated as α (s ₂ = 2) γ (s ₂ = 2,1) + α (s ₂ = 3) γ (s ₂ = 3,0). do.

The reverse state metric is repeatedly calculated in reverse order from β (s _N ) to β (s ₀ ) by Backward Recursion. In FIG. 6, since it is known that the final state value is state 0 (s _N = 0), β (s _N ) is 1 when s _N = 0, and 0 when the remaining s _N = 1, 2, 3 It is initialized. β _(k = s i) is the reverse of s _{k +1} that for all of the reverse leading to s _k in state s _{k +1} having the value of i from an arbitrary state value, and the branch metric for each of It is calculated as the sum of the products of the state metrics. This is expressed as an equation (9).

When the branch metric, the forward metric, and the reverse metric are all calculated, a post-transition probability is calculated for each time as shown in Equation (7). As shown in Equation 6, the sum of the post-transition probabilities for d at each time can be obtained. The decoder determines the value of each transmission bit according to the posterior probability. In FIG. 6, a method of decoding the state-check code according to the BCJR algorithm has been described, but the decoding method is not limited thereto.

While the system and apparatus disclosed herein have been described with reference to the embodiments shown in the drawings for purposes of clarity of understanding, they are illustrative only and various modifications and equivalent embodiments can be made by those skilled in the art. I will understand that. Accordingly, the true scope of protection of the disclosed technology should be determined by the appended claims.

Claims (19)

Receiving any one of the information bits not previously input;
Transitioning from a current state to a next state according to the received bit;
Repeating the step of receiving the input and the transitioning a plurality of times;
Determining state-check bits according to the state transitioned at the last iteration; And
And combining the information bits and the state-check bits to generate a codeword. The method of claim 1, wherein the determining step,
And determining the values of the input bits as the state-check bits to cause the transitioned state in the last iteration to converge to a preset state. The method of claim 1, wherein the determining step,
And determining the values of the input bits as the state-check bits to cause the transitioned state in the last iteration to converge to a zero state. The method of claim 1, wherein the step of transitioning,
And transitioning to a state determined according to the received bit among two states corresponding to the current state. The method of claim 1, wherein the step of transitioning,
The current state in the k-th iteration is N bits [d _{N -1, k} ... d _{0 , k} ]
d _{n , k + 1} = d _{n + 1, k} (where n = 0,…, N-2)

Where i _k is the information bit received in the current iteration,

Means an exclusive OR (XOR) operation, and d _k Denotes a value obtained by performing XOR operation on at least one bit selected from d _{0 , k} to d _{N -1, k} ), wherein N bits [d _{N −1, k + 1} ... d _{0 , k + 1} ] state-check encoding method for transitioning to the next state. The method of claim 1, wherein the step of transitioning,
The current state in the k-th iteration is N bits [d _{N -1, k} ... d _{0 , k} ]
d _{n , k + 1} = d _{n + 1, k} (where n = 0,…, N-2)

Where i _k is the information bit received in the current iteration,

Denotes an exclusive OR (XOR) operation, where a ₁ to a _N-1 have a value of 0 or 1), N bits [d _{N −1, k + 1} ... d _{0 , k + 1} ] state-check encoding method for transitioning to the next state. The method of claim 1, wherein the step of transitioning,
When the current state at the k th iteration is represented by two bits [d _{1 , k} d _{0 , k} ],
d _{0 , k + 1} = d _{1 , k}

Where i _k is the information bit received in the current iteration,

Transitions to the next state represented by two bits [d _{1, k + 1} d _{0, k + 1} ] determined according to an exclusive OR (XOR) operation. The method of claim 1, wherein the step of transitioning,
When the current state at the k th iteration is represented by two bits [d _{1 , k} d _{0 , k} ],
d _{0 , k + 1} = d _{1 , k}

Where i _k is the information bit received in the current iteration,

Transitions to the next state represented by two bits [d _{1 , k + 1} d _{0 , k + 1} ] determined according to an exclusive OR (XOR) operation. The method of claim 1,
The number of times of repeating the receiving step and the transition step is equal to the number of bits of the information bits. The method of claim 1,
And the number of times of repeating the receiving and the transitioning steps is smaller than the number of bits of the information bits. A state determination unit to determine an encoding state according to input information bits;
A state-check bit determining unit determining state-check bits according to the determined encoding state, and determining, as the state-check bits, values of input bits for causing the determined encoding state to converge to a preset state; And
And a codeword generator for generating a codeword by combining the information bits and the state-check bits. The apparatus of claim 11, wherein the state-check bit determiner comprises:
And a state-check bit determining a value of input bits for causing the determined encoding state to converge to a zero state. The method of claim 11, wherein the state determination unit,
A register for storing bits representing the encoding state; And
And an operation unit configured to perform an XOR operation between at least one of the input bits and the bits representing the encoding state.
Whenever a bit is input to the state determining unit, the register moves the stored bits to the lower bit position by one bit, and the operation result performed by the operation unit is input to the highest bit position to update the bits indicating the encoding state. A state-check encoding device which is a recursive shift register. The method of claim 11,
And the state determination unit repeats the process of updating the current state a plurality of times in accordance with a current state and a currently input bit, and determines the current state updated in the last iteration as the encoding state. The method of claim 14, wherein the state determination unit,
N bits representing the current state in the k-th iteration [d _{N -1, k} ... d _{0 , k} ]
d _{n , k + 1} = d _{n + 1, k} (where n = 0,…, N-2)

Where i _k is the information bit received in the current iteration,

Means an exclusive OR (XOR) operation, and d _k Denotes a value obtained by performing XOR operation on at least one bit selected from d _{0 , k} to d _{N -1, k} ), wherein N bits [d _{N −1, k + 1} ... d _{0 , k + 1} ]. The method of claim 14, wherein the state determination unit,
N bits representing the current state in the k-th iteration [d _{N -1, k} ... d _{0 , k} ]
d _{n , k + 1} = d _{n + 1, k} (where n = 0,…, N-2)

Where i _k is the information bit received in the current iteration,

Denotes an exclusive OR (XOR) operation, where a ₁ to a _N-1 have a value of 0 or 1), N bits [d _{N −1, k + 1} ... d _{0 , k + 1} ]. The method of claim 14, wherein the state determination unit,
two bits [d _{1 , k} d _{0 , k} ] representing the current state at the k th iteration
d _{0 , k + 1} = d _{1 , k}

Where i _k is the information bit received in the current iteration,

Represents an exclusive OR (XOR) operation). The state-check encoding apparatus updates with two bits [d _{1 , k + 1} d _{0 , k + 1} ]. The method of claim 14, wherein the state determination unit,
two bits [d _{1 , k} d _{0 , k} ] representing the current state at the k th iteration
d _{0 , k + 1} = d _{1 , k}

Where i _k is the information bit received in the current iteration,

Denotes an exclusive OR (XOR) operation). The state-check encoding apparatus updates with two bits [d _{1, k + 1} d _{0, k + 1} ]. 15. The method of claim 14,
And a number of times of repeating the updating process is less than or equal to the number of bits of the information bits.

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