KR101268060B1 - Method for encoing and decoding using unitive state-check code - Google Patents

Abstract

PURPOSE: An encoding and decoding method using an engagement state check code is provided to reduce a necessary storage space and to improve error correction performance. CONSTITUTION: An encoding device selects at least some data bits in the bits of a data bit string to be encoded(S110). The encoding device initializes an encoding state whenever determining each SC(State Check) bit(S120). The encoding device determines an encoding state according to the selected data bits in the data bits comprising a data bit string(S130). The encoding device determines SC bits based on a shifted state value in the final repetition according to the input of selected bits(S140). The encoding device repeats S110 stage to S140 stage for the predetermined times(S150). If the each SC bit is determined, the encoding device generates a code word by engaging the bits engaging a plurality of the SC bits with the data bit string(S160). [Reference numerals] (AA) Start; (BB) Repeat count(G) is satisfied?; (CC) End; (S110) Select data bits from a data bit string; (S120) Initialize an encoding state; (S132) Input one of the selected data bits; (S134) Shift the state according to the input bit; (S136) Selected data bits are all inputted?; (S140) Determine SC bits according to the shifted state; (S160) Generate a code word by combining the data bits and the SC bits

Description

Coding method and decoding method using combined state-check code {METHOD FOR ENCOING AND DECODING USING UNITIVE STATE-CHECK CODE}

The disclosed technique relates to a method of encoding data, and more particularly, but without limitation, relates to an encoding and decoding method using unitary state-check codes (USC codes). The new joint state-check code proposed herein can speed up the processing of encoding and decoding operations, reduce the storage space required, and improve error correction performance. have. Although the technology disclosed herein can be applied to various ranges, it can be utilized to improve the operation speed through parallel processes and to efficiently use storage space, especially in a communication terminal having an enhanced processor.

In communication, encoding is generally used to recover original data at the receiving end despite errors caused by distortion, loss, or the like of the data transmitted from the transmitting side through the communication channel. It means the process of processing the data in the sender to make sure that it is. This is called channel coding, which is distinguished from source coding that reduces the size of original data to facilitate transmission and storage. Decoding is a process of restoring the encoded and transmitted signal to the original data at the receiving side. To encode is usually to make an information sequence of length K (information bits) into a code of length N. In wireless LAN or mobile communication where signal transmission path is unstable, code length N is made significantly larger than information sequence length K. That is, the data to be transmitted is repeatedly repeated in the coded code. In two-way communication, if a receiving side fails to recover data in transmitting data including an information sequence, the transmitting side transmits the data again. Since repetitive transmission of such data causes a drop in transmission speed, channel coding techniques for reducing such repetitive transmission have been studied.

Channel coding is roughly divided into block codes and convolution codes. The block code generates K bits of data sequences into N bits of output codes. The convolution code is a method of using some signals from the past with the current input signal when coding. Turbo codes are further developed through parallel coding and interleaving based on convolutional codes. Turbo codes are one of error correction codes (ECC) based on the idea of keeping the bit error probability of a communication channel to a minimum. The turbo code, proposed by Berrou et al. In 1993, has a relatively simple structure and provides very good error correction performance, and has been applied to a communication system requiring a high performance error correction code method.

Recently, low-density parity-check (LDPC) codes have been applied to communication systems. The LDPC code makes an information sequence of length K a codeword of length N. A parity bit having a length of (NK) excluding an information sequence among codewords may be generated using a parity-check matrix H. The parity check matrix H is (NK) x N in size and has a low density property with more zeros than one. In the encoding method using the LDPC code, how to make the parity check matrix H is the most important factor. Typically, irregular LDPC codes provide better performance than regular LDPC codes. Regular here means that all rows of parity check matrix H used for LDPC code have the same number of 1s and all columns of H have the same number of 1s, otherwise LDPC code Is considered to be irregular. Here the number of 1s in a row or column is referred to as the weight of the row or column. Irregular low-density parity-check (LDPC) codes with block lengths greater than 10 ⁴ have been shown to perform better than turbo codes.

However, since the parity check matrix H has a size of about 1000 × 2000 or more, many operations are required in the encoding and decoding process, implementation is very complicated, and requires a lot of storage space. In other words, as the size of the data block increases, the error correction capability of the LDPC becomes stronger, but there is a problem that the amount of computation and processing space required by the processor also increase. As a technique for solving such a problem, Korean Patent Laid-Open Publication No. 10-2007-0058438 (Encoding, Decoding Method and Apparatus Using Low Density Parity Check Code in a Wireless Communication System).

The technical problem to be achieved by the disclosed technology is to provide an encoding method and a decoding method that can improve the operation speed and performance while reducing the storage space. In addition, since the operation processing speed can be increased through parallel operation, the disclosed technology provides a code suitable for parallel operation.

In order to achieve the above technical problem, a first aspect of the disclosed technology comprises: (a) determining an encoding state according to selected information bits among information bits constituting an information bit string; (b) determining state-check bits based on the encoding state; (c) repeating steps (a) and (b) at least once using newly selected information bits of the information bits constituting the information bit string; And (d) combining the information bit string and the state-check bits to generate a codeword.

A second aspect of the disclosed technology to achieve the above technical problem comprises the steps of: (a) receiving an encoded signal in which information bits are combined with state-check bits; (b) a second value based on the value of the first message, wherein the value of the first message indicates the likelihood of each bit estimated based on the likelihood of the surrounding bits of each bit of the encoded signal. Calculating values of the message; (c) calculating values of the first message based on the values of the second message using a trellis based BCJR algorithm indicating a transition state of encoding according to the information bits; (d) repeating steps (b) and (c) using the newly calculated values of the first message and the values of the second message; And (e) determining the value of each bit according to the likelihood of each bit estimated based on the values of the first message calculated in the last iteration.

Embodiments of the disclosed technique may have effects that include the following advantages. It should be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, since the embodiments of the disclosed technology are not meant to include all such embodiments.

개(N_SC는 각 SC 비트들의 길이)의 SC 코드만이 필요하다는 장점이 있다. A state check code (SC code) according to an embodiment of the disclosed technology generates a state check bit (SC bit) having a larger number of bits than a conventional parity bit in one operation. do. In a coding method using a unitary state-check code (USC code), which is a method of combining and encoding such SC codes, in the conventional coding method using an LDPC code, M (M = NK, N is a codeword). Unlike the length, K is the length of the information block) component codes,

An advantage is that only SC SCs (N _SC is the length of each SC bit) are needed.

In the encoding or decoding method using the USC code according to the disclosed technology, there is an advantage that the encoding and decoding speed is faster than the conventional coding scheme (for example, LDPC code). In addition, the encoding or decoding method using the USC code has an advantage that the required storage space is small and parallel processing is easy while showing improved error correction performance.

1 is a flowchart illustrating a method of encoding by a coding apparatus using a USC code, according to an embodiment of the disclosed technology.
2 is a diagram for describing a process of transitioning a state of an encoding apparatus and a process of determining an SC bit, according to an embodiment of the disclosed technology.
3 is a diagram for describing a process of changing a register value of an encoding apparatus according to an embodiment of the disclosed technology.
FIG. 4 is a diagram for describing a process of encoding using SC integration matrix A according to one embodiment of the disclosed technology.
5 is a diagram for describing a method of decoding using a USC code, according to an embodiment of the disclosed technology.

The description of the disclosed technique is merely an example for structural or functional explanation and the scope of the disclosed technology should not be construed as being limited by the embodiments described in the text. That is, the embodiments may be variously modified and may have various forms, and thus the scope of the disclosed technology should be understood to include equivalents capable of realizing the technical idea.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms " first ", " second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected to the other element, but there may be other elements in between. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that there are no other elements in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "include" or "have" refer to features, numbers, steps, operations, components, parts, or parts thereof described. It is to be understood that the combination is intended to be present, but not to exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

Each step may occur differently from the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed technology belongs, unless otherwise defined. Terms such as those defined in the commonly used dictionaries should be construed as consistent with the meanings in the context of the related art, and should not be construed as having ideal or overly formal meanings unless expressly defined in this application. .

The LDPC code shows better performance than the turbo code when the block length is 10 ⁴ or more, but it has various problems such as requiring a lot of operations in the encoding and decoding process, implementation is very complicated, and requires a lot of storage space. . The disclosed technology proposes an encoding and decoding method that exhibits improved error correction performance compared to the conventional LDPC code and has a faster operation speed and easier parallel processing. In the disclosed technology, a state-check concept corresponding to an existing parity-check concept is newly introduced to perform encoding and decoding using a combined state-check code (USC code). Hereinafter, the USC code newly proposed in the disclosed technology will be described with reference to the drawings.

1 is a flowchart illustrating a method of encoding by a coding apparatus using a USC code, according to an embodiment of the disclosed technology. According to the disclosed technology, the encoder is configured to determine an encoding state according to input bits that are at least some of the information bits to be encoded, and to repeatedly determine the SC bits according to the determined final encoding state a plurality of times, each outputted a plurality of times. Combine the SC bits of. The combined SC bits are transmitted with the information bits, thereby making it possible to correct a transmission error of the information bits. The length of each SC bit, that is, the number of bits N _SC is an integer of 2 or more, and may be determined in an appropriate number in consideration of error correction performance, encoding speed, arithmetic speed, required storage space, and the like. Hereinafter, a description will be given focusing on the case where the number of N _SCs is 2, but the present invention is not limited thereto, and the N _SCs may be integers such as 3 and 4.

The encoding apparatus first selects at least some information bits among the bits of the information bit string b _k to be encoded (S110). As can be seen in FIG. 1, steps S110 to S140 are repeated a predetermined number of times (for example, G times). At each repetition, at least some information bits of the bits of the information bit string are newly selected and newly selected information bits are selected. Each SC bit is determined using. In addition, according to an embodiment, the encoding apparatus may select not only information bits but also at least some of the SC bits determined in the previous repetition together and use them in a subsequent encoding process. The encoding apparatus initializes the encoding state whenever determining each SC bit (S120). It is assumed that the initialized coding state is a zero state.

The encoding apparatus determines an encoding state according to the selected information bits among the information bits constituting the information bit stream (S130). According to an embodiment, when some bits of the SC bits are selected in operation S110, in operation S130, the encoding apparatus determines an encoding state according to the selected information bits and the selected SC bits (hereinafter, selected bits). The encoding apparatus may repeat steps S132 and S134 by the number of selected bits, and determine the encoding state as the encoding state in the last iteration.

In operation S132, the encoding apparatus receives one of the selected bits, which has not been previously input. For example, the encoding apparatus may receive one selected bit in sequence. If any one bit is input, the encoding apparatus transitions from the current state to the next state according to the received bit (S134). The number of states that an encoding device can have is N _s . The current state is determined as one of N _s states based on previously input bits. The current state is initialized to state 0 in the first iteration, and the state transitioned from the previous iteration to the current state in subsequent iterations. The next state is any one of two states corresponding to the current state, which is determined according to the currently input bit. According to an embodiment, when N _s is 4, a process of transitioning an encoding state according to input bits is illustrated in FIG. 2. In the embodiment of FIG. 2, when the current state is state 0, the next state may be state 0 or state 2. When the input bit is 0, the next state is state 0, and when the input bit is 1, the next state is state 2 Becomes That is, according to the current state, there are two states that can be the next state, and the encoding apparatus transitions to one state determined according to an input bit among two states corresponding to the current state.

When the current state (state at the k-th iteration, S _k ) and the next state (state at the k + 1 iteration, S _{k +1} ) are expressed as in Equation 1, there is an embodiment between the current state and the next state. Accordingly, a relationship such as Equation 2 or Equation 3 can be established.

When the value of S _k is represented by N bits, d _{N -1, k} represents the most significant bit of the N bits, and d _{0, k} represents the least significant bit of the N bits. Similarly, when the value of S _{k +1} is represented by N bits, d _{N −1, k + 1} represents the most significant bit of the N bits, and d _{0 , k + 1} represents the least significant bit of the N bits.

는 배타적 논리합(exclusive OR, XOR) 연산을 의미하고, d_k 는 d_{0 ,k} 내지 d_{N -1,k}중 선택되는 적어도 하나의 비트를 XOR 연산한 결과 값을 나타낸다. 일례로, d_k 는 d_{0 ,k} 내지 d_{N -1,k} 비트들을 모두 XOR 연산한 결과일 수 있으며, 다른 일례로, d_k 는 d_{0 ,k} 내지 d_{N -1,k} 비트들 중 d_{0 ,k}, d_{2 ,k} 등 홀수 번째 비트들을 XOR 연산한 결과일 수 있다.i _k is the information bit received in the current iteration,

Means an exclusive OR (XOR) operation, and d _k Represents a result of performing an XOR operation on at least one bit selected from d _{0 , k} to d _{N -1, k} . For example, d _k May be the result of performing an XOR operation on all of d _{0 , k} to d _{N −1, k} bits. As another example, d _k May be the result of performing an XOR operation on odd bits, such as d _{0 , k} , d _{2 , k} , among d _{0 , k} to d _{N −1, k} bits.

At this time, a ₁ to a _{N -1} have a value of 0 or 1 _{, and} the coefficient of d _{0 , k} is always 1. The values a ₁ to a _{N -1} may all have a value of 1, depending on the implementation, and some (eg, odd-numbered) may have a value of 0 for the remainder (eg, even-numbered). .

More specifically, the case where the state transitions as in the embodiment of FIG. 2 from the case where the state number N _s is 4 and the number of SC bits N _SC is 2 will be described as an example. When the current state in the k iterations is represented by two bits [d _{1 , k} d _{0 , k} ], and the next state is represented by [d _{1 , k + 1} d _{0 , k + 1} ], each state The relationship between the bits representing may be represented by Equation 4.

At this time, if the current state value is 0 [00], the next state value is 0 [00] when the input bit is 0 and 2 [10] when the input bit is 1. If the current state value is 1 [01], the next state value is 2 [10] when the input bit is 0, and 0 [00] when the input bit is 1. If the current state value is 2 [10], the next state value is 3 [11] when the input bit is 0 and 1 [01] when the input bit is 1. Finally, if the current state value is 3 [11], the next state value is 1 [01] when the input bit is 0 and 3 [11] when the input bit is 1.

Among the cases where the number of states N _s is 4 and the number of SC bits N _SC is 2, the state transition rule according to another embodiment may be expressed by Equation 5 below.

The step of receiving input (S132) and the step of transition (S134) are repeated a plurality of times a predetermined number of times (S136). The preset number of times may be, for example, the same as the number of bits of the bits selected in step S110. That is, the selected information bits of the information bit stream to be encoded or the selected bits of the SC bits determined in the previous iteration are sequentially input one by one (S132), and whenever the selected bits are input one by one, a state transition is performed (S134). . The information bits selected from the information bit strings are preferably smaller than the number of bits constituting the entire information bit string, but are not necessarily limited thereto.

The encoding apparatus determines SC bits based on the state value transitioned in the last repetition according to the input of the selected bits (S140). According to an embodiment, the encoding apparatus determines SC bits as values of input bits for converging the state transitioned at the last iteration to a preset state. For example, the value of the input bits, which causes the transitioned state in the last iteration to converge to zero state, becomes the SC bit. More specifically, in the case of FIG. 2 where N _S is 4, N _SC is 2, and the state transitions as shown in Equation 4, the SC bit is determined as follows. If the value of the transitioned state in the last iteration is state 0, the SC bit is [00]. If the value of the transitioned state in the last iteration is state 1, the SC bit is [10] and the value of the transitioned state in the last iteration. In this state 2, the SC bit is [11], and when the value of the transitioned state at the last iteration is state 3, the SC bit is [01]. Referring to FIG. 2, when it is assumed that the SC bit enters the input bit after the last repetition, it may be confirmed that the state transition ends by converging to the state 0, which is a preset state. In FIG. 2 and the example described above, the case of converging to the state 0 is assumed, but the converging state is not limited thereto and may be determined to converge to another state. On the other hand, when the number of states is N _S , the number of bits N _SC of the SC bits is log ₂ N _s .

이 된다.
The encoding apparatus repeats steps S110 to S140 as many times as the preset number G (S150). The encoding apparatus newly selects information bits every repetition and determines SC bits every repetition. When each SC bit is determined, the encoding apparatus generates a codeword by combining the bits combining the plurality of SC bits with the information bit string (S160). If the number of bits of information bits is K and the number of bits of each SC bit is N _SC , the code rate of the USC code is

.

2 is a diagram for describing a process of transitioning a state of an encoding apparatus and a process of determining an SC bit, according to an embodiment of the disclosed technology. FIG. 2 is a trellis diagram when N _S is 4, N _SC is 2, and a state transitions as shown in Equation 4 as described above. In FIG. 2, an iterative process of transitioning states as information bits are input is unfolded over time. The state of the encoding apparatus according to the input of the information bits is displayed in a circle, and a solid line arrow indicates a case where bit 0 is input and a dotted line arrow indicates a case where bit 1 is input. First, the coding state is initialized to state 0. Then, when the information bit is input, it is transitioned to the next state according to the current state and the value of the input bit. At T = t ₀ , the current state value is state 0, which is an initialization value. Thereafter, when 0 is inputted, the state transitions to 0, and when 1 is inputted, state 2 is entered. Assuming 1 is entered, the current state value at T = t ₁ is state 2. Thereafter, the state transitions to state 3 when 0 is input, and to state 1 when 1 is input. If 0 is entered, the current state value at T = t ₂ is state 3. As the information bits are input as described above, the state transition is repeated. If all of the selected bits are sequentially input, the encoding apparatus determines a state at the last iteration as an encoding state and determines SC bits according to the encoding state. For example, when the coding state at T = t _K is state 2, the SC bit is [11]. The SC bit is determined by the value of the input bit that makes the state at the last iteration go to a specific state, that is, state zero. Referring to FIG. 2, when the encoding state is state 2, it can be confirmed that when bit 1 is input, state 1 is input, and when bit 1 is input again in state 1, state 0 is obtained. As described above, since the SC bit value is determined according to the encoding state when the information bit is last input, the receiving side can determine whether there is an error of the transmitted data using the SC bit.

3 is a diagram for describing a process of changing a register value of an encoding apparatus according to an embodiment of the disclosed technology. The value stored in the register of the encoding device indicates the encoding state. The register 310 stores bits representing the coding state. When any one bit is input to the encoding apparatus, the operation unit 320 may include an information bit (i) input to the encoding apparatus and bits indicating an encoding state (that is, bits having a value stored in a register, d _o , d). _1, and performs at least one XOR (exclusive OR) operation between the bit of .... in one example, may be an XOR operation between all the bits of the input bit stored in the register 310, the D ₀ registers as another example An XOR operation may also be performed between the stored bits and the input bits, ie each storage space D _{0 in} register 310. D _{N -1} is selectively connected to the operation unit 320 to provide the stored bit value to the operation unit 320. According to an embodiment, the register 310 is a recursive shift register. When the information bits are input to the encoding apparatus, the stored bits are shifted by one bit to the lower bit positions and performed by the operation unit 320. The operation result is input to the most significant bit digit to update the bits indicating the encoding state. The operation of the register 310 and the operation unit 320 may be expressed as Equation 2 or Equation 3 below.

FIG. 4 is a diagram for describing a process of encoding using SC integration matrix A according to one embodiment of the disclosed technology. Since the process of encoding the information bit stream using the matrix A of FIG. 4 is included in the embodiment of FIG. 1, the description of FIG. 1 may be equally applied to the embodiment.

FIG. 4A illustrates a G by N SC Unifying matrix A of G rows N columns. The matrix A may structurally represent a process of encoding an information bit string using a USC code. The matrix A repeats steps S110 to S140 of FIG. 1, selecting information bits from the information bit string b _k (S110), and determining SC bits using the selected bits (S140) as a matrix of rows G. FIG. Express. The matrix A may serve as a generator matrix in the LDPC code. The number of bits selected from the information bit string b _k in the i iterations of the G repetitions is m (i), and the number of repeatedly selected jth bits of the K bits constituting the information bit string b _k is q. It is called (j). The matrix A is a binary matrix, and the values of the components a _{i and j} of the matrix have all zero values except a _{i and pi (l)} . π (l) means the column index j of the l-th selected bit among the m (i) bits selected in the i-th iteration. The value of a _{i , j} (ie a _{i , π (l)} ) with j = π (l) is 1.

In FIG. 4A, a 10 by 40 matrix A is illustrated. The matrix A shown in FIG. 4A is G = 10, and the steps S110 to S140 are repeated 10 times. With K = 20, the _number of bits of the information bit string b _k is 20, and the number of bits N _SC of the SC bits is two. Since the process of determining the SC bits is repeated 10 times, the length NK of the total SC bit block determined is 20. The gray shaded parts of matrix A all have zero values. In the first row, the 3rd, 4th, 9th, 14th, 16th, 17th column has a value of 1, so in the first iteration, the 3rd, 4th, 9th, 14th, 16th, 17th of the information bits of the information bit string b _k The bits are selected and step S130 is performed. The remaining columns can be interpreted as well. In operation S110, according to an embodiment, the bits to be input to the encoding apparatus may be selected, including SC bits determined in a previous iteration, in the K information bit streams. For example, in the fourth row, since the sixth, fourteenth, fifteenth, sixteenth, and twenty-second columns have a value of 1, in the fourth iteration, the sixth, fourteenth, fifteenth, sixteenth bits of the information bits of b _k , and the first SC bit. The second bit is selected to perform the step S130. 4B illustrates a process of encoding using the matrix A. Referring to FIG. According to an embodiment, the codeword c generated by the encoding apparatus may be a bit string having a length N of [ b _k b _p ]. b _p may be a SC bit string of G · N _SC length including G SC bits. It is assumed that the encoding apparatus performs encoding including the RSR shown in FIG. 3. The encoding apparatus repeats the process of determining SC bits G times. The encoding apparatus initializes the state of the RSR every iteration. The encoding apparatus sequentially inputs the selected m (i) bits to the RSR every iteration. According to the encoding state of the RSR according to the last input bit, input bits for causing the encoding state to converge to a specific state (eg, state 0) are determined as SC bits. The i-th determined SC bits become the K + 2i-2, K + 2i-1, ... th bits of the codeword C. Repeating this process G times, all SC bits of b _P are determined, and the encoding apparatus outputs codeword C.

5 is a diagram for describing a method of decoding using a USC code, according to an embodiment of the disclosed technology. The USC code according to the disclosed technique can be decoded using the BCJR algorithm, unlike the conventional LDPC code using the tanh rule for parity check. Hereinafter, for the sake of understanding, a process of decoding the received data using the BCJR algorithm based on the trellis of FIG. 2 will be described as an example. In relation to the present embodiment, a part to which the LDPC decoding scheme is equally applicable may be simply mentioned or omitted.

The SC coupling matrix A may be used in the encoding process as shown in FIG. 4 and may also be used in the decoding process. In the decoding process, the matrix A plays the same role as a parity check matrix in decoding using an LDPC code. As in the LDPC decoding process, based on the Tanner Graph, the USC code may be represented by nodes divided into two sides and edges connected from one node to another node. The nodes on one side of the nodes are variable nodes meaning each bit of the codeword, and the nodes on the other side are SC checks related to SC constraints. . The decoding process can be described by repeating a process of transmitting a message from one node to another node along the branch and updating a message to be delivered based on the received message. As the message delivery and update process is repeated, the accuracy of decryption increases. In this case, the message includes information on the likelihood of the corresponding bit in the coded signal. Likelihood refers to the degree of likelihood that a bit has a value of 1 or 0. As an index representing the likelihood, a case in which a log likelihood ratio (LLR) is used will be described as an example, but is not limited thereto. For example, the variable nodes may be as many as the columns of the matrix A (the length of the codeword N), and the SC nodes are the number of rows of the matrix A (the number of SC bits generated for one codeword). G) There can be as many. Here, the order of the N variable nodes is denoted by j, and the order of the G SC nodes is denoted by i. The variable nodes and the SC nodes are connected to the i th SC node and the j th variable node by edges whenever the values of elements a _{i and j} of the matrix A are 1. In this case, the number of variable nodes connected to the i-th SC node is called m (i), and when the order of m (i) variable nodes is expressed as l, the relationship between l and j is j = π (l). Display. For example, the third variable node of the m (i) variable nodes corresponds to the j = π (3) th variable node of the total N variable nodes. In the case of the matrix A of FIG. 4, when i is 2, the j value of π (3) is 7. Similarly, when the number of SC nodes connected to the j th variable node is q (j), and the order of q (j) SC nodes is expressed as k, the relationship k and i is i = σ (k). Display. That is, the k th node among the q (j) SC nodes corresponds to the i = σ (k) th node among the G SC nodes. The SC node updates the message from each SC node to the variable node according to SC rules. The decoding method using the USC code will be described with reference to FIG. 5.

In operation S510, the decoding apparatus receives an encoded signal in which information bits are combined with state-check bits. According to an embodiment, the decoding apparatus may initialize the likelihood L and the first message U of each bit of the encoded signal based on the received encoded signal (S520). L _j means the LLR of the j th bit (b _j ) of the N-bit encoded signal. The first message U is a message provided by the SC node to the variable node. U _{i , j} is a message provided by the i th SC node to the j th variable node, and has a value L L of b _j estimated by the i th SC node. U _{0 , j} is an observed LLR value of b _j estimated based on the received coded signal value. U _0, U _{i, j} except for _j is initialized to 0, L _j values are initialized to the value of U _{0, j.}

In operation S530, the decoding apparatus calculates values of the second message based on the values of the first message. According to an embodiment, in the j th variable node, q (j) first messages U _{σ (k), j} provided from q (j) SC nodes connected with the j th variable node, where k is from 1 a second message V is calculated based on the integers between q (j). The calculated q (j) second messages V _{j , σ (k)} , where k is an integer between 1 and q (j), are provided by the j th variable node to each of the q (j) SC nodes. is the LLR value of b _j . Among them, the second message V _{j , σ (n) =} V _{j , i} provided to the σ (n) = i-th SC node may be calculated as in Equation 6 according to an embodiment. At this time, it is defined as σ (0) = 0.

The second message provided by the j-th variable node is the sum of the LLR values (U _{σ (k), j} ) of b _j and U _{0 , j} provided by the SC nodes connected to the j-th variable node to the j-th variable node. In this case, the second message V _{j , i} provided to the i-th SC node is determined as a sum value except for the value of the first message U _{i , j} provided from the i-th SC node.

In operation S540, the demodulation device calculates values of the first message based on the values of the second message. According to an embodiment of the present disclosure, the decoding apparatus is further configured to perform operations on bits included in the i-th group based on values of the second message for bits included in the i-th group (where i is 1≤i≤G). 1 The process of calculating the values of the message is performed for each group. Here, the bits included in the i-th group are bits corresponding to a column having a value of 1 in the i-th row of the matrix A, and mean bits corresponding to variable nodes connected to the i-th SC node. The value of the first message is the likelihood of each bit that each SC node estimates for the bits associated with each SC node, based on the likelihood of the neighboring bits of each bit of the bits associated with each SC node. It is estimated. For example, U _{i , j} is the value of the first message provided by the i th SC node to the j th variable node, and j j of the second messages provided from m (i) variable nodes connected to the i th SC node. A value estimated based on the second messages except the second message provided from the variable node. That is, L _j of b _j estimated based on LLR values of bits other than the j th bit among the m (i) bits. Unlike the LDPC code using the tanh rule, the decoding device may calculate the first message value using the BCJR algorithm. In the present embodiment, the BCJR algorithm is performed based on a trellis (eg, the trellis of FIG. 2) indicating a coding state transition according to an encoded signal. The BCJR algorithm sequentially calculates the forward state metric (α) and the backward state metric (β) corresponding to each state of the trellis, and then calculates the posterior probability by using the soft decision of the transmission bit. Value can be obtained. The posterior probability at time t may be calculated as the sum of the posterior transition probabilities at time t. The posterior probability at time t is expressed by Equation 7, and the post-transition probability is expressed by Equation 8.

Here, the posterior probability P (d _t = d) is a probability that the transmission bit value at time t is d (d is 0 or 1). σ (s _t , s _{t +1} ) is the probability of post-transition at time t, σ (s _t = a, s _{t +1} = b) is that state at time t (s _t ) is state a, and It means the probability that the state s _{t +1} at t + 1 is the state b. At this time, state b is a state value transitioned at time t + 1 when the state at time t is state a and the transmission bit value at time t is d. s _t has a value of any one of coding states given by the state number N _s .

Here, α (s _t) is the state at time t-forward state metric of s _t, in the β _{(t +1} s) of time t + 1 is the backward state metric of the state s _t at _+1, γ _(t s, s _{t +1} ) is the branch metric that links between s _t and s _{t +1} .

In the present embodiment, although the conventional BCJR is applied, only the LLR values (extrinsic information) of bits other than the self are reflected in the process of estimating the LLR value thereof. Do not multiply the values of the metric.

According to an embodiment, the process of the decoding apparatus calculating the values of the first messages based on the values of the second message using the BCJR algorithm is as follows. For convenience of description, in the i th SC node, the m (i) second messages V _{π (l), i} provided by the i th SC node from the variable nodes, where l is from 1 to m (i) A process of calculating the value of m (i) first messages U _{i , π (l)} (where l is an integer between 1 and m (i)) based on an integer between .

First, the decoding apparatus determines the value of branch metrics based on the values of the second message. At this time, the values of the second message are input values of the BCJR algorithm and correspond to the pre-LLR values of respective transmission bits in the BCJR algorithm. According to an embodiment, the branch metrics at time t = l may be determined based on the value of V _{pi (l), i} , which is the first l-th message of m (i). For example, the metric of the branch corresponding to bit 0 of the branch metrics at time t = l is determined from the value of V _{π (l), i} as a probability that the bit value at time t = l is 0 and corresponds to bit 1 One metric is also determined by the probability that the bit value at time t = l is 1 from the value of V _{pi (l), i} .

This may be expressed as an equation (9).

When the branch metric is calculated, the decoding apparatus sequentially calculates the forward state metric as shown in Equation 10, and calculates the backward state metrics in the reverse order as shown in Equation 11.

The decoding apparatus calculates a value of the first message for the t th bit among the m (i) bits based on the product of the t th forward state metric and the t + 1 th backward state metric. According to an embodiment, the value of the first message U _{i , π (n)} provided to the t = n-th variable node (where n is an integer of 1 ≦ n ≦ m (i)) is calculated as shown in Equation 12. It can be calculated as the sum of the post-transition probabilities. For example, the value of the first message U _{i , π (n)} may be determined as a value obtained by converting the posterior probability P (d _n ) of the n th transmission bits calculated according to Equations 12 and 7 in the BCJR algorithm to LLR. Can be.

The value U _{i , π (n)} of the first message provided to the j = π (n) th variable node corresponding to t = n is the value of the second message provided from the j = π (n) th variable node ( Since it does not reflect V _{π (n), i} ), unlike Equation 8, Equation 12 excludes various metrics from the equation.

As such, the values of the first message are output values of the BCJR algorithm and are determined based on post-transition probabilities calculated as in Equation 12.

As described above, an operation of calculating the value U of the first message from the value V of the second message by the BCJR algorithm may be simply expressed as in Equation 14.

Thereafter, the decoding apparatus repeats steps S530 and S540 by using the newly calculated values of the first message and the values of the second message (S550). That is, the decoding apparatus calculates a second message using the first message calculated in the previous iteration, and repeats the process of updating the first message using the newly calculated second message by a predetermined amount.

Screen in step S550 decryption apparatus determines the value of each bit (b _j), depending on also available for each bit (b _j) is estimated on the basis of the value of the first message determined in a last repetition. According to an embodiment, L _{j, which} is an LLR value of b _j , may be calculated as in Equation 15.

The decoding apparatus determines whether the value of b _j is 1 or 0 depending on whether the value of L _j is smaller than 1 or larger than 1.

While the system and apparatus disclosed herein have been described with reference to the embodiments shown in the drawings for purposes of clarity of understanding, they are illustrative only and various modifications and equivalent embodiments can be made by those skilled in the art. I will understand that. Accordingly, the true scope of protection of the disclosed technology should be determined by the appended claims.

Claims (12)

(a) determining an encoding state according to selected information bits among information bits constituting the information bit string;
(b) determining state-check bits based on the encoding state;
(c) repeating steps (a) and (b) at least once using newly selected information bits of the information bits constituting the information bit string; And
(d) combining the information bit string and the state-check bits to generate a codeword. The method of claim 1, wherein the step (b)
And determining the value of the input bits as the state-check bits to cause the encoding state to converge to a preset state. The method of claim 1, wherein the step (b)
And determining the value of the input bits as the state-check bits to cause the coding state to converge to a zero state. The method of claim 1, wherein the step (a)
And encoding the current state updated in the last iteration as the encoded state by repeating the updating of the current state a plurality of times in accordance with a current state and a currently input bit. The method of claim 1, wherein the step (a)
(a1) receiving any one of the selected information bits not previously input;
(a2) transitioning from a current state to a next state according to the received bit;
(a3) repeating the receiving step and the transitioning step a plurality of times;
(a4) encoding the transition state in the last iteration as the encoding state. The method of claim 5, wherein step (a2) comprises:
And transitioning to a state determined according to the received bit among two states corresponding to the current state. The method of claim 5, wherein step (a2) comprises:
The current state in the k-th iteration is N bits [d _{N -1, k} ... d _{0 , k} ]
d _{n , k + 1} = d _{n + 1, k} (where n = 0, ..., N-2)

Where i _k is the information bit received in the current iteration,

Means an exclusive OR (XOR) operation, and d _k Denotes a value obtained by performing XOR operation on at least one bit selected from d _{0 , k} to d _{N -1, k} ), wherein N bits [d _{N −1, k + 1} ... d _{0 , k + 1} ]. A method of transitioning to the next state represented by d. The method of claim 5, wherein step (a2) comprises:
The current state in the k-th iteration is N bits [d _{N -1, k} ... d _{0 , k} ]
d _{n , k + 1} = d _{n + 1, k} (where n = 0, ..., N-2)

Where i _k is the information bit received in the current iteration,

Denotes an exclusive OR (XOR) operation, wherein a ₁ to a _{N -1} has a value of 0 or 1, and N bits [d _{N −1, k + 1} ... d _{0 , k + 1} ]. A method of transitioning to the next state represented by d. The method of claim 5, wherein step (a2) comprises:
Performing an XOR operation between the input bit and at least one of the bits representing the current state when the bit is input; And
Shifting the bits representing the current state stored in the register to the lower bit position by one bit, and storing the result of the XOR operation in the most significant bit position to update the value of the register with the value of the bit representing the next state. An encoding method comprising the steps. The method of claim 1,
And the number of bits of the selected information bits is smaller than the number of information bits constituting the information bit string. (a) receiving an encoded signal in which information bits are combined with state-check bits;
(b) a second value based on the value of the first message, wherein the value of the first message indicates the likelihood of each bit estimated based on the likelihood of the surrounding bits of each bit of the encoded signal. Calculating values of the message;
(c) calculating values of the first message based on the values of the second message using a trellis based BCJR algorithm indicating a transition state of encoding according to the information bits;
(d) repeating steps (b) and (c) using the newly calculated values of the first message and the values of the second message; And
(e) determining the value of each bit according to the likelihood of each bit estimated based on the values of the first message calculated in the last iteration. 12. The method of claim 11, wherein step (c) comprises: the bits included in the i-th group based on the values of the second message for the bits included in the i-th (where i is 1≤i≤G) group. Computing the values of the first message for each group is performed for each group, the calculating process,
(c1) calculating forward state metrics and backward state metrics based on the values of the second message;
(c2) calculating a value of the first message for the k th bit of the i th group of bits based on the product of the k th forward state metric and the k + 1 th backward state metric.

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