JP5490931B2 - Encoder, decoder, encoding method, and decoding method - Google Patents

Description

  The present invention relates to an encoder, a decoder, an encoding method, and a decoding method that perform error correction encoding / decoding using a low-density parity-check convolutional code (LDPC-CC). .

  In recent years, attention has been focused on a low-density parity check (LDPC) code as an error correction code that exhibits high error correction capability with a feasible circuit scale. The LDPC code is adopted in an error correction coding system such as an IEEE802.11n high-speed wireless local area network (LAN) system or a digital broadcasting system because of its high error correction capability and ease of implementation.

  The LDPC code is an error correction code defined by a parity check matrix H having a low density (the number of 1 elements included in the matrix is significantly smaller than the number of 0 elements). The LDPC code is a block code having a block length equal to the number N of columns of the check matrix H.

  However, many of the current communication systems are characterized by performing communication based on variable-length packets and frames, such as Ethernet (registered trademark). When an LDPC code that is a block code is applied to such a system, for example, there is a problem of how a block of a fixed-length LDPC code corresponds to a variable-length Ethernet (registered trademark) frame. . In IEEE802.11n, which is a wireless LAN standard that employs an LDPC code, padding and puncturing are applied to a transmission information sequence to adjust the length of the transmission information sequence and the block length of the LDPC code. However, there is a problem that a coding rate change or redundant sequence transmission is required due to padding and puncturing.

  An LDPC code of such a block code (hereinafter referred to as “LDPC-BC: Low-Density Parity-Check Block Code”) can be encoded / decoded for an information sequence of any length. A low-density parity-check convolutional code (LDPC-CC) has been studied (see Non-Patent Document 1).

LDPC-CC is a convolutional code defined by a low-density parity check matrix. FIG. 54 shows, as an example, an LDPC-CC parity check matrix H _{[0, n]} ^T with a coding rate R = 1/2 (= b / c).

In LDPC-CC, elements h ₁ ^(m) (t) and h ₂ ^(m) (t) of parity check matrix H _{[0, n]} ^T take 0 or 1. In addition, all elements other than h ₁ ^(m) (t) and h ₂ ^(m) (t) included in the check matrix H [0, n] ^T are 0. In the figure, M represents the memory length in LDPC-CC, and n represents the length of the transmission information sequence. As shown in FIG. 54, in the LDPC-CC parity check matrix, 1 is set only in the diagonal term of the matrix and the elements in the vicinity thereof, the elements in the lower left and upper right of the matrix are zero, and the parallelogram There is a feature that it is a matrix.

なお、ｕ_ｔは送信情報系列を表し、ｖ_１,ｔ，ｖ_２,ｔは送信符号語系列を表す。 Here, when an example of coding rate R = 1/2 (= b / c) is shown, when h ₁ ⁽⁰⁾ (t), h ₂ ⁽⁰⁾ (t) = 1, LDPC-CC Encoding is performed using Equation (1) and Equation (2) according to the parity check matrix H _{[0, n]} ^{T in} FIG.

Note that u _t represents a transmission information sequence, and v _{1, t} , v _{2, t} represents a transmission codeword sequence.

  FIG. 55 shows a configuration example of an LDPC-CC encoder that performs equations (1) and (2). As shown in FIG. 55, the LDPC-CC encoder 10 includes shift registers 11-1 to 11-M, 14-1 to 14-M, weight multipliers 12-0 to 12-M, 13-0 to 13-. M, a weight control unit 16, and a mod 2 adder 15.

The shift registers 11-1 to 11-M and 14-1 to 14-M are registers that hold v1 _{, ti} , v2 _{, ti} (i = 0,..., M), respectively. Is input to the shift register on the right and the value output from the shift register on the left is newly stored.

The weight multipliers 12-0 to 12-M and 13-0 to 13-M set the values of h ₁ ^(m) and h ₂ ^(m) to 0/1 according to the control signal output from the weight control unit 16. Switch. The weight control unit 16 determines the values of h ₁ ^(m) and h ₂ ^{(m) at} the timing based on the check matrix held inside the weight multipliers 12-0 to 12-M, 13-0. Output to 13-M.

The mod2 adder 15 performs mod2 addition on the outputs of the weight multipliers 12-0 to 12-M, 13-0 to 13-M, and calculates v2 _{, t} .

  By adopting such a configuration, LDPC-CC encoder 10 can perform LDPC-CC encoding according to a parity check matrix.

  The LDPC-CC encoder can be realized with a very simple circuit compared to an encoder circuit that performs multiplication of a generator matrix and an LDPC-BC encoder that performs an operation based on a backward substitution method or a forward substitution method. is there. Also, since LDPC-CC is a convolutional code, it is not necessary to encode a transmission information sequence by dividing it into fixed-length blocks, and an information sequence of an arbitrary length can be encoded.

  A sum-product algorithm based on the parity check matrix H can be applied to LDPC-CC decoding as in LDPC-BC. Therefore, it is not necessary to use a decoding algorithm based on maximum likelihood sequence estimation like the Viterbi algorithm, and the decoding process can be completed with a low processing delay time. Furthermore, Non-Patent Document 1 proposes a decoding algorithm that takes advantage of the form of a parity check matrix that 1 stands in the shape of a parallelogram (Patent Document 1).

  It has been shown that when the decoding characteristics of LDPC-CC and LDPC-BC are compared with parameters having the same circuit scale of the decoder, the decoding characteristics of LDPC-CC are superior (see Non-Patent Document 1). ).

  In LDPC-CC, when encoding is completed with an arbitrary length n, when the received codeword sequence is decoded in the decoder on the receiving side, the probability propagation of the rear c × M bits in the sum-product decoding is added. In order to make it equal to the bits of n, a code word obtained by encoding the transmission information series after n and the state of the shift register at the end of encoding are required.

  However, if the transmission information sequence is simply encoded, the state of the shift register of the encoder at the end of encoding depends on the transmission information sequence, so that the state is uniquely determined when decoding on the receiving side. It is difficult.

  In such a situation, when decoding processing is performed on the receiving side based on the received codeword, a phenomenon occurs in which errors increase toward the end of the received information sequence obtained after decoding, particularly the rear c × M bits.

  In order to avoid such an error, it is necessary to perform termination processing (termination) for uniquely determining the end state of encoding on the transmission information sequence.

  In a convolutional code conforming to IEEE802.11a, termination processing is performed by adding the same number (six) of 0 bits as the shift register of the encoder called tail bits to the rear part of the transmission information sequence. In this way, the state of the shift register of the encoder can be set to all zeros when the tail bits have been input. Note that the codeword output when the tail bit is input is necessary for decoding on the reception side, and is therefore transmitted to the reception side together with the transmission codeword.

For LDPC-CC, as shown in equation (2), to determine the codeword v _{2, t,} since the codeword v _{2, t-i} for the past M-time is required, LDPC-CC code The device is provided with a shift register that holds code words v _{2, t-i} of the past M times. Register that holds the transmission information sequence, can be all zeros state by which a sequence of all zeros of length M the end of a transmission information sequence (termination), only this termination processing, codeword v _{2, t} There is a problem that it is difficult to set the shift register holding _-i to an all-zero state.

  Non-Patent Document 2 proposes a termination process in which the state of the shift register at the end of encoding is made all-zero by encoding after adding a termination sequence that is not all-zero to the rear part of the transmission information sequence.

In the termination processing proposed in Non-Patent Document 2, a transmission codeword sequence is defined as in Expression (3). Equation (3) is an example when the coding rate R = 1/2. In Expression (3), v _{1 × 2n} is a codeword sequence having a length of 2n obtained by convolutionally encoding an information sequence having a length n, and x _{1 × 2L} is a terminal sequence having a length L. Is a terminal codeword sequence obtained by encoding, and 0 _{1 × 2M} is a 0 sequence having a length of 2M.

Here, the termination sequence x _{1 × 2L} is determined by Equation (4) and Equation (5).

  By encoding the transmission codeword sequence to which such a termination sequence is added with an LDPC-CC encoder, the state of the shift register can be set to the all-zero state. The transmitting communication device transmits the transmission codeword thus terminated to the receiving device, so that the receiving decoder uniquely determines the state of the shift register at the end of encoding. Error correction decoding with desired performance.

FIG. 56 shows a configuration of an LDPC-CC encoder to which a termination sequence generation unit that generates termination sequence x _{1 × 2L} shown in Expression (5) is added. An LDPC-CC encoder 20 shown in FIG. 56 includes a termination sequence generation unit 17, a check matrix storage unit 18, and a switcher 19 in addition to the components of the LDPC-CC encoder 10.

  The parity check matrix storage unit 18 stores an LDPC-CC parity check matrix.

The termination sequence generation unit 17 generates the termination sequence x _{1 × 2L} according to Equation (5) by using the parity check matrix stored in the parity check matrix storage unit 18 and v _{1, t} , v _{2, t.} The terminal sequence x _{1 × 2L} obtained is output to the switch 19.

  The switch 19 switches the sequence output to the shift register 11-1 to either the transmission information sequence or the termination sequence based on the termination processing control signal. Specifically, the switcher 19 outputs the transmission information sequence to the shift register 11-1 when the termination processing control signal indicates encoding of the transmission information sequence, and the termination processing control signal indicates termination processing. The terminal sequence is output to the shift register 11-1.

  FIG. 57 shows an input sequence and an output sequence of the LDPC-CC encoder 20. FIG. 57A shows an input sequence input to the LDPC-CC encoder 20, and FIG. 57B shows an output sequence output from the LDPC-CC encoder 20. In FIG. 57, the time series are along the direction from the right to the left of each series.

  The input sequence of the LDPC-CC encoder 20 is composed of an information sequence consisting of n bits, a padding sequence consisting of 0 to M bits, and a termination sequence consisting of (M + 1) bits.

Here, since the length n of the information sequence is arbitrary, the weight controller 12-0 to the weight multipliers 12-0 to 12-M, 13-0 is used when the encoding of the information sequence is completed according to the value of n. The weight pattern output to .about.13-M is different. This indicates that D _{2L × (L + M} ) in Equation (5) differs depending on n. As a result, there are cases where D _{2L × (L + M)} becomes a full rank and not. Therefore, D _{2L × (L + M)} for obtaining the termination sequence varies depending on the number of bits n of the information sequence. Therefore, a padding sequence of K (K = 0 to M) bits is inserted after the information sequence in order to make D _{2L × (L + M)} when performing the termination process the same regardless of the number of bits n of the information sequence. The padding sequence may be any sequence as long as it is a known sequence on the encoding side and the decoding side. For example, an all-zero sequence can be used.

  The padding sequence and the termination sequence are sequences necessary for termination processing, and do not include any information other than the purpose of padding and termination processing.

  The output sequence of the LDPC-CC encoder 20 includes a codeword sequence obtained by encoding a padding sequence and a termination sequence in addition to a codeword sequence obtained by encoding an information sequence. As a result, the overhead during information transmission is (K + M + 1) × c bits. Here, K represents the length of the padding sequence, and c represents the denominator of the coding rate R = b / c of the LDPC-CC code.

US Pat. No. 60,682,178

Alberto Jimenez Felstorom, and Kamil Sh. Zigangirov, “Time-Varying Periodic Convolutional Codes With Low-Density Parity-Check Matrix,” IEEE Transactions on Information Theory, Vol. 45, No. 6, pp2181-2191, September 1999. Zhengang Chen, Stephen Bates, and Ziaodai Dong, “Low-Density Parity-Check Convolutional Codes Applied to Packet Based Communication Systems,” Proceeding of IEEE Globecom 2005, pp1250-1254. Stephen Bates, Duncan G. Elliott, Ramkrishna Swamy, “Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes,” IEEE Transactions on Circuits and Systems-1: Regular Papers, Vol. 53, No. 9, September 2006. R. D. Gallager, “Low-Density Parity-Check Codes,” Cambridge, MA: MIT Press, 1963. MPC Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low density parity check codes based on belief propagation,” IEEE Trans. Commun., Vol.47., No.5, pp.673-680, May 1999. J. Chen, A. Dholakia, E. Eleftheriou, MPC Fossorier, and X.-Yu Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun., Vol.53., No.8, pp.1288 -1299, Aug. 2005. Yuichi Ogawa, “sum-product decoding of turbo codes,” Master's thesis, Nagaoka University of Technology, 2007. S. Lin, D. J. Jr., Costello, “Error control coding: Fundamentals and applications,” Prentice-Hall. RM Tanner, D. Sridhara, A. Sridharan, TE Fuja, and DJ Costello Jr., “LDPC block and convolutional codes based on circulant matrices,” IEEE Trans. Inform. Theory, vol.50, no.12, pp.2966 -2984, Dec. 2004. G. Richter, M. Kaupper, and K. Sh. Zigangirov, “Irregular low-density parity-Check convolutional codes based on protographs,” Proceeding of IEEE ISIT 2006, pp1633-1637.

However, the conventional configuration requires a configuration for generating an end sequence x _{1 × 2L} in the LDPC-CC encoder, and there is a problem that the circuit scale of the encoder increases. As an example, Non-Patent Document 3 describes that when a termination sequence generation circuit is added to an LDPC-CC encoder, the circuit scale is about seven times that of an LDPC-CC encoder.

  In addition, the conventional configuration requires a (K + M + 1) × c bit sequence as the terminal sequence length to be transmitted, and there is a problem of an increase in overhead amount and deterioration in transmission efficiency due to the output of a redundant signal sequence. For example, when transmitting an 8000-bit transmission information sequence using an LDPC-CC with a memory length M = 200, 400 bits or more, that is, 5% or more redundant bits of the transmission information sequence must be transmitted for termination processing. Don't be.

  The present invention has been made in view of such points, and provides an LDPC-CC coding termination sequence with a simple configuration, and can reduce the amount of termination sequences transmitted to a transmission line. An object is to provide an encoding method and a decoding method.

  One aspect of the encoder of the present invention is a low-density parity check convolutional code (LDPC-CC) check for an information sequence and a termination sequence of (M × b) bits or less. An information code sequence obtained by performing convolutional coding with a coding rate R = b / c and a memory length M according to a matrix and coding the information sequence, and a termination sequence of (M × b) bits or less. A terminal code sequence obtained by encoding, and a coding unit that outputs the information sequence, the information code sequence, and a concatenation unit that outputs a codeword concatenating the terminal code sequence, The sequence adopts a configuration that is a known sequence even in a decoder that is a communication partner of the code word.

  One aspect of the decoder of the present invention is a convolution with a coding rate R = b / c and a memory length M according to a low-density parity-check convolutional code (LDPC-CC) check matrix. A decoder that performs decoding, wherein a termination sequence that is a known sequence in the encoder that is a communication partner is concatenated with an input codeword, and the termination sequence and an information sequence included in the input codeword The estimated values of the information code sequence obtained by encoding the information sequence and the termination code sequence obtained by encoding the termination sequence are set as input sequences, and BP (Belief Propagation) decoding is performed, and an estimated information sequence obtained by BP decoding is output.

  One aspect of the coding method according to the present invention is that a low-density parity check convolutional code (LDPC-CC) is applied to an information sequence and a terminal sequence of (M × b) bits or less. In accordance with a parity check matrix, convolutional coding with an encoding rate of R = b / c and a memory length of M is performed, and the information sequence and a termination sequence of (M × b) bits or less are used as input sequences. A step of performing coding based on a matrix, the information sequence, an information code sequence obtained by coding the information sequence, and a termination code sequence obtained by coding the termination sequence. And outputting the code word, and the termination sequence is a sequence known also in the decoder which is a communication partner of the code word.

  One aspect of the decoding method of the present invention is a convolution with a coding rate R = b / c and a memory length M according to a low-density parity-check convolutional code (LDPC-CC) check matrix. A decoding method for performing decoding, comprising: a step of concatenating a terminal sequence, which is a known sequence even in an encoder as a communication partner, to an input codeword; and the terminal sequence and the input codeword An estimated value of each of an information sequence, an information code sequence obtained by encoding the information sequence, and a termination code sequence obtained by encoding the termination sequence is used as an input sequence, and BP is input to the input sequence. (Belief Propagation) decoding and a step of outputting an estimated information sequence obtained by BP decoding.

  ADVANTAGE OF THE INVENTION According to this invention, the termination sequence of LDPC-CC encoding can be provided with a simple structure, and the quantity of termination sequences transmitted to a transmission line can be reduced.

The figure which shows an example of the LDPC-CC check matrix in this Embodiment 1. FIG. The figure which shows the information partial check matrix in Embodiment 1 The figure which shows the parity partial check matrix in Embodiment 1. FIG. FIG. 2 is a block diagram showing a configuration of an LDPC-CC encoder in Embodiment 1 FIG. 3 is a block diagram showing the internal configuration of the first encoder in the first embodiment. The figure which shows the weight pattern currently hold | maintained at the weight control part in Embodiment 1. Block diagram showing the internal configuration of the second encoder in the first embodiment The figure which shows the input sequence and output sequence of the LDPC-CC encoder in Embodiment 1 FIG. 5 is a block diagram showing another configuration of the LDPC-CC encoder in the first embodiment. The figure which shows the input sequence and output sequence of the LDPC-CC encoder in Embodiment 1 FIG. 5 is a block diagram showing another configuration of the LDPC-CC encoder in the first embodiment. The figure which shows another example of the LDPC-CC parity check matrix in Embodiment 1. FIG. FIG. 10 is a diagram illustrating another example of the parity partial check matrix in the first embodiment. Block diagram showing another internal configuration of the second encoder according to the first embodiment The figure which shows the time-varying parity partial check matrix in Embodiment 1. Block diagram showing another internal configuration of the second encoder according to the first embodiment FIG. 3 is a block diagram showing another internal configuration of the first encoder in the first embodiment. The figure which shows an example of the LDPC-CC check matrix in this Embodiment 2. FIG. The figure which shows the information partial check matrix in Embodiment 2 The figure which shows the parity partial check matrix in Embodiment 2. Block diagram showing a configuration of an LDPC-CC encoder in the second embodiment Block diagram showing the internal configuration of the first encoder in the second embodiment Block diagram showing an internal configuration of a second encoder in the second embodiment Block diagram showing another internal configuration of the first encoder in the second embodiment The figure which shows an example of the LDPC-CC check matrix in this Embodiment 3. FIG. The figure which shows the information partial test | inspection matrix in Embodiment 3. The figure which shows the parity partial check matrix in Embodiment 3. Block diagram showing a configuration of an LDPC-CC encoder in Embodiment 3 FIG. 9 is a block diagram showing the internal configuration of the first encoder in the third embodiment. Block diagram showing an internal configuration of the second encoder in the third embodiment The figure which shows the input sequence and output sequence of the LDPC-CC encoder in Embodiment 3 FIG. 18 is a diagram illustrating another example of the parity partial check matrix in the third embodiment FIG. 9 is a block diagram showing another configuration of the LDPC-CC encoder in the third embodiment. Block diagram showing another internal configuration of the second encoder in the third embodiment Block diagram showing a configuration of an LDPC-CC encoder in the fourth embodiment The figure which shows the termination | terminus part of the LDPC-CC check matrix in Embodiment 4. The figure which shows the termination | terminus part of the LDPC-CC check matrix in Embodiment 1 The figure which shows the input sequence and output sequence of the LDPC-CC encoder in this Embodiment 5. The figure which shows the termination | terminus part of the LDPC-CC check matrix in Embodiment 5 The figure which shows the input sequence and output sequence of the LDPC-CC decoder in Embodiment 5 The figure which shows the termination | terminus part of the LDPC-CC check matrix in Embodiment 5 The figure which shows the encoder of a (7,5) convolutional code. The figure which shows the check matrix of a (7,5) convolutional code. The figure which shows the check matrix of a (7,5) convolutional code. The figure which shows an example at the time of adding "1" to the approximate lower triangular matrix of the check matrix of FIG. The figure which shows an example of a structure of the check matrix of LDPC-CC in other Embodiment 1. FIG. The figure which shows the check matrix of a (7,5) convolutional code. The figure which shows an example of a structure of the check matrix of LDPC-CC in other Embodiment 1. FIG. The figure which shows an example of a structure of the check matrix of LDPC-CC in other Embodiment 2. FIG. The figure which shows an example of a structure of the check matrix of LDPC-CC of the time-varying period 1 in other Embodiment 2. The figure which shows an example of a structure of the check matrix of LDPC-CC of the time-varying period m in other Embodiment 2. FIG. Illustration for explaining the number of puncture patterns The figure which shows the relationship between an encoding sequence and a puncture pattern Diagram showing the number of parity check polynomials that must be checked to select a puncture pattern The figure which shows an example of a structure of the check matrix of LDPC-CC of time-varying period 2 The figure which shows an example of a structure of the check matrix of LDPC-CC of time-varying period 4 The figure which shows an example of the conventional LDPC-CC check matrix Block diagram showing a configuration example of a conventional LDPC-CC encoder Block diagram showing a configuration example of an LDPC-CC encoder to which a conventional termination sequence generator is added The figure which shows the input sequence and output sequence of the conventional LDPC-CC encoder

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the present embodiment, an LDPC-CC encoder that performs LDPC-CC encoding and a termination processing method thereof will be described.

  FIG. 1 shows an example of a parity check matrix of LDPC-CC in the present embodiment. 1 is a parity check matrix that defines a periodic time-varying LDPC-CC with a coding rate R = 1/2 and a memory length M = 5. Here, the periodic time variation indicates that the 1/0 arrangement pattern in the check matrix is different for each column and that the pattern has periodicity.

  In FIG. 1, each row of the parity check matrix 100 corresponds to a parity check equation (parity check equation). In FIG. 1, c1, c2,... Are labeled on the parity check expression of each row. Each column of parity check matrix 100 corresponds to each bit of the transmission codeword sequence. 1 is a parity check matrix that defines a systematic code. Each column includes a first information bit u1, a first parity bit p1, a second information bit u2, and a second bit of a transmission codeword sequence. Are arranged in the order of parity bits p2,.

  FIG. 2 shows a partial parity check matrix (hereinafter, also referred to as “information partial parity check matrix”) 110 obtained by extracting columns corresponding to information bits from parity check matrix 100. FIG. 3 shows a partial parity check matrix (hereinafter also referred to as “parity partial parity check matrix”) 120 obtained by extracting columns corresponding to parity bits from parity check matrix 100.

  As shown in FIGS. 2 and 3, the LDPC-CC encoder in the present embodiment decomposes the parity check matrix 100 into an information partial parity check matrix 110 and a parity partial parity check matrix 120, and then LDPC-CC code. It is characterized by performing.

  FIG. 4 shows an example of the configuration of the LDPC-CC encoder in the present embodiment. The LDPC-CC encoder 200 of FIG. 4 includes a first encoder 230 and a second encoder 240. In addition to LDPC-CC encoder 200, FIG. 4 shows termination sequence generator 210, termination sequence concatenation unit 220, and codeword concatenation unit 250. LDPC-CC encoder 200 A systematic code is encoded in which the sequence appears in the transmission codeword sequence as it is.

  Termination sequence generation section 210 generates a termination sequence necessary for performing termination processing of LDPC-CC encoder 200, and outputs the generated termination sequence to termination sequence connection section 220.

  The termination sequence concatenation unit 220 receives the information sequence and the termination sequence output from the termination sequence generation unit 210, and concatenates the termination sequence to the tail of the information sequence. The termination sequence concatenation unit 220 outputs the concatenated information sequence and termination sequence to the first encoder 230. In this way, the termination sequence provided from termination sequence generation section 210 is input to first encoder 230 as the input sequence of first encoder 230. Also, termination sequence concatenation unit 220 outputs the concatenated information sequence and termination sequence to codeword concatenation unit 250.

  The first encoder 230 performs coding on the information sequence or the termination sequence output from the termination sequence concatenation unit 220 based on the information partial check matrix 110, and acquires the first codeword sequence. The first encoder 230 outputs the first codeword sequence to the second encoder 240.

  Second encoder 240 encodes the first codeword sequence output from first encoder 230 based on parity partial check matrix 120 to obtain a second codeword sequence. Second encoder 240 outputs the second codeword sequence to codeword concatenation unit 250.

  The codeword concatenation unit 250 concatenates the information sequence, the termination sequence, and the second codeword sequence, generates a transmission codeword sequence, and outputs the transmission codeword sequence as a codeword.

  As described above, the LDPC-CC encoder 200 uses the information partial parity check matrix 110 obtained by extracting the column corresponding to the information bits from the parity check matrix 100, and extracts the column corresponding to the parity bits from the parity check matrix 100. Coding using the parity partial check matrix 120 is performed concatenatedly.

(First encoder)
FIG. 5 shows the internal configuration of the first encoder 230. The first encoder 230 in FIG. 5 is a convolutional encoder that uses each row of the information partial check matrix 110 as a coefficient of a generator polynomial (an expression representing a connection between a shift register and a mod2 adder). The first encoder 230 is a non-recursive convolutional encoder with four delay units, and codes an input sequence based on a generator polynomial corresponding to 1/0 arrangement of each column of the information partial check matrix 110. Do.

  In FIG. 5, the first encoder 230 includes shift registers 231-1 to 231-4, weight multipliers 232-0 to 232-4, a weight control unit 233, and a mod2 adder 234. If the number of shift registers of the first encoder is M1, the first encoder 230 shown in FIG. 5 is an example in the case of M1 = 4. M1 is the memory length of the first encoder.

  The shift registers 231-1 to 231-4 are registers that hold input bits, and at the timing when the next input is input, the held values are output to the shift register on the right and the shift register on the left Holds the value output from.

  The weight multipliers 232-0 to 232-4 multiply the outputs of the shift registers 231-1 to 231-4 by weight values according to the weight pattern output from the weight control unit 233.

  The weight control unit 233 outputs the weight value at the timing to the weight multipliers 232-0 to 232-4 based on the weight pattern held inside.

The mod2 adder 234 performs mod2 addition of the output results of the weight multipliers 232-0 to 232-4, and calculates the mod2 addition result as the codeword bits v _{c1, t} of the first codeword sequence.

  FIG. 6 shows a weight pattern held in the weight control unit 233. Note that the weight pattern in FIG. 6 is obtained by aligning 1/0 positions of each row of the information partial parity check matrix 110 in FIG. As shown in FIG. 2, since the 1/0 arrangement of each row of the information partial parity check matrix 110 has four types of patterns repeatedly arranged, the weight control unit 233 has four weight patterns (weight patterns 1 to 4). ).

  The weight control unit 233 sequentially outputs the weight patterns 1 to 4 shown in FIG. 6A shows the weight value output to the weight multiplier 232-0, FIG. 6B shows the weight value output to the weight multiplier 232-1, and FIG. ) Shows the weight value output to the weight multiplier 232-2, FIG. 6D shows the weight value output to the weight multiplier 232-3, and FIG. 6E shows the weight multiplier 232-4. Indicates the weight value to be output.

(Second encoder)
Second encoder 240 performs encoding based on the 1/0 sequence of each row of parity partial check matrix 120. As shown in FIG. 3, the 1/0 arrangement of each row of the parity partial check matrix 120 is {1, 0, 0, 0, 0, 1}. This indicates that the parity bit at a certain time point is obtained by adding mod 2 the input at that time point and the parity bit at the five time points before that time point. For example, the parity bit at the time point p6 is obtained by mod2 addition of the input of the second encoder 240 at the time point p6 and the parity bit p1 obtained at the time point p1.

  Therefore, encoding based on the 1/0 sequence of each row of the parity sub-check matrix 120 is performed by using a differential encoder having five delay units, a recursive convolutional encoder having five delay units, or the number of delay units. It can be realized with five accumulators.

  FIG. 7 shows the internal configuration of the second encoder 240. The second encoder 240 shown in FIG. 7 includes shift registers 241-1 to 241-5 and a mod2 adder 242. Assuming that the number of delay units of the second encoder is M2, the second encoder 240 of FIG. 7 is an example in the case of M2 = 5. M2 is the memory length of the second encoder.

The shift registers 241-1 to 241-5 are registers that hold the parity bit pt _-i , and at the timing when the next input is input, the held value is output to the shift register on the left and the right side. Holds the value output from the adjacent shift register.

The mod2 adder 242 performs mod2 addition of the codeword bits v _{c1, t of} the first codeword sequence input to the second encoder 240 and the output of the shift register 241-1 and the parity obtained from the addition result Bit p _t is output to codeword concatenation unit 250 as codeword bits _{vc2, t} of the second codeword sequence. Note that the codeword bit _{v c2, t} of the second codeword sequence is equivalent to _{v 2, t} shown in equation (2).

  The codeword concatenation unit 250 concatenates the information sequence or termination sequence and the second codeword sequence output from the second encoder 240, and outputs the concatenated sequence as a transmission codeword sequence.

In this way, the first encoder 230 performs encoding on the input sequence to calculate the codeword bits v _{c1, t} of the first codeword sequence, and the second encoder 240 performs the first codeword sequence. Codeword bits v _{c1, t} are input, and codeword bits v _{c2, t} of the second codeword sequence are calculated.

In this way, by connecting the first encoder 230 and the second encoder 240, the codeword bits _{vc2, t} of the LDPC-CC codeword sequence can be calculated by LDPC-CC encoding. This is because the codeword bits v _{2 and t} are generated by the equation (2).

  Note that the memory size of the LDPC-CC encoder is M = max (M1, M2). M1 indicates the number of delay units (shift registers) of the first encoder, M2 indicates the number of delay units (shift registers) of the second encoder, and max (·) is the maximum number in (·). Represents taking.

  Hereinafter, termination processing of the LDPC-CC encoder 200 configured as described above will be described.

(Termination processing)
In FIG. 4, termination sequence generation section 210 generates a termination sequence for terminating LDPC-CC encoder 200 and provides the termination sequence to termination sequence concatenation section 220. The termination sequence is as follows from the configuration of the first encoder 230 and the second encoder 240.

  Since the first encoder 230 in the present embodiment is a non-recursive convolutional encoder as shown in FIG. 5, a zero sequence having the same number of bits as the number of shift registers M1, that is, a 4-bit zero sequence is the first. By inputting to the encoder 230, the states of the shift registers 231-1 to 231-4 at the end of encoding can be all zero. That is, the termination sequence for terminating the first encoder 230 is {0, 0, 0, 0}.

  On the other hand, as shown in FIG. 7, second encoder 240 in the present embodiment is a differential encoder having five delay units (shift registers), and the value held in each shift register is It is output to the communication channel at the previous time. Therefore, on the decoding side, the state of the shift register can be uniquely determined by using the received codeword, so that the termination process of the second encoder 240 is not necessary.

  From the above, the termination sequence necessary for termination processing of the LDPC-CC encoder 200 is the same number of zero sequences as the number of shift registers (M1) of the first encoder 230. Therefore, the termination sequence generation unit 210 may generate a 4-bit (M1 × b bit) zero sequence as the termination sequence and provide it to the termination sequence connection unit 220.

  Termination sequence concatenation unit 220 concatenates the termination sequence provided from termination sequence generation unit 210 to the end of the information sequence, and outputs the concatenated information sequence and termination sequence to first encoder 230.

  FIG. 8 shows the relationship between the input sequence and output sequence of LDPC-CC encoder 200. FIG. 8A shows an input sequence of the first encoder 230. FIG. 8B shows a second codeword sequence corresponding to the parity bit part output from the codeword connection part 250.

  As shown in FIG. 8, the input sequence input to the first encoder 230 is an information sequence consisting of n bits and a termination sequence consisting of (M1 × b) bits.

  In LDPC-CC encoder 200 in the present embodiment, the termination sequence may be the same number of zero sequences as the number obtained by multiplying the memory length M1 of first encoder 230 by b. It is not necessary to solve the equation 5) and the termination sequence does not depend on the weight pattern when starting the termination process. Therefore, the LDPC-CC encoder 20 does not need to insert a padding sequence of K bits (K: 0 to M), which is required. As a result, when the LDPC-CC encoder 200 is used, the overhead at the time of information transmission generated by the termination process becomes (M1 × c) bits.

  As described above, LDPC-CC encoder 200 according to the present embodiment includes first encoder 230 that performs encoding based on information partial parity check matrix 110 and second encoder that performs encoding based on parity partial parity check matrix 120. 240 is concatenated and LDPC-CC encoding based on the parity check matrix 100 is performed.

  As described above, the second encoder 240 that performs encoding based on the parity partial check matrix 120 includes a differential encoder. For this reason, the value held in each shift register is output to the communication channel before that time, and the decoding side can uniquely determine the state of the shift register from the received codeword. The termination process of the encoder 240 is not necessary.

  Therefore, by configuring the LDPC-CC encoder 200 as described above, the termination processing of the LDPC-CC encoder 200 is the same as the number of shift registers of the first encoder 230 at the end of the information sequence, that is, This can be realized by concatenating and encoding the same number of 0 series as the number obtained by multiplying the memory length M1 of the 1 encoder 230 by b.

  As described above, the termination sequence generation unit 210 only needs to provide the same number of termination sequences as the number of shift registers, that is, the termination sequence of 0, which is the same as the number obtained by multiplying the memory length M1 of the first encoder 230 by b. Compared to the termination sequence generation circuit in the conventional LDPC-CC encoder, the termination sequence generation unit 210 can be configured on a much smaller scale.

  Further, in the configuration of the conventional LDPC-CC encoder, the termination processing of the encoder cannot be performed only by inputting the same number of 0 series as the number of shift registers of the LDPC-CC encoder to the encoder. On the other hand, in the present embodiment, termination processing can be performed only by inputting the same number of 0 series as the number of shift registers constituting the first encoder 230 to the LDPC-CC encoder 200. The overhead when the conventional LDPC-CC encoder 20 is used is (K + M + 1) × b / R = (K + M + 1) × c, whereas information transmission generated by termination processing of the LDPC-CC encoder 200 is performed. The overhead at the time is M1 × b / R = M1 × c bits, and M1 × c ≦ (K + M + 1) × c. Therefore, compared with the case where the conventional LDPC-CC encoder 20 is used, In the LDPC-CC encoder 200 in the embodiment, the overhead at the time of information transmission generated by the termination process can be reduced.

  In FIG. 4, the termination sequence concatenation unit 220 concatenates the termination sequence to the rear part of the information sequence and outputs the concatenated sequence to the first encoder 230 and the codeword concatenation unit 250. As shown in FIG. 9, the connected sequence may be output only to the first encoder 230, and the terminal sequence connection unit 220 </ b> A that outputs the information sequence may be used as the codeword connection unit 250.

  As described above, when the first encoder 230 is configured by a non-recursive convolutional encoder, the terminal sequence may be the same number of 0 sequences as the number of shift registers configuring the first encoder 230. On the decoding side, it is possible to know in advance what the termination sequence is, even if the encoding side does not transmit the termination sequence. Therefore, as shown in FIG. 9, even if the terminal sequence is not output from the terminal sequence connecting unit 220A to the codeword connecting unit 250, the decoding side can know in advance what the terminal sequence is, so that the terminal sequence is The overhead can be further reduced by the amount not transmitted.

  FIG. 10 shows an input sequence and an output sequence of LDPC-CC encoder 200. FIG. 10A shows an input sequence of the first encoder 230. FIG. 10B shows a second codeword sequence corresponding to the parity bit part output from the codeword concatenation part 250.

  As shown in FIG. 10, the input sequence input to the first encoder 230 is a termination sequence consisting of an information sequence consisting of n bits and (M1 × b) bits. However, since the termination sequence is all zero sequence and can be known on the decoding side, it does not have to be transmitted to the transmission line.

  Therefore, the overhead at the time of information transmission generated by the termination process of the LDPC-CC encoder 200 is M1 × (c−b) bits. Since R = b / c, M1 × (c−b) <M1 × c, and overhead can be further reduced by not transmitting the termination sequence to the transmission line.

  Further, since M1 × (c−b) ≦ (K + M + 1) × c, the termination processing of the LDPC-CC encoder 200 as described above causes overhead of (K + M + 1) / R bits. As compared with the LDPC-CC encoder 20, the transmission line utilization efficiency can be improved.

  4 employs a configuration in which a sequence in which a termination sequence is connected to the rear part of an information sequence is output to first encoder 230 and codeword connection unit 250, but is not limited thereto. Absent. For example, as shown in FIG. 11, an input sequence selection unit 260 may be used instead of the termination sequence connection unit 220.

  The input sequence selection unit 260 switches the sequence to be output to the first encoder 230 and the codeword concatenation unit 250 according to the termination processing control signal. The termination processing control signal is a signal for instructing the start of termination processing. When the termination processing control signal indicates before termination processing, the input sequence selection unit 260 converts the information sequence into the first encoder 230 and the codeword concatenation. Output to the unit 250. On the other hand, when the termination processing control signal indicates the start of termination processing, the input sequence selection unit 260 outputs the termination sequence to the first encoder 230 and the codeword concatenation unit 250.

  Similarly to the terminal sequence concatenation unit 220A, the input sequence selection unit 260 may be switched so as not to output the terminal sequence to the codeword concatenation unit 250 according to the termination processing control signal. Specifically, when the termination sequence control signal indicates that before termination processing is started, the input sequence selection unit 260 outputs the information sequence to the first encoder 230 and the codeword concatenation unit 250, and the termination processing control signal is When the start of the termination process is indicated, a switching operation for outputting the termination sequence to the first encoder 230 may be performed.

  In the above description, the case where LDPC-CC encoding is performed based on parity check matrix 100 in FIG. 1 has been described. can do.

  Hereinafter, an LDPC-CC encoder that performs LDPC-CC encoding based on the parity check matrix illustrated in FIG. 12 will be described as an example. FIG. 13 shows a partial parity check matrix obtained by extracting columns corresponding to parity bits from parity check matrix 100A in FIG. Note that the partial parity check matrix from which the column corresponding to the information bits is extracted is the same as the information partial parity check matrix 110, and thus description thereof is omitted. The 1/0 array in the column direction of the parity partial check matrix 120A of FIG. 13 is {1, 0, 1, 0, 0, 1}, which is, for example, a parity bit obtained at the time of p6. p6 indicates that it is obtained by mod2 addition of the input of the second encoder 240 at the time point p6 and the parity bits p1 and p3 obtained at the time points p1 and p3. That is, encoding based on the 1/0 sequence of each row of the parity partial check matrix 120A is performed by using a differential encoder having five delay units, a recursive convolutional encoder having five delay units, or five delay units. It can be realized with the accumulator.

  FIG. 14 shows a configuration of a second encoder that performs encoding using parity partial check matrix 120A of FIG. The second encoder 240A in FIG. 14 includes shift registers 241-1 to 241-5 and a mod2 adder 242, similarly to the second encoder 240 in FIG. 7, and includes the shift register 241-3. 7 is different from the second encoder 240 in FIG. 7 in that the output is output to the mod2 adder 242.

  Similarly to the second encoder 240 in FIG. 7, the second encoder 240A in FIG. 14 is configured by a differential encoder, so that the value held in each shift register is the communication path at the previous time point. Is output. Therefore, on the decoding side, the state of the shift register can be uniquely determined by using the received codeword. Therefore, the termination processing of the second encoder 240A is not necessary, and the termination processing of the LDPC-CC encoder 200 is performed. As described above, it is only necessary to perform termination processing on the first encoder 230.

  In the above description, the case where the parity partial check matrix is time-invariant has been described as an example, but it may be time-variant. FIG. 15 shows an example when the parity partial check matrix is time-varying. In the parity partial check matrix 120B of FIG. 15, the 1/0 arrangement pattern is different for each column.

  FIG. 16 shows a configuration of a second encoder that performs encoding using parity partial check matrix 120B of FIG. The second encoder 240B illustrated in FIG. 16 includes shift registers 241-1 to 241-5, a mod2 adder 242, weight multipliers 243-1 to 243-5, and a weight control unit 244.

  Weight control section 244 outputs a weight pattern to be given to weight multipliers 243-1 to 243-5 in accordance with the 1/0 arrangement in the row direction of parity partial check matrix 120B.

  The weight multipliers 243-1 to 243-5 multiply the output of the shift register by a weight according to the weight pattern output from the weight control unit 244.

  Similarly to the second encoder 240 in FIG. 7, the second encoder 240B in FIG. 16 is configured by a differential encoder, so that the value held in each shift register is the communication path at the previous time point. Is output. Therefore, on the decoding side, the state of the shift register can be uniquely determined by using the received codeword. Therefore, the termination process of the second encoder 240B is not necessary, and the termination process of the LDPC-CC encoder 200 is performed. As described above, it is only necessary to perform termination processing on the first encoder 230.

  In the above description, the case where the partial check matrix of the information bit part is time-varying has been described as an example, but it may be a time-invariant case. FIG. 17 shows a configuration example of the first encoder when the partial check matrix of the information bit part is time-invariant. The first encoder 230A of FIG. 17 includes shift registers 231-1 to 231-5 and a mod2 adder 234. As the termination processing of the first encoder 230A, the same number of 5 bits ((M1 × b) bits as the number of shift registers constituting the first encoder 230A, as in the case of the first encoder 230 that is time-varying. ) Zero sequence may be input as the termination sequence.

  The time-variant / time-invariant combination is not limited to the above-described combinations, and other combinations may be used. When the first encoder is configured by a non-recursive convolutional encoder, the termination process of the second encoder is not necessary even in other combinations, and the termination process of the LDPC-CC encoder 200 is as follows. Since it is sufficient to input the same number of zero sequences as the number of shift registers of one encoder, the effect of the present invention can be obtained.

  As described above, according to the present embodiment, the first codeword sequence is obtained by encoding the input sequence based on the information partial parity check matrix 110 obtained by extracting the column corresponding to the information bits of the parity check matrix 100. And a second codeword sequence by encoding the first codeword sequence based on the parity partial parity check matrix 120 obtained by extracting a column corresponding to the parity bit of the parity check matrix 100. A first encoder 230 that performs encoding based on the information partial check matrix 110, and a second encoder 240 that performs encoding based on the parity partial check matrix 120. LDPC-CC encoding is performed by concatenating and encoding.

  Since the encoding based on the parity partial check matrix 120 can be implemented using a differential encoder, the termination processing for the second encoder 240 is not necessary, and the termination sequence generation unit 210 is configured by the LDPC-CC encoder 200. Since it is only necessary to provide a termination sequence for the first encoder 230 as the termination sequence, the amount of overhead can be reduced.

  Further, when first encoder 230 is a non-recursive convolutional encoder, termination sequence generation unit 210 only needs to provide a zero sequence as the termination sequence, and therefore, termination sequence generation unit 210 is implemented with a very simple configuration. It is possible to suppress an increase in the circuit scale of the LDPC-CC encoder 200.

  Further, when the first encoder 230 is a non-recursive convolutional encoder, the termination sequence can be a zero sequence and can be known in advance on the decoding side, so by not transmitting the termination sequence to the transmission path, The overhead can be further reduced, and the utilization efficiency of the transmission path can be improved.

(Embodiment 2)
In the first embodiment, the case of using a non-recursive convolutional encoder as the first encoder has been described. However, in this embodiment, the configuration of an LDPC-CC encoder using a recursive convolutional encoder as the first encoder. The termination method will be described. In addition, the same code | symbol is attached | subjected to the part which is common in the component demonstrated in the above-mentioned Embodiment 1, and description is abbreviate | omitted.

  FIG. 18 shows an example of the LDPC-CC parity check matrix in the present embodiment. A parity check matrix 300 in FIG. 18 represents an LDPC-CC (or convolutional code) parity check matrix having a coding rate of ½ (= b / c) and a memory length of M = 2.

  18, each row of parity check matrix 300 corresponds to parity check equations c1, c2,..., And each column corresponds to each bit of a transmission codeword sequence. Here, the column with index usx (x = 1, 2,...) Corresponds to the bits of the information sequence, and the column with index upx is a feedback sequence obtained by recursive convolutional coding. , And a column with an index px (x = 1, 2,...) Corresponds to a parity bit obtained by encoding.

  FIG. 19 shows a partial parity check matrix (hereinafter also referred to as “information partial parity check matrix”) 310 from which columns corresponding to information bits of parity check matrix 300 are extracted. 19 includes a column corresponding to the feedback bit as a column corresponding to the information bit. FIG. 20 shows a partial parity check matrix (hereinafter also referred to as “parity partial parity check matrix”) 320 from which columns corresponding to parity bits of parity check matrix 300 are extracted.

  Similarly to the first embodiment, the LDPC-CC encoder in the present embodiment also extracts the check matrix 300, the information partial check matrix 310 obtained by extracting the columns corresponding to the information bits, and the columns corresponding to the parity bits. It is characterized by performing LDPC-CC encoding after decomposing into the parity partial check matrix 320.

  FIG. 21 shows an example of the configuration of the LDPC-CC encoder in the present embodiment. The LDPC-CC encoder 400 of FIG. 21 includes a first encoder 420 and a second encoder 430. FIG. 21 shows an input sequence selection unit 410 and a codeword connection unit 250.

  Input sequence selection section 410 selects a sequence to be output to first encoder 420 according to the termination processing control signal. The termination processing control signal is a signal for instructing the start of termination processing of the LDPC-CC encoder 400. When the termination processing control signal indicates before termination processing, the input sequence selection unit 410 sets the first information sequence as the first information sequence. The data is output to the encoder 420 and the codeword connection unit 250. On the other hand, when the termination processing control signal indicates the start of termination processing, the input sequence selection unit 410 outputs the sequence output from the first encoder 420 to the first encoder 420 and the codeword concatenation unit 250 as the termination sequence. To do.

(First encoder)
The first encoder 420 encodes the input sequence based on the information partial check matrix 310.

  FIG. 22 shows the internal configuration of the first encoder 420. The first encoder 420 shown in FIG. 22 includes shift registers 421-1 and 421-2 and mod2 adders 422-1 to 422-3, and is a recursive convolutional code having two shift registers (M1 = 2). It is a vessel.

  The mod2 adder 422-1 adds mod2 to the bit input to the first encoder 420 and the bit output from the mod2 adder 422-3.

  The mod2 adder 422-2 performs mod2 addition between the output of the mod2 adder 422-1 and the output of the shift register 421-2.

  The mod2 adder 422-3 performs mod2 addition between the output of the shift register 421-1 and the output of the shift register 421-2.

The first encoder 420 outputs the output of the mod2 adder 422-2 to the second encoder 430 as the codeword bits vc1 _{, t} of the first codeword sequence, and also outputs the mod2 adder 422-3. Is output to the input sequence selection unit 410.

(Second encoder)
Second encoder 430 performs encoding based on parity partial check matrix 320.

  FIG. 23 shows an internal configuration of second encoder 430. The second encoder 430 in FIG. 23 includes shift registers 431-1 and 431-2 and a mod2 adder 432, and is a differential encoder having two shift registers (M2 = 2) (“recursive”). Also referred to as a “convolutional encoder” or “accumulator”.

The mod2 adder 432 adds mod2 the codeword bits v _{c1, t1 of} the first codeword sequence output from the first encoder 420 and the output of the shift register 431-1 and outputs the result as the shift register 431. -2 and output to the codeword concatenation unit 250 as the second codeword sequence _{vc2, t} .

  Codeword concatenation unit 250 concatenates the information sequence or termination sequence and the second codeword sequence output from second encoder 430, and outputs the concatenated sequence as a transmission codeword sequence.

  Hereinafter, termination processing of the LDPC-CC encoder 400 configured as described above will be described.

(Termination)
Similar to the LDPC-CC encoder 200 described in Embodiment 1, the second encoder 430 of the LDPC-CC encoder 400 is also configured by a differential encoder. As described above, the value held in each shift register of the differential encoder is output to the communication path at an earlier time. Therefore, on the decoding side, the state of the shift register can be uniquely determined by using the received codeword. Therefore, the termination process of the second encoder 430 is unnecessary, and the termination process of the LDPC-CC encoder 400 is as follows. As in the first embodiment, it is only necessary to perform termination processing for the first encoder 420.

  Hereinafter, termination processing of the first encoder 420 will be described.

  As described above, the first encoder 420 outputs the mod2 addition result of the input of the first encoder 420 and the output of the mod2 adder 422-3 to the shift registers 421-1 and 421-2. Therefore, it is difficult to set the shift registers 421-1 and 421-2 to the zero state only by inputting the zero sequence to the first encoder 420, but the first encoder 420 is a recursive convolutional encoder. Therefore, the first encoder 420 can be terminated by using the output of the mod 2 adder 422-3 as the input of the first encoder 420.

  Therefore, the input sequence selection unit 410 outputs the information sequence to the first encoder 420 when the termination processing control signal indicates the start of termination processing, and the information sequence is encoded. When the start of termination processing is indicated, the output of the mod2 adder 422-3 of the first encoder 420 output from the first encoder 420 is output to the first encoder 420.

  As described above, when the first encoder 420 is a recursive convolutional encoder, the mod2 addition result of the mod2 adder 422-3 of the first encoder 420 may be provided to the first encoder 420 as a termination sequence. Therefore, it is not necessary to generate a terminal sequence separately. Therefore, it is not necessary to provide a termination processing generation unit, and an increase in circuit scale can be suppressed accordingly.

  The length of the termination sequence required for termination processing is also (M1 × c) bits, which can be shorter than the conventional LDPC-CC encoder that requires (K + M + 1) × c bits. Can reduce overhead.

  In the above description, the case where the first encoder 420 of the LDPC-CC encoder 400 is a time-invariant recursive convolutional encoder has been described as an example. However, the present invention is not limited to this, and the first encoder is It may be an odd recursive convolutional encoder.

  FIG. 24 shows a configuration example of the first encoder in the case of a time-varying recursive convolutional encoder. Since the first encoder 420A in FIG. 24 is a recursive convolutional encoder like the second encoder 420, the mod2 addition result of the mod2 adder 422-3 of the first encoder 420 is used as a termination sequence. What is necessary is just to provide to the 1st encoder 420A, and it is not necessary to produce | generate a termination | terminus series separately. Therefore, it is not necessary to provide a termination processing generation unit, and an increase in circuit scale can be suppressed accordingly.

  In the above description, the case where the second encoder 430 of the LDPC-CC encoder 400 adopts the configuration of a time-invariant differential encoder is described as an example. As described above, the encoder may perform encoding based on a time-varying parity partial check matrix in which the number of 1s in each row is two or more, or the 1/0 sequence is different for each row.

(Embodiment 3)
In this embodiment, a configuration and termination method of an LDPC-CC encoder that performs non-systematic LDPC-CC encoding in which an information sequence is not included in a transmission codeword sequence will be described.

  FIG. 25 shows an example of the LDPC-CC parity check matrix in the present embodiment. 25 is a parity check matrix of an unstructured convolutional code with a coding rate of 1/2.

  FIG. 26 shows a partial parity check matrix (hereinafter also referred to as “information partial parity check matrix”) 510 obtained by extracting columns corresponding to information bits of parity check matrix 500. FIG. 27 shows a partial parity check matrix (hereinafter, also referred to as “parity partial parity check matrix”) 520 from which columns corresponding to parity bits of parity check matrix 500 are extracted.

  Similarly to the first and second embodiments, the LDPC-CC encoder in the present embodiment also converts the check matrix 500 into the information partial check matrix 510 obtained by extracting the column corresponding to the information bits, and the parity bit. It is characterized in that LDPC-CC coding is performed after decomposing the corresponding column into a parity partial check matrix 520 extracted.

  FIG. 28 shows an example of the configuration of the LDPC-CC encoder in the present embodiment. The LDPC-CC encoder 600 of FIG. 28 includes a first encoder 610 and second encoders 620-1 and 620-2. FIG. 28 shows a terminal sequence generation unit 210, a terminal sequence connection unit 220, and a codeword connection unit 630. In addition, the same code | symbol is attached | subjected to the part which is common in the component demonstrated in the above-mentioned Embodiment 1, and description is abbreviate | omitted.

(First encoder)
First encoder 610 is a non-systematic convolutional encoder having 6 shift registers (M1 = 6) and a coding rate of 1/2, and extracts columns corresponding to information bits of parity check matrix 500 for the input sequence. Encoding is performed based on the information partial check matrix 510.

  FIG. 29 shows the internal configuration of the first encoder 610. The first encoder 610 in FIG. 29 includes shift registers 611-1 to 611-6 and mod2 adders 612-1 and 612-2.

  The mod2 adder 612-1 includes the bit input to the first encoder 610, the output of the shift register 611-2, the output of the shift register 611-3, the output of the shift register 611-5, and the shift register 611. The output of −6 is mod2 added, and the mod2 addition result is output to the second encoder 620-1 as the codeword bits of the first codeword sequence # 1.

  Further, the mod2 adder 612-2 includes the bit input to the first encoder 610, the output of the shift register 611-1, the output of the shift register 611-2, the output of the shift register 611-1, Mod2 is added to the output of the register 611-6, and the mod2 addition result is output to the second encoder 620-2 as the codeword bits of the first codeword sequence # 2.

(Second encoder)
FIG. 30 shows the configuration of the second encoders 620-1 and 620-2. The second encoders 620-1 and 620-2 adopt a configuration in which a shift register 241-6 is added to the second encoder 240 shown in FIG.

  Second encoder 620-1 receives first codeword sequence # 1 output from first encoder 610, and performs parity check on odd rows of parity partial parity check matrix 520 for first codeword sequence # 1. Is encoded, and the encoded sequence is output to the codeword concatenation unit 630 as the second codeword sequence # 1. Note that the codeword bits of the second codeword sequence # 1 include the codeword bits of the first codeword sequence # 1 at that time and the past second codeword sequence # 1 accumulated in the shift register 241-1. It is obtained by mod2 addition with the codeword bits.

  Second encoder 620-2 receives first codeword sequence # 2 output from first encoder 610, performs encoding based on a parity check polynomial of an even number row in parity partial check matrix 520, and performs encoding. Is output to the codeword concatenation unit 630 as the second codeword sequence # 2. Note that the codeword bits of the second codeword sequence # 2 are the codeword bits of the first codeword sequence # 2 at that time and the past second codeword sequence # 2 accumulated in the shift register 241-1. It is obtained by mod2 addition with the codeword bits.

  The codeword concatenation unit 630 concatenates the second codeword sequence # 1 output from the second encoder 620-1 and the second codeword sequence # 2 output from the second encoder 620-2, The sequence after concatenation is output as a transmission codeword sequence.

  Hereinafter, termination processing of LDPC-CC encoder 600 configured as described above will be described.

(Termination processing)
In LDPC-CC encoder 600, second encoders 620-1 and 620-2 adopt a differential encoder configuration, so that termination processing is performed as already described in the first and second embodiments. It becomes unnecessary. Therefore, as the termination process of LDPC-CC encoder 600, it is only necessary to perform the termination process on first encoder 610.

  Since the first encoder 610 is a non-recursive convolutional encoder having 6 shift registers (M1 = 6), in order to make all the states of the M1 shift registers zero, the zero sequence of M1 bits is terminated. If it inputs as a series, termination processing can be completed. M1 is the memory length of the first encoder.

  Therefore, the termination sequence generator 210 may provide the termination sequence concatenation unit 220 with the M1 bit zero sequence as a termination sequence when a termination processing control signal indicating the start of termination processing is input. In the case of coding rate R = b / c, as in the first embodiment, a zero sequence of M1 × b bits may be used as a termination sequence.

  End sequence concatenation unit 220 concatenates the end sequence after the information sequence and outputs the concatenated sequence to first encoder 610.

  FIG. 31 shows an input sequence and an output sequence of LDPC-CC encoder 600. FIG. 31A shows an input sequence of the first encoder 610, and FIG. 31B shows an output sequence of the second encoders 620-1 and 620-2.

  As shown in FIG. 31, the input sequence of the first encoder 610 is an information sequence consisting of n bits and a termination sequence consisting of (M1 × b) bits.

  In LDPC-CC encoder 600 in the present embodiment, the termination sequence may be the same number of zero sequences as the number obtained by multiplying memory length M1 of first encoder 610 by b. It is not necessary to solve the equation 5) and the termination sequence does not depend on the weight pattern when starting the termination process. Therefore, the LDPC-CC encoder 20 does not need to insert a padding sequence of K bits (K: 0 to M), which is required. As a result, when the LDPC-CC encoder 600 is used, the overhead at the time of information transmission generated by the termination process becomes (M1 × c) bits.

  As described above, LDPC-CC encoder 600 in the present embodiment includes first encoder 610 that performs encoding based on information partial parity check matrix 510 obtained by extracting a column corresponding to the information bits of parity check matrix 500, and a check. LDPC-CC coding based on parity check matrix 500 by concatenating second encoders 620-1 and 620-2 that perform coding based on parity partial parity check matrix 520 obtained by extracting columns corresponding to parity bits of matrix 500. To do.

  As described above, the second encoders 620-1 and 620-2 that perform encoding based on the parity partial check matrix 520 of the LPDC-CC check matrix 500 are configured by differential encoders. Therefore, the termination processing of the second encoders 620-1 and 620-2 is unnecessary as in the first and second embodiments.

  Therefore, by configuring the LDPC-CC encoder 600 as described above, the termination processing of the LDPC-CC encoder 600 is performed by the number M1 of shift registers of the first encoder 610 at the end of the information sequence, that is, the first This can be realized by concatenating and encoding 0 series of the same number as the memory length of the encoder 610.

  Since the termination sequence generator 210 only needs to provide a termination sequence consisting of 0, which is the same number as the number of shift registers M1, the termination sequence generator 210 in comparison with the termination sequence generation circuit in the conventional LDPC-CC encoder described above. Can be constructed on a much smaller scale.

  Further, in the configuration of the conventional LDPC-CC encoder, the termination processing of the encoder cannot be performed only by inputting the same number of 0 series as the number of shift registers of the LDPC-CC encoder to the encoder. On the other hand, in the present embodiment, the termination process can be performed simply by inputting the LDPC-CC encoder 600 with the same number of zero sequences as the number M1 of the shift registers constituting the first encoder 610. The overhead when the conventional LDPC-CC encoder 20 is used is (K + M + 1) × c, whereas the overhead at the time of information transmission generated by the termination processing of the LDPC-CC encoder 600 is (M1 × c) Since the bits are M1 × c ≦ (K + M + 1) × c, the LDPC-CC encoder 600 according to the present embodiment has a termination process as compared with the case where the conventional LDPC-CC encoder 20 is used. The overhead at the time of information transmission generated by can be reduced.

  In the above description, the case where the second encoders 620-1 and 620-2 perform coding based on the parity partial check matrix 520 is not limited to this. For example, as shown in FIG. Encoding may be performed based on the parity partial check matrix 520A.

  FIG. 33 shows an LDPC-CC encoder 600A in this case.

  The LDPC-CC encoder 600A includes a first encoder 610 and a second encoder 620A. Also, FIG. 33 shows a terminal sequence connection unit 220, a terminal sequence generation unit 210, and a codeword connection unit 630.

  FIG. 34 shows the configuration of the second encoder 620A.

  The second encoder 620A includes shift registers 621-1 to 621-6, 622-1 to 622-6, and mod2 adders 623-1 and 623-2.

  Second encoder 620A receives first codeword sequence # 1 and first codeword sequence # 2 output from first encoder 610, performs encoding based on the parity check matrix of parity partial parity check matrix 520A, and The encoded sequences are output to codeword concatenation unit 630 as second codeword sequence # 1 and second codeword sequence # 2. Note that the codeword bits of the second codeword sequence # 1 include the codeword bits of the first codeword sequence # 1 at that time and the past second codeword sequence # 2 accumulated in the shift register 622-1. It is obtained by mod2 addition with the codeword bits. Also, the codeword bits of the second codeword sequence # 2 are the codeword bits of the first codeword sequence # 2 at that time and the past second codeword sequence # 1 accumulated in the shift register 621-1. It is obtained by mod2 addition with the codeword bits.

  Similarly to the second encoder 620, the second encoder 620A in FIG. 34 adopts the configuration of a differential encoder, so that termination processing is not necessary as already described. Therefore, as the termination process of LDPC-CC encoder 600A, similar to LDPC-CC encoder 600, it is only necessary to perform the termination process of first encoder 610, and the same effect can be obtained.

(Embodiment 4)
In the present embodiment, a configuration and termination method of an LDPC-CC encoder that can reduce the amount of memory during decoding will be described. In the present embodiment, for the termination sequence, the first termination code sequence generated by encoding using the first encoder is used as the transmission codeword sequence without using the second encoder.

  FIG. 35 shows the configuration of the LDPC-CC encoder in the present embodiment. In the LDPC-CC encoder in the present embodiment in FIG. 35, the same reference numerals as those in FIG.

  The LDPC-CC encoder 700 of FIG. 35 includes a first encoder 230, a second encoder 240, and a codeword selection unit 720. FIG. 35 shows a terminal sequence generation unit 210, a terminal sequence connection unit 220, a codeword connection unit 250, and a switch 710.

  The switcher 710 receives the first codeword sequence output from the first encoder 230 and outputs the first codeword sequence to the second encoder 240 according to the termination processing control signal. The data is output to the selection unit 720 or the output destination of the first codeword sequence is switched. Specifically, when the termination processing control signal indicates before termination processing, that is, when the output of the first encoder 230 is a code word (first information code sequence) obtained by encoding an information sequence The switch 710 outputs the first information code sequence to the second encoder 240. On the other hand, when the termination sequence control signal indicates the start of termination processing, that is, when the output of the first encoder 230 is a code word (first termination code sequence) obtained by encoding the termination sequence, the switcher 710 outputs the first terminal code sequence to the codeword selection unit 720.

  The code word selection unit 720 selects a sequence to be output to the code word concatenation unit 250 according to the termination processing control signal. Specifically, when the termination processing control signal indicates before the termination processing, the codeword selection unit 720 selects the second codeword sequence output from the second encoder 240 and supplies the codeword connection unit 250 with the second codeword sequence. Output. On the other hand, when the termination processing control signal indicates the start of termination processing, the codeword selection unit 720 selects the first termination code sequence output from the switch 710 and outputs the first termination code sequence to the codeword connection unit 250.

  As described above, in the present embodiment, the first termination code sequence generated as a result of the termination process of the first encoder 230 is not encoded by the second encoder 240 and is output as it is as a transmission codeword sequence. Is done.

  Hereinafter, termination processing of LDPC-CC encoder 700 configured as described above will be described. Hereinafter, the first encoder 230 performs encoding based on the information partial check matrix 110 illustrated in FIG. 2, and the second encoder 240 performs encoding based on the information partial check matrix 110 illustrated in FIG. A case will be described as an example.

(Termination processing)
The first encoder 230 encodes the information sequence or the terminal sequence using the information partial check matrix 110 to generate a first codeword sequence. The first codeword sequence is output to switch 710.

  In the switcher 710, the output destination of the first codeword sequence is switched to either the second encoder 240 or the codeword selector 720 in accordance with the termination processing control signal. Specifically, when the termination processing control signal indicates before termination processing, that is, when the output of the first encoder 230 is the first information code sequence, the first information code sequence is sent to the second encoder 240. Is output.

  On the other hand, when the termination sequence control signal indicates the start of termination processing, that is, when the output of the first encoder 230 is the first termination code sequence, the first termination code sequence is output to the codeword selection unit 720. .

  Thus, during the termination process, the first termination code sequence is not output to the second encoder 240 but is output to the codeword concatenation unit 250 via the codeword selection unit 720. Therefore, during the termination process, the first termination code sequence is output from the codeword concatenation unit 250 as the transmission codeword sequence.

  FIG. 36 shows a parity check matrix in the case where the first termination code sequence generated by using only the first encoder 230 without using the second encoder 240 at the time of termination processing is a transmission codeword sequence. The terminal part of is shown. In FIG. 36, the bits corresponding to the portion surrounded by the square frame indicate the bits to be added when the first code termination sequence is output to the second encoder 240. When the first terminal code sequence is output to the second encoder 240, 1 is set in the portion surrounded by the square frame, and the corresponding bit is added. For example, in the parity check equation of c7, (u3 + u6 + u7) is output to the second encoder 240 as the first terminal code sequence, and the second encoder 240 adds the past p2 to (u3 + u6 + u7), whereby p7 Is calculated.

  On the other hand, when the first terminal code sequence is not output to the second encoder 240 but is output to the codeword selection unit 720, the past p2 added by the second encoder 240 is (u3 + u6 + u7). P7 is calculated without being added.

  Therefore, as shown in FIG. 36, when the first termination code sequence is not output to the second encoder 240 during the termination process and the first termination code sequence is transmitted as a transmission codeword sequence, a square frame is used. Coding is performed using a parity check expression in which the enclosed portion is replaced with 0.

  As a result, the column weight of the column corresponding to the parity bit portion of the parity check matrix after p2 becomes 1, and the zero sequence connected on the decoding side required when decoding these bits can be shortened. For example, in the example shown in FIG. 36, focusing on u4, u8 included in the parity check expression c8 including u4 is also included in the parity check expression c9. U9 included in the parity check expression c9 is also included in the parity check expression c13. Therefore, on the decoding side, in order to decode u4, it is necessary to connect a zero sequence further to the subsequent stage of the termination sequence by the number of bits necessary for the parity check equation c13. In the example shown in FIG. 36, the zero series is connected by 4 bits.

  On the other hand, FIG. 37 shows a termination part of the parity check matrix when the first termination code sequence is output to second encoder 240. In this case, the second codeword sequence obtained by encoding the first terminal code sequence is output to the codeword concatenation unit 250 via the codeword selection unit 720 and transmitted from the codeword concatenation unit 250. Sent as a series.

  As shown in FIG. 37, in the parity check equation c7, the second encoder 240 outputs the first terminal code sequence from the first encoder 230 (u3, u6, u7), whereas the past p2 is By adding, p7 is calculated. The same applies to other parity check equations. Therefore, in FIG. 37, 1 stands in a portion surrounded by a square frame.

  In the example shown in FIG. 37, when paying attention to p6, p11 included in the parity check expression c11 including p6 is also included in the other parity check expression c16. Therefore, a zero sequence of the number of bits necessary for the parity check expression c16 is obtained. Need to connect. In the example shown in FIG. 37, 10 bits of the zero series are connected.

  On the other hand, in the present embodiment, at the time of termination processing, the first termination code sequence is not encoded by the second encoder 240, so that the zeros that need to be connected as shown in FIG. The number of bits in the sequence can be reduced. For example, it can be seen that the number of bits of the zero series that need to be connected by the decoder is shortened by 6 bits compared to the end of the parity check matrix 100 shown in Embodiment 1 shown in FIG. As a result, the memory size required for the decoder and the amount of decoding calculation can be reduced.

  Although the first end code sequence is not encoded by the second encoder 240, the column weight of the corresponding column becomes 1, and the error correction capability deteriorates, but the second encoder 240 does not encode. Since the sequence is a terminal sequence, and the LDPC-CC decoding algorithm propagates reliability in order from the codeword positioned to the left of the parity check matrix, the error of the terminal sequence positioned in the rightmost column of the parity check matrix Therefore, since the influence on the decoding of the codeword bits related to the information bits located on the left side is small, it is expected that the error correction capability is hardly deteriorated. Therefore, it is effective to apply the LDPC-CC encoder 700 in the present embodiment when there are severe restrictions on the memory size of the decoder, the decoding calculation amount, and the like.

  As described above, according to the present embodiment, switch 710 converts the first codeword sequence output from first encoder 230 into the second code according to whether the input sequence is an information sequence or a termination sequence. The codeword selection unit 720 selects either the first codeword sequence or the second codeword sequence as a codeword depending on whether the input sequence is an information sequence or a termination sequence. Output as a series. In this way, the column weight of the check matrix is reduced, and the number of 0-sequence bits that need to be connected at the time of termination processing on the decoding side can be reduced. Therefore, the memory size of the decoder and the amount of code computation Can be reduced.

(Embodiment 5)
In the first to fourth embodiments, the LDPC-CC encoder and the encoding method that can reduce the amount of the termination sequence transmitted to the transmission path have been described. In the present embodiment, focusing on the input sequence and output sequence of the LDPC-CC encoder, the relationship with the parity check matrix will be explained, and decoding for decoding the transmission codeword sequence transmitted from the LDPC-CC encoder The decoder and decoding method will be described mainly focusing on termination sequence processing.

(Encoding method)
FIG. 38 shows an input sequence and an output sequence of the LDPC-CC encoder in the present embodiment. The LDPC-CC encoder 800 in FIG. 38 is an encoder that performs LDPC-CC encoding with a coding rate R = b / c and a memory length M based on a low-density parity check matrix.

  LDPC-CC encoder 800 includes an information sequence composed of information bits, followed by a termination sequence for termination processing of LDPC-CC encoder 800 (hereinafter collectively referred to as a “transmission information sequence”). Is an input sequence, and the input sequence is encoded.

  LDPC-CC encoder 800 outputs an information code sequence when the input sequence is an information sequence. Also, LDPC-CC encoder 800 outputs a termination code sequence when the input sequence is a termination sequence. Hereinafter, the information code sequence and the terminal code sequence are collectively referred to as “transmission codeword sequence”.

  Hereinafter, a termination sequence when LDPC-CC encoder 800 performs LDPC-CC encoding using the parity check matrix illustrated in FIG. 1 will be described. Parity check matrix 100 in FIG. 1 is a parity check matrix that defines an LDPC-CC with coding rate R = 1/2 and memory length M = 5.

  Among the labels attached to each column of parity check matrix 100 shown in FIG. 1, u1, u2,... Correspond to each bit of the transmission information sequence input to LDPC-CC encoder 800, and p1, p2, ... correspond to each bit of the transmission codeword sequence output from the LDPC-CC encoder 800. The partial matrix from which the columns corresponding to u1, u2,... are extracted is the information partial check matrix 110 in FIG. Moreover, the partial matrix which extracted the column corresponding to p1, p2, ... is the parity partial check matrix 120 of FIG.

  By the way, in each row of the information partial check matrix, the maximum value of the difference between the index of the column having 1 at the left and the index of the column having 1 at the right corresponds to (M1 × b). The information partial parity check matrix 110 in FIG. 2 is an example of b = 1 and M1 = 4, which matches the maximum value 4 of the index difference.

  Further, in each row of the parity partial check matrix, the maximum value of the difference between the index of the column having 1 on the left and the index of the column having 1 on the right corresponds to M2 (c−b). . The parity partial check matrix 120 of FIG. 3 is an example of b = 1, c = 2, and M2 = 5, and matches the maximum value 5 of the index difference.

  The length of the termination sequence for LDPC-CC encoder 800 may be M1 × b = 4 × 1 = 4 as described in the above embodiment. Further, the memory length M of the LDPC-CC encoder 800 is the larger of M1 and M2 (M = max (M1, M2)). That is, the length of the termination sequence is equal to or less than the number obtained by multiplying the memory length M by b. Encoding is performed as follows.

  First, coding when an information sequence is input to the LDPC-CC encoder 800 will be described using a parity check equation labeled c6 in the parity check matrix 100 as an example. The parity check expression of c6 represents a method for generating bit p6 of a transmission codeword sequence that is output when bit u6 is input to LDPC-CC encoder 800 as a transmission information sequence.

  Specifically, the transmission codeword bit p6 is obtained by adding mod2 to a bit corresponding to a standing column other than p6 in the row c6. That is, p6 is calculated by p6 = p1 + u5 + u6.

  Further, since the pattern of arrangement of 1 and 0 in each row is different for each row, the check matrix 100 is calculated by p7 = p2 + u3 + u7 in the case of p7.

  Next, encoding when an M1 × b (= 4) bit termination sequence is input to LDPC-CC encoder 800 will be described.

  The terminal sequence is expressed as t = [t1, t2, t3, t4]. An information sequence input immediately before the termination sequence is represented as d = [..., d5, d4, d3, d2, d1]. The transmission information sequence at this time is u = [..., D5, d4, d3, d2, d1, t1, t2, t3, t4].

  The transmission codeword sequence is assumed to be v = [..., g5, g4, g3, g2, g1, s1, s2, s3, s4]. Here, the information code sequences g5 to g1 are transmission codeword sequences corresponding to the information sequences d5 to d1, and the termination code sequences s1 to s4 are transmission codeword sequences corresponding to the termination sequences t1 to t4.

FIG. 39 shows the end part of parity check matrix 100. From the rows of the parity check equations ct1 to ct4, the terminal code sequences s1 to s4 are calculated by equations (6-1) to (6-4).

  That is, the terminal code sequences s1 to s4 are generated using the terminal sequences t1 to t4, the last 4 bits d1 to d4 of the information sequence, and the last 5 bits g1 to g5 of the information code sequence.

  Since LDPC-CC encoder 800 is a convolutional encoder, it can take a sequence of an arbitrary length as an information sequence. Also, the LDPC-CC encoder 800 can be composed of a time-varying convolutional encoder. For this reason, the bits used to generate the termination code sequence vary depending on the length of the information sequence and the value of the information sequence.

  However, as described above, the maximum difference between the index of the leftmost 1 position and the rightmost 1 position of each row of the information partial parity check matrix and the parity partial parity check matrix is (M1 × b), respectively. Since it corresponds to M2 × (c−b), the bits of the terminal code sequence can be expressed as follows.

  That is, the terminal code sequence includes a terminal sequence composed of (M1 × b) bits, a maximum of (M1 × b) bits after the information sequence, and a maximum of M2 × (c−b) bits after the information code sequence. And will be generated.

(Decryption method)
Next, a decoding method of the LDPC-CC decoder that decodes the transmission codeword sequence output from LDPC-CC encoder 800 will be described.

  FIG. 40 shows an input sequence and an output sequence of the LDPC-CC decoder in the present embodiment. The LDPC-CC decoder 900 of FIG. 40 is a decoder that performs LDPC-CC decoding with a coding rate R = b / c and a memory length M based on a low-density parity check matrix.

  LDPC-CC decoder 900 receives the estimated value of the received sequence (information sequence, termination sequence, information code sequence, termination code sequence) obtained from the communication path and performs decoding processing. As a decoding processing method, a sum-product algorithm based on a parity check matrix can be applied as in LDPC-BC. LDPC-CC decoder 900 outputs an estimated information sequence after decoding. A sequence composed of the estimated value of the information sequence and the estimated value of the termination sequence is called a received information sequence, and a sequence composed of the estimated value of the information code sequence and the estimated value of the termination code sequence is called a received codeword sequence.

  FIG. 41 shows an example of a termination part of a parity check matrix used by LDPC-CC decoder 900 for decoding processing. 41 is a termination corresponding to parity check matrix 100 used in LDPC-CC encoder 800 on the encoding side.

  When termination processing is performed on the encoding side, the state of the LDPC-CC encoder 800 after completion of termination processing becomes all zeros. Therefore, on the decoding side, after the termination sequence and the termination code sequence, the memory length M is zero. The sequences x and y are added and decoded.

  Further, in the present embodiment, LDPC-CC decoder 900 has a right side of a column corresponding to the M2 × (c−b) th bit from the last bit of the received codeword sequence, as shown in FIG. A parity check matrix in which one column is inserted is used.

  The inserted column has 1 in the same row as the lowest 1 in the bit corresponding column of the received codeword sequence (the column on the left side of the inserted column), and the other rows are all 0 columns. . In the example shown in FIG. 41, 5 (= M2 × (c−b)) columns g1 ′, s1 ′, s2 ′, s3 ′, and s4 ′ are inserted at the end of the parity check matrix.

Since the columns are inserted, the parity check equations c6 to c10 of the parity check matrix of FIG. 41 are as shown in equations (7-1) to (7-5).

  In the present embodiment, LDPC-CC decoder 800 performs decoding using the same value as the channel value of the bit string of the left received codeword sequence as the channel value of the inserted column. In the example shown in FIG. 41, the same values as g1, s1, s2, s3, and s4 are used as the channel values of the columns g1 ', s1', s2 ', s3', and s4 ', respectively.

This is the LDPC-CC, as shown in Equation (2), to obtain the codeword v _{2, t,} this would require codeword v _{2, t-i} at a past time, LDPC-CC code This is because the code word v _{2, t-i} of the past time is held in the shift register of the device 800. At the time of termination processing, the LDPC-CC decoder 900 needs the state of the shift register of the LDPC-CC encoder 800, but what is held in the shift register is a codeword of a past time, The time codeword has already been transmitted. Therefore, on the decoding side, a shift is performed by decoding using a parity check matrix in which columns g1 ′, s1 ′, s2 ′, s3 ′, and s4 ′ are inserted to the right of g1, s1, s2, s3, and s4. Termination processing is performed using the codeword held in the register. Therefore, on the encoding side, it is not necessary to transmit the code word at the past time held in the shift register necessary for _{obtaining the} code word v _{2, t,} and the terminal sequence of (M1 × b) bits is used. Just get better.

When termination processing is completed, since x1 to x5 and y1 to y5 are 0, and g1 = g1 ′, sx = sx ′ (x = 1,..., 4), the equation (8− 1) to (8-5) are obtained.

Therefore, from the equations (8-1) to (8-5), the terminal sequence t = [t1, t2, t3, t4] should be a sequence satisfying the relationships of the equations (9-1) to (9-2). For example, t = [0, 0, 0, 0] can be used as the termination sequence.

  As described above, the LDPC-CC encoder in this embodiment is configured to output the information code sequence and the termination code sequence with the termination sequence including (M1 × b) bits following the information sequence as an input.

  Also, the LDPC-CC decoder according to the present embodiment adds the check matrix used for encoding to the back of each received codeword sequence (sequence consisting of an estimated value of an information code sequence and an estimated value of a terminal code sequence). Decoding processing is performed using a parity check matrix to which M2 × (c−b) columns having the same channel value as M2 × (c−b) bits are added.

  In this way, termination processing of the LDPC-CC encoder can be performed using (M1 × b) zero termination sequences, and termination sequences are generated using information code sequences and termination code sequences. Thus, an LDPC-CC encoder can be realized with a simple configuration.

  In the above description, the case where the LDPC-CC encoder 800 performs coding using the parity check matrix 100 of a non-recursive convolutional code has been described as an example, but not limited to the parity check matrix 100, for example, FIG. The same can be applied to the case where encoding is performed using a recursive convolutional code check matrix 300 as shown in FIG. However, the terminal sequence in this case is not a zero sequence, but is a feedback bit of (M1 × b) bits as described in the second embodiment.

  Further, when the termination sequence and decoding method described in the present embodiment are used, the same effect can be obtained for the conventional LDPC-CC encoder 10 as shown in FIG.

(Other embodiment 1)
In the present embodiment, a method for designing a new LDPC-CC from the (7, 5) convolutional code will be described in detail.

  FIG. 42 is a diagram illustrating the configuration of the encoder of the (7, 5) convolutional code. The encoder illustrated in FIG. 42 includes shift registers 4201 and 4202 and exclusive OR circuits 4203, 4204, and 4205. The encoder shown in FIG. 42 outputs an output x and a parity p for an input x. This code is a systematic code.

  In the present invention, it is important to use a convolutional code that is a systematic code.

Consider a convolutional code of coding rate 1/2 and generator polynomial G = [1 G ₁ (D) / G ₀ (D)] as an example. In this case, _{G 1} is feed-forward polynomial, _{G 0} represents a feedback polynomial. When the polynomial expression of the information sequence (data) is X (D) and the polynomial expression of the parity sequence is P (D), the parity check polynomial is expressed as the following equation (10).

FIG. 43 describes information related to the (7, 5) convolutional code. The generation matrix of the (7, 5) convolutional code is expressed as G = [1 (D ² +1) / (D ² + D + 1)]. Accordingly, the parity check polynomial is expressed by the following equation (11).

Here, the data at the time point i is represented as X _i , the parity is represented as P _i, and the transmission sequence W _i = (X _i , P _i ). The transmission vector w = (X ₁ , P ₁ , X ₂ , P ₂ ,..., X _i , P _i ...). Then, from Equation (11), the check matrix H can be expressed as shown in FIG. At this time, the following relational expression (12) is established.

  Therefore, the receiving apparatus uses the check matrix H, BP (Belief Propagation) decoding as shown in Non-Patent Document 4 to Non-Patent Document 6, min-sum decoding approximating BP decoding, offset BP decoding, Normalized Decoding can be performed by using BP decoding, shuffled BP decoding, or the like.

  Here, in the parity check matrix of FIG. 43, the lower left portion (the lower left portion of 4301 in FIG. 43) from the row number = column number “1” is defined as an approximate lower triangular matrix. The upper right part of row number = column number “1” is defined as an upper trapezoid matrix.

  Next, the LDPC-CC design method in the present invention will be described in detail.

  In this embodiment, in order to realize the encoder with a simple configuration, a method of adding “1” to the approximate lower triangular matrix of the parity check matrix H for the (7, 5) convolutional code shown in FIG. Take.

<Encoding method>
Here, as an example, it is assumed that “1” to be added to the parity check matrix of FIG. 43 is one for each of data and parity. When “1” is added to the approximate lower triangular matrix of the parity check matrix H in FIG. 43 for each of data and parity, the parity check polynomial is expressed as in the following equation (13). However, in formula (13), α ≧ 3 and β ≧ 3.

Therefore, the parity P (D) is expressed as the following equation (14).

When “1” is added to the approximate lower triangular matrix of the parity check matrix, D ^β P (D), D ² P (D), and DP (D) are past data and are known values. Parity P (D) can be obtained.

<Location to add “1”>
Next, the position of “1” to be added will be described in detail with reference to FIG. In FIG. 44, reference numeral 4401 is “1” related to the decoding of the data X _{i at} the time point i, and reference numeral 4402 is “1” related to the parity P _i at the time point i. A dotted line 4403 is a protograph related to the propagation of external information for the data X _i and the parity P _i at the time point i when one BP decoding is performed. That is, the reliability from time point i-2 to time point i + 2 is involved in propagation.

A boundary line 4405 is drawn on the vertical axis for “1” (4404) on the rightmost side of the protograph 4403. Then, the boundary line 4407 is drawn with respect to the leftmost “1” (4406) adjacent to the boundary line 4405 (the leftmost “1” among the lines is the line adjacent to the boundary line 4405). Then, “1” is added to the region 4408 so that the reliability after the boundary line 4405 is propagated to the data X _i and the parity P _i at the time point i. Accordingly, it is possible to propagate a probability that was not obtained before adding “1”, that is, a reliability other than the time point i−2 to the time point i + 2. In order to propagate a new probability, it is necessary to add to the area 4408 in FIG. In other words, the reliability of “1” on the right side of the boundary line 4405 and below the boundary line 4407 is determined for the data X _i and the parity P _i at the time point i through “1” added to the area 4408. Will be propagated.

  Here, in each row of parity check matrix H in FIG. 44, the width of the rightmost “1” and the leftmost “1” is L. So far, the position where “1” is added has been described in the column direction. Considering this in the row direction, in the parity check matrix of FIG. 43, “1” is added to the left position of “L-2” or more from the leftmost “1”. Further, in the case of explanation using a check polynomial, in equation (13), α may be set to 5 or more and β may be set to 5 or more.

This is expressed by a general formula. A general expression of the parity check polynomial of the convolutional code is expressed as the following expression (15).

When “1” is added to the approximate lower triangular matrix of the parity check matrix H, one for each of data and parity, the parity check polynomial is expressed as the following equation (16).

  In this case, α may be set to 2K + 1 or more, and β may be set to 2K + 1 or more. K ≧ 2.

FIG. 45 is a diagram illustrating an example when “1” is added to the approximate lower triangular matrix of the parity check matrix in FIG. 44. Then, when “1” is added to the data and parity at all times, the parity check matrix is represented as shown in FIG. FIG. 46 is a diagram illustrating an example of a configuration of an LDPC-CC parity check matrix according to the present embodiment. In FIG. 46, “1” in regions 4601 and 4602 is the added “1”, and the code having the check matrix H is the LDPC-CC in the present embodiment. At this time, the check polynomial is expressed by the following equation (17).

  As described above, the transmission apparatus adds “1” to the approximate lower triangular matrix of the parity check matrix H and creates an LDPC-CC from the convolutional code, so that the reception apparatus uses the created LDPC-CC parity check matrix. By using BP decoding or approximated BP decoding, good reception quality can be obtained.

In this embodiment, the case where one “1” is added to each of data and parity has been described. However, the present invention is not limited to this, and for example, “1” is set to either data or parity. The method of adding may be used. For example, “1” may be added to data and “1” may not be added to parity. As an example, let us consider a case where there is no ^Dβ in the above equation (16). At this time, if α is set to 2K + 1 or more, the receiving apparatus can obtain good reception quality. Conversely, let us consider a case where there is no ^Dα in equation (16). At this time, if β is set to 2K + 1 or more, the receiving apparatus can obtain good reception quality.

Also, the reception quality is greatly improved by a code in which a plurality of “1” s are added to both data and parity. For example, as an example of inserting a plurality, a parity check polynomial of a certain convolutional code is expressed by equation (18). In Equation (18), K ≧ 2.

When a plurality of “1” s are added to the approximate lower triangular matrix of the parity check matrix H for the data and parity, the parity check polynomial is represented by the following equation (19).

In this case, when α ₁ ,..., Α _{n is set} to 2K + 1 or more and β ₁ ,..., Β _m are set to 2K + 1 or more, good reception quality can be obtained in the receiving apparatus. This point is important in the present embodiment.

However, even when one or more of α ₁ ,..., Α _n satisfy 2K + 1 or more, good reception quality can be obtained in the receiving apparatus. Further, even when one or more of β ₁ ,..., Β _m satisfy 2K + 1 or more, good reception quality can be obtained in the receiving apparatus.

Further, when the LDPC-CC parity check polynomial is expressed by the following equation (20), when α ₁ ,..., Α _n are set to 2K + 1 or more, good reception quality is obtained in the receiving apparatus. be able to. This point is important in the present embodiment.

However, even when one or more of α ₁ ,..., Α _n satisfy 2K + 1 or more, good reception quality can be obtained in the receiving apparatus.

Similarly, when the LDPC-CC parity check polynomial is expressed by the following equation (21), if β ₁ ,..., Β _m are set to 2K + 1 or more, good reception quality can be obtained in the receiver. Can be obtained. This point is important in the present embodiment.

However, even when one or more of β ₁ ,..., Β _m satisfy 2K + 1 or more, good reception quality can be obtained in the receiving apparatus.

  Next, a method for designing an LDPC-CC using a parity check polynomial different from Equation (11) of the (7, 5) convolutional code will be described in detail. Here, as an example, a case where two “1” s are added to data and two “1” s are added to parity will be described as an example.

Non-Patent Document 7 shows a parity check polynomial different from Equation (11) of the (7, 5) convolutional code. An example of this is expressed by the following equation (22).

  In this case, the check matrix H can be represented as shown in FIG.

<Encoding method>
Here, a case where two “1” s are added to each of the data and the parity for the parity check matrix of FIG. 47 will be described. When two “1” s are added to each of the data and parity in the approximate lower triangular matrix of the parity check matrix H in FIG. 47, the parity check polynomial is represented by the following equation (23).

Therefore, the parity P (D) can be expressed as the following equation (24).

Thus, when “1” is added to the approximate lower triangular matrix of the parity check matrix, D ^β1 P (D), D ^β2 P (D), D ⁹ P (D), D ⁸ P (D), D ³ Since P (D) and DP (D) are past data and are known values, the parity P (D) can be easily obtained.

<Location to add “1”>
In order to obtain the same effect as described above, when α ₁ and α ₂ are set to 19 or more and β ₁ and β ₂ are set to 19 or more, good reception quality can be obtained in the receiving apparatus. As an example, in the parity check matrix of FIG. 48, α ₁ = 26, α ₂ = 19, β ₁ = 30, and β ₂ = 24. Thereby, for the same reason as described above, the reception apparatus can obtain good reception quality.

  From the above example, a method for creating an LDPC-CC from a convolutional code is as follows. The following procedure is an example when the convolutional code is an encoding rate of 1/2.

  <1> Select a convolutional code that gives good characteristics.

  <2> A check polynomial for the selected convolutional code is generated (for example, Equation (15)). However, it is important to use the selected convolutional code as a systematic code. Further, the check polynomial is not limited to one as described above. It is necessary to select a check polynomial that gives good reception quality. At this time, it is better to use an equivalent check polynomial having a higher degree than the check polynomial generated from the generator polynomial (see Non-Patent Document 7).

  <3> A check matrix H of the selected convolutional code is created.

  <4> Probability propagation is considered for data or (and) parity, and “1” is added to the parity check matrix. The position where “1” is added is as described above.

  In the present embodiment, the method of creating the LDPC-CC from the (7, 5) convolutional code has been described. However, the present invention is not limited to the (7, 5) convolutional code, and other convolutional codes are used. Can be similarly implemented. At this time, the generating polynomial G of the convolutional code that gives good reception quality is described in detail in Non-Patent Document 8.

As described above, in the transmission apparatus, α ₁ ,..., Α _n are set to 2K + 1 or more, β ₁ ,..., Β _m are set to 2K + 1 or more in Equation (19), and the LDPC-CC is calculated from the convolutional code. Thus, the reception apparatus can obtain good reception quality by performing BP decoding or approximated BP decoding using the created LDPC-CC parity check matrix. Further, when the LDPC-CC is created from the convolutional code, the size of the protograph, that is, the check polynomial, is much smaller than the protographs shown in Non-Patent Document 9 and Non-Patent Document 10, so that the transmission data Therefore, it is possible to reduce the number of extra bits generated when a packet having a small number of bits is transmitted, and to suppress the problem that the data transmission efficiency is lowered.

  The above description is associated with the configuration of the LDPC-CC encoder and the LDPC-CC parity check matrix described in the first to fifth embodiments.

Let α be the maximum order involved in the data X (D) of the original convolutional code. In this case, consider an LDPC-CC in which “1” is added to the approximate lower triangular matrix of the parity check matrix H to the parity P (D), and a term of D ^β is added to the parity P (D) of the parity check polynomial. . Here, β is the maximum order involved in the parity P (D) of the LDPC-CC created according to the above description. At this time, as described in the present embodiment, by setting β to 2α + 1 or more, good reception quality can be obtained.

  Data X (D) is generated by the first encoder. That is, if the memory length of the first encoder is M1, α corresponds to M1 because α is the maximum order involved in the data X (D).

  The parity P (D) is generated by the second encoder. That is, assuming that the memory length of the second encoder is M2, the maximum order β of the parity P (D) corresponds to M2.

At this time, Expression (25) is obtained from the relational expression β ≧ 2α + 1 for obtaining good reception performance, α = M1, and β = M2.

  That is, by adopting a configuration in which the memory length M1 of the first encoder and the memory length M2 of the second encoder satisfy Equation (25), the termination sequence length described in the first to fifth embodiments is used. In addition to the effect of shortening the length of the termination code sequence associated therewith, it is possible to obtain an effect of obtaining good reception performance.

  In other words, if the memory length M2 of the second encoder is at least twice the memory length M1 of the first encoder, the termination sequence length can be shortened and good reception performance can be obtained.

  Note that (M1 × b) is an index of a column in which 1 is present on the left and a column in which 1 is present on the right in each row of the information submatrix extracted from the column corresponding to the information bit of the parity check matrix. Is the maximum difference from the index. M2 × (c−b) is an index of a column having 1 on the left and 1 on the right in each row of the parity submatrix extracted from the column corresponding to the information bit of the check matrix. This is the maximum difference from the index of the column to be executed. Therefore, when the coding rate R = b / c, an LDPC-CC codeword sequence is generated using an information sub-matrix and a parity sub-matrix such that M2 is twice or more of M1. The termination sequence can be shortened and good reception performance can be obtained.

(Other embodiment 2)
Hereinafter, an example of LDPC-CC suitable for the configuration of the first to fifth embodiments will be described in detail below.

  In this embodiment, a configuration of a time-varying LDPC-CC that can easily perform puncturing and that has a simple encoder configuration will be described. In particular, in this embodiment, an LDPC-CC capable of periodically puncturing data will be described. In the LDPC code, a puncturing method for periodically puncturing data has not been sufficiently studied so far, and a method for performing puncturing in particular has not been sufficiently discussed. In LDPC-CC in the present embodiment, if data can be punctured periodically and regularly instead of being randomly punctured, degradation of reception quality can be suppressed. In the following, a configuration method of time-varying LDPC-CC capable of realizing the coding rate R = 1/2 will be described.

When the coding rate is 1/2 and the polynomial expression of the information sequence (data) is X (D) and the polynomial expression of the parity sequence is P (D), the parity check polynomial is expressed as follows.

In the formula (26), a1, a2,..., An are integers of 1 or more (where a1 ≠ a2 ≠ ... ≠ an). Further, b1, b2,... Bm are integers of 1 or more (where b1 ≠ b2 ≠ ... ≠ bm). Here, in order to enable easy encoding, it is assumed that the terms D ⁰ X (D) and D ⁰ P (D) (D ⁰ = 1) exist. Therefore, P (D) is expressed as follows.

As can be seen from the equation (27), since D ⁰ = 1 exists and past parity terms, that is, b1, b2,... Bm are integers of 1 or more, the parity P is sequentially changed. Can be sought.

Next, a parity check polynomial with a coding rate of 1/2 different from Equation (26) is expressed as follows.

In the formula (28), A1, A2,..., AN are integers of 1 or more (where A1 ≠ A2 ≠... AN). Further, B1, B2,..., BM are integers of 1 or more (where B1 ≠ B2 ≠ ... ≠ BM). Here, it is assumed that the terms D ⁰ X (D) and D ⁰ P (D) (D ⁰ = 1) exist in order to enable easy encoding. At this time, P (D) is expressed as in Expression (29).

Hereinafter, data X and parity P at time 2i are represented by X _2i and P _2i , respectively, and data X and parity P at time 2i + 1 are represented by X _{2i + 1} and P _{2i + 1} , respectively (i: integer).

In the present embodiment, an LDPC-CC with a time-varying period of 2 calculated using the equation (27) for the parity P _2i at the time point 2i and calculated using the equation (29) for the parity P _{2i + 1} at the time point 2i + 1 is proposed. To do. Similar to the above-described embodiment, there is an advantage that the parity can be easily obtained sequentially.

Below, it demonstrates using Formula (30) and Formula (31) as an example of Formula (26) and Formula (28).

  At this time, the parity check matrix can be expressed as shown in FIG. In FIG. 49, (Ha, 11) is a portion corresponding to the equation (30), and (Hc, 11) is a portion corresponding to the equation (31). When the BP decoding is performed using the parity check matrix of FIG. 49, that is, the time-varying periodicity 2 parity check matrix, the data reception quality is greatly improved as compared with the LDPC-CC described in the first to sixth embodiments. Confirmed to do.

  Although the case where the time varying period is 2 has been described above, the time varying period is not limited to 2. However, if the time-varying period is too large, it is difficult to puncture periodically, and for example, it is necessary to puncture at random, so that reception quality may be deteriorated. Hereinafter, the advantage that the reception quality is improved by reducing the time-varying period will be described.

ここで、送信系列ベクトルｖ＝（ｖ１、ｖ２、ｖ３、ｖ４、ｖ５、ｖ６、・・・、ｖ2i、ｖ2i+1、・・・）である。 FIG. 50 shows an example of a puncturing method in the case of time varying period 1. In the figure, H is an LDPC-CC parity check matrix, and when a transmission sequence vector is represented by v, a relational expression of Expression (32) is established.

Here, the transmission sequence vector v = (v1, v2, v3, v4, v5, v6,..., V2i, v2i + 1,...).

  FIG. 50 illustrates an example in which a transmission sequence with a coding rate R = 1/2 is punctured to obtain a coding rate R = 3/4. When puncturing is performed periodically, first, a block cycle for selecting puncture bits is set. FIG. 50 shows an example in which the block period is set to 6 and the block is set as indicated by a dotted line (5002). Of the 6 bits constituting one block, 2 bits are selected as puncture bits, and the selected 2 bits are set as bits that are not transmitted. In FIG. 50, a bit 5001 surrounded by a circle is a bit that is not transmitted. In this way, a coding rate of 3/4 can be realized. Therefore, the transmission data series are v1, v3, v4, v5, v7, v9, v11, v13, v15, v16, v17, v19, v21, v22, v23, v25,.

  In FIG. 50, “1” surrounded by a square frame is set to 0 because the initial log likelihood ratio does not exist at the time of reception due to puncturing.

  In BP decoding, row operations and column operations are repeated. Therefore, if two or more bits (erasure bits) for which no initial log likelihood ratio exists (log likelihood ratio is 0) are included in the same row, the initial log likelihood ratio is calculated by column operation in that row. The log-likelihood ratio is not updated by the row operation alone until the log-likelihood ratio of bits for which there is no (the log-likelihood ratio is 0) is updated. That is, the reliability is not propagated by the row operation alone, and in order to propagate the reliability, it is necessary to repeat the row operation and the column operation. Therefore, when there are a large number of such rows, there is a limit on the number of iteration processes in BP decoding, or the reliability is not propagated even if the iteration process is performed many times, which causes deterioration in reception quality. It becomes. In the example shown in FIG. 50, a bit corresponding to 1 surrounded by a square frame indicates an erasure bit, and a row 5003 is a row where reliability is not propagated by a row operation alone, that is, a cause of deterioration of reception quality. Line.

  Therefore, as a method for determining puncture bits (bits not to be transmitted), that is, a method for determining a puncture pattern, it is necessary to search for a method that minimizes the number of rows whose reliability is not propagated by puncture alone. Hereinafter, a search for a puncture bit selection method will be described.

When 2 bits out of 6 bits constituting one block are set as puncture bits, there are _{3 × 2} C ₂ selection methods for 2 bits. Among these, the selection method that is cyclically shifted within 6 bits of the block period can be regarded as the same. Hereinafter, supplementary explanation will be given with reference to FIG. 52A. As an example, FIG. 52A shows six puncture patterns when two of the six bits are continuously punctured. As shown in FIG. 52A, puncture patterns # 1 to # 3 become the same puncture pattern by changing the block delimiter. Similarly, puncture patterns # 4 to # 6 become the same puncture pattern by changing the block delimiter. As described above, the selection methods that are cyclically shifted in the 6 bits of the block period can be regarded as the same. Therefore, there are _{3 × 2} C ₂ × 2 / (3 × 2) = 5 ways to select puncture bits.

When one block is composed of L × k bits and k bits of L × k bits are punctured, there are the number of puncture patterns obtained by Expression (33).

FIG. 52B shows the relationship between the encoded sequence and the puncture pattern when attention is paid to one puncture pattern. As can be seen from FIG. 52B, when 2 bits out of 6 bits constituting one block are punctured, the pattern of the check expression existing for one puncture pattern is (3 × 2) × 1/2. Similarly, when one block is composed of L × k bits and k bits of L × k bits are punctured, there are the number of check equations obtained by Equation (34) for one puncture pattern.

Therefore, in the puncture pattern selection method, it is necessary to check whether or not the reliability is propagated independently for the number of check expressions (rows) obtained from Expression (35).

From the above relationship, when the code rate is 1/2 and the code rate is 3/4, when k bits are punctured from an L × k bit block, the number of check equations obtained from Equation (36) ( It is necessary to check whether or not the reliability is propagated by itself.

  If no good puncture pattern is found, L and k need to be increased.

  Next, consider the case where the time-varying period is m. In this case as well, as in the case where the time-varying period is 1, m different inspection formulas represented by the formula (26) are prepared. Hereinafter, m inspection formulas are named “inspection formula # 1, inspection formula # 2,..., Inspection formula #m”.

なお、式（３７）において、ＬＣＭ｛α，β｝は、自然数αと自然数βとの最小公倍数をあらわす。 Then, the parity P _{mi + 1} at the time point mi + 1 is obtained using the “check equation # 1”, the parity P _{mi + 2} at the time point mi + 2 is obtained using the “check equation # 2”, and the parity P _{mi + m} at the time point mi + m is obtained as “ Consider the LDPC-CC obtained using the “check formula #m”. At this time, when considered in the same manner as in FIG. 49, the parity check matrix is represented as shown in FIG. Then, in the case where the code rate is 1/2 to the code rate 3/4, for example, when puncturing 2 bits from a 6-bit block, when considered similarly to the equation (35), the equation (37) It is necessary to check whether or not the number of check formulas (rows) obtained from (1) alone is a row whose reliability is not propagated.

In Expression (37), LCM {α, β} represents the least common multiple of the natural number α and the natural number β.

  As can be seen from equation (37), as m increases, the number of check equations that must be checked increases. Therefore, a puncturing method that periodically punctures is not suitable, and for example, a method of puncturing at random is used, so that reception quality may be deteriorated.

  Note that in FIG. 52C, when puncturing is performed to generate a code sequence of coding rates R = 2/3, 3/4, and 5/6 by puncturing from L × k bits to k bits, this must be checked. Indicates the number of parity check polynomials that should not be.

  In reality, the time-varying period during which the best puncture pattern can be searched is about 2 to 10. In particular, the time-varying cycle 2 is suitable in consideration of the time-varying cycle in which the best puncture pattern can be searched and the improvement in reception quality. Further, when the time-varying cycle is 2, and the check equations such as the equations (26) and (28) are periodically repeated, there is an advantage that the encoder / decoder can be configured very easily.

  In the case of time-varying periods 3, 4, 5,..., The configuration of the code / decoder is slightly larger than when the time-varying period is 2. Similarly to the above, when a plurality of parity check expressions based on the expressions (26) and (28) are periodically repeated, a simple configuration can be adopted.

  Note that when the time-varying cycle is an extremely long cycle (semi-infinite) or when an LDPC-CC is created based on the LDPC-BC, the time-varying cycle is generally very long. It is difficult to search for the best puncture pattern by adopting a method of selecting puncture bits. For example, it is conceivable to adopt a method of selecting puncture bits at random, but there is a possibility that the reception quality at the time of puncture is greatly degraded.

Incidentally, formula (26), (28), (30), it is also possible to express check polynomial by multiplying the ^{D n} in, on both sides (31). In the present embodiment, there are D ⁰ X (D) and D ⁰ P (D) terms (D ⁰ = 1) in formulas (26), (28), (30) and (31). It was.

In this way, since the parity can be calculated sequentially, the configuration of the encoder is simplified, and in the case of the systematic code, considering the reliability propagation to the data at the time point i, the data and If there is a term of D ⁰ in both of the parities, it is possible to easily understand the reliability propagation to the data, so that the code design can be easily performed. If the ease of code design is not taken into consideration, D ⁰ X (D) does not need to exist in the equations (26), (28), (30), and (31).

  FIG. 53A shows an example of an LDPC-CC parity check matrix with a time varying period of 2. As shown in FIG. 53A, in the case of time-varying period 2, two parity check expressions, a parity check expression 5301 and a parity check expression 5302, are used alternately.

  FIG. 53B shows an example of an LDPC-CC parity check matrix with a time varying period of 4. As shown in FIG. 53B, in the case of time-varying period 4, four parity check expressions, that is, a parity check expression 5301, a parity check expression 5302, a parity check expression 5303, and a parity check expression 5304 are used repeatedly.

  As described above, according to the present embodiment, the parity sequence is determined by the parity check matrix (26) and the parity check polynomial (28) different from the equation (26), and the parity check matrix having a time-varying period of 2 is used. I asked for. Note that the time varying period is not limited to 2, and for example, a parity sequence may be obtained using a parity check matrix having a time varying period 4 as shown in FIG. 53B. However, if the time-varying period m is too large, it is difficult to puncture periodically, and, for example, punctures at random, so that reception quality deteriorates. Realistically, the time-varying period during which an optimum puncture pattern can be searched is about 2 to 10. In this case, reception quality can be improved and puncturing can be performed periodically, so that an LDPC-CC encoder can be easily configured.

  It has been confirmed that good reception quality can be obtained when the row weight in the parity check matrix H, that is, the number of elements with 1 standing among the row elements constituting the parity check matrix is 7 to 12. As described in Non-Patent Document 8, when a code having an excellent minimum distance in a convolutional code is considered, the row weight increases as the constraint length increases. For example, in a feedback convolutional code having a constraint length of 11, Considering that the weight is 14, the point where the row weight is 7 to 12 can be considered as a value peculiar to the LDPC-CC of the present proposal. Further, when considering the merit of code design, the design is facilitated by making the row weights of the rows of the LDPC-CC parity check matrix equal.

  In the above description, the case of coding rate 1/2 has been described. However, the present invention is not limited to this, and a parity sequence is obtained using a check matrix having a time-varying period m even in cases other than coding rate 1/2. The same effect can be obtained when the time varying period is 2 to about 10 time varying periods.

  In particular, when the coding rate R = 5/6, 7/8 or more, in the LDPC-CC having the time varying period 2 or the time varying period m described in the present embodiment, only by a row including two or more erasure bits. Select a puncture pattern that is not configured. In other words, selecting a puncture pattern in which there are 0 or one erasure bit indicates that good reception quality is achieved when the coding rate is high, such as coding rate R = 5/6, 7/8 or higher. It becomes important in getting.

  By using the encoding method described in Embodiment 1 to Embodiment 5 or the encoding method described in Embodiment 1 for LDPC-CC described above, periodic and regular Therefore, it is possible to easily configure the encoder, to obtain good reception quality, and to achieve a very excellent code that can shorten the termination sequence. Can be generated.

(Other embodiment 3)
In the present embodiment, a time-varying LDPC-CC that uses a check equation in which “1” exists in the upper trapezoid matrix of the check matrix and can easily configure the encoder will be described. In the following, a configuration method of time-varying LDPC-CC capable of realizing the coding rate R = 1/2 will be described.

When the coding rate is 1/2 and the polynomial expression of the information sequence (data) is X (D) and the polynomial expression of the parity sequence is P (D), the parity check polynomial is expressed as follows.

In the formula (38), a1, a2,..., An are integers of 1 or more (where a1 ≠ a2 ≠ ... ≠ an). In addition, b1, b2,..., Bm are integers of 1 or more (however, b1 ≠ b2 ≠ ... ≠ bm. Also, c1, c2,..., Cq are −1 or less. As an integer, c1 ≠ c2 ≠... ≠ cq, where P (D) is expressed as follows.

  Similar to the second embodiment, the parity P can be obtained sequentially.

Next, equations (40) and (41) are considered as parity check polynomials with a coding rate of 1/2 different from equation (38).

In the expressions (40) and (41), A1, A2,..., AN are integers of 1 or more (where A1 ≠ A2 ≠ ... ≠ AN). Further, B1, B2,..., BM are integers of 1 or more (where B1 ≠ B2 ≠ ... ≠ BM). C1, C2,..., CQ are integers equal to or less than −1 (where C1 ≠ C2 ≠ ... ≠ CQ). At this time, P (D) is expressed as follows.

Hereinafter, data X and parity P at time 2i are represented by X _2i and P _2i , respectively, and data X and parity P at time 2i + 1 are represented by X _{2i + 1} and P _{2i + 1} , respectively (i: integer).

At this time, the parity P _2i at the time point 2i is obtained by using the equation (39), and the parity P _{2i + 1} at the time point 2i + 1 is obtained by using the equation (42). The LDPC-CC having the time varying period of 2 or the parity at the time point 2i Consider an LDPC-CC with a time-varying period of 2 obtained from P _2i using equation (39) and parity P _{2i + 1} at time 2i + 1 obtained using equation (43).

Such LDPC-CC codes are:
The encoder can be easily configured, and the parity can be obtained sequentially.
• Puncture bits can be set periodically.
-It has the advantage that it is possible to reduce the number of termination bits and improve the reception quality at the time of puncturing at the termination.

Next, consider LDPC-CC with a time-varying period of m. As in the case of the time-varying cycle 2, “check expression # 1” represented by the expression (40) is prepared, and from “check expression # 2” represented by either the expression (40) or the expression (41), “Inspection formula #m” is prepared. Data X and parity P at time _{mi + 1} are represented as X _{mi + 1} and P _{mi + 1} , data X and parity P at time mi + 2 are represented as X _{mi + 2} and P _{mi + 2} , respectively, and data X and parity P at time mi + m are represented respectively. X _{mi + m} and P _{mi + m} (i: integer).

At this time, the parity P _{mi + 1} at the time point mi + 1 is obtained using the “check equation # 1”, the parity P _{mi + 2} at the time point mi + 2 is obtained using the “check equation # 2,” and the parity P _{mi + m} at the time point mi + m is obtained. Consider an LDPC-CC obtained using “checking formula #m”. Such LDPC-CC codes are:
The encoder can be easily configured, and the parity can be obtained sequentially.
-It has the advantage that it is possible to reduce the number of termination bits and improve the reception quality at the time of puncturing at the termination.

  As described above, according to the present embodiment, a parity sequence is obtained using a parity check matrix (38) and a parity check polynomial (40) different from equation (38), and a parity check matrix having a time-varying period of 2. I did it.

  Thus, when using a check equation in which “1” is present in the upper trapezoidal matrix of the check matrix, a time-varying LDPC-CC encoder can be easily configured. The time varying period is not limited to 2. However, when the method of periodically puncturing is employed, the time-varying period in which the best puncture pattern can be actually searched is about 2 to 10.

  In the case of time-varying periods 3, 4, 5,..., The configuration of the code / decoder is slightly larger than when the time-varying period is 2. Similarly to the above, when the inspection formulas of the equations (40) and (41) are periodically repeated, a simple configuration can be adopted.

Incidentally, formula (38), (40), it is also possible to express check polynomial by multiplying the ^{D n} in, on both sides (41). In the present embodiment, it is assumed that D ⁰ X (D) and D ⁰ P (D) terms (D ⁰ = 1) exist in formulas (38), (40), and (41).

In this way, since the parity can be calculated sequentially, the configuration of the encoder is simplified, and in the case of the systematic code, considering the reliability propagation to the data at the time point i, the data and If a term of D ⁰ exists in both of the parities, code design can be easily performed. If the ease of code design is not taken into consideration, D ⁰ X (D) does not need to exist in the equations (38), (40), and (41).

  In addition, it has been confirmed that good reception quality can be obtained when the row weight in the parity check matrix H, that is, the number of elements with 1 standing among the row elements constituting the parity check matrix is 7-12. As described in Non-Patent Document 8, when a code having an excellent minimum distance in a convolutional code is considered, the row weight increases as the constraint length increases. For example, in a feedback convolutional code having a constraint length of 11, Considering that the weight is 14, the point where the row weight is 7 to 12 can be considered as a value peculiar to the LDPC-CC of the present proposal. Further, when considering the merit of code design, the design is facilitated by making the row weights of the rows of the LDPC-CC parity check matrix equal.

  By using the encoding method described in Embodiment 1 to Embodiment 5 or the encoding method described in Embodiment 1 for LDPC-CC described above, periodic and regular Therefore, it is possible to easily configure the encoder, to obtain good reception quality, and to achieve a very excellent code that can shorten the termination sequence. Can be generated.

  The present invention is not limited to all the above embodiments, and can be implemented with various modifications. For example, in the above-described embodiment, the case of performing as a wireless communication device has been described. However, the present invention is not limited to this, and the present invention can also be applied to a case where it is realized by a power line communication device.

  It is also possible to perform this communication method as software. For example, a program for executing the communication method may be stored in advance in a ROM (Read Only Memory), and the program may be operated by a CPU (Central Processor Unit).

  Further, a program for executing the communication method is stored in a computer-readable storage medium, the program stored in the storage medium is recorded in a RAM (Random Access Memory) of the computer, and the computer is operated according to the program. You may do it.

  Needless to say, the present invention is useful not only in wireless communication but also in power line communication (PLC), visible light communication, and optical communication.

  An encoder, a decoder, an encoding method, and a decoding method according to the present invention provide a termination sequence for LDPC-CC encoding with a simple configuration, and reduce the amount of termination sequence transmitted to a transmission line. It is useful as an encoder, decoder, encoding method, and decoding method for performing error correction encoding / decoding using LDPC-CC.

200, 400, 600, 600A, 700, 800 LDPC-CC encoder 210 Termination sequence generator 220, 220A Termination sequence concatenation unit 230, 420, 420A, 610 First encoder 240, 240A, 240B, 430, 620-1 , 620-2, 620A Second encoder 250, 630 Code word concatenation unit 260, 410 Input sequence selection unit 710 Switcher 720 Code word selection unit 900 LDPC-CC decoder

Claims (8)

For an information sequence and a terminal sequence of (M × b) bits or less, a coding rate R = b / c according to a low-density parity check convolutional code (LDPC-CC) parity check matrix. An information code sequence obtained by performing convolutional coding of memory length M and coding the information sequence, and a termination code sequence obtained by coding the termination sequence of (M × b) bits or less , And an encoding unit that outputs
A concatenation unit that outputs a codeword obtained by concatenating the information sequence, the information code sequence, and the terminal code sequence;
Including
The termination sequence is a sequence that is also known in the decoder that is the transmission destination of the codeword.
Encoder. The termination sequence is a sequence in which all bits are 0.
The encoder according to claim 1. For an information sequence and a terminal sequence of (M × b) bits or less, a coding rate R = b / c according to a low-density parity check convolutional code (LDPC-CC) parity check matrix. An information code sequence obtained by performing convolutional coding of memory length M and coding the information sequence, and a termination code sequence obtained by coding the termination sequence of (M × b) bits or less , And an encoding unit that outputs
A concatenation unit that outputs a codeword obtained by concatenating the information sequence, the information code sequence, and the terminal code sequence;
A transmission unit for transmitting the codeword;
Including
The termination sequence is a sequence that is also known in the receiving device that is the transmission destination of the codeword.
Transmitter device. A decoder that performs convolutional decoding with a coding rate R = b / c and a memory length M according to a parity check matrix of a low-density parity check convolutional code (LDPC-CC),
In the encoder that is the communication partner, a termination sequence that is a known sequence is concatenated to the input codeword,
Each of the termination sequence, the information sequence included in the input codeword, the information code sequence obtained by encoding the information sequence, and the termination code sequence obtained by encoding the termination sequence An estimated value is used as an input sequence, BP (Belief Propagation) decoding is performed on the input sequence, and an estimated information sequence obtained by BP decoding is output .
Decoder. The termination sequence is a sequence in which all bits are 0.
The decoder according to claim 4. A receiving unit for receiving a codeword;
In a transmission device that is a communication partner, a termination sequence that is a known sequence, a concatenation unit that concatenates the input codeword,
Each of the termination sequence, the information sequence included in the input codeword, the information code sequence obtained by encoding the information sequence, and the termination code sequence obtained by encoding the termination sequence An estimated value generator for generating an estimated value;
Each of the termination sequence, the information sequence included in the input codeword, the information code sequence obtained by encoding the information sequence, and the termination code sequence obtained by encoding the termination sequence For the estimated value, BP (convolutional decoding BP (coding rate R = b / c) and memory length M) according to a low-density parity-check convolutional code (LDPC-CC) check matrix. A decoding unit which performs decoding and outputs an estimated information sequence obtained by BP decoding;
Including a receiving device. For an information sequence and a terminal sequence of (M × b) bits or less, a coding rate R = b / c according to a low-density parity check convolutional code (LDPC-CC) parity check matrix. Performing convolutional encoding with a memory length of M, setting the information sequence and a termination sequence of (M × b) bits or less as an input sequence, and encoding the input sequence based on the parity check matrix;
Outputting a codeword concatenating the information sequence, an information code sequence obtained by encoding the information sequence, and a termination code sequence obtained by encoding the termination sequence;
Including
The termination sequence is a sequence that is also known in the decoder that is the communication partner of the codeword.
Encoding method. A decoding method for performing convolutional decoding with a coding rate R = b / c and a memory length M according to a parity check matrix of a low-density parity-check convolutional code (LDPC-CC),
A step of concatenating a terminal sequence which is a known sequence in the encoder which is a communication partner to the input codeword;
Each of the termination sequence, the information sequence included in the input codeword, the information code sequence obtained by encoding the information sequence, and the termination code sequence obtained by encoding the termination sequence Using an estimated value as an input sequence, and performing BP (Belief Propagation) decoding on the input sequence;
Outputting an estimated information sequence obtained by BP decoding;
A decryption method.

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