KR20130034153A - Method of forming pattern having narrow width and method of fabricating array substrate for in-plane switching mode liquid crystal display device using the same - Google Patents

Abstract

The present invention includes forming a sacrificial layer having a first thickness of an opaque metal material on a substrate; Forming a photoresist layer over the sacrificial layer; Exposing the photoresist layer using an exposure apparatus; Developing the exposed photoresist layer to form a first photoresist pattern spaced at a first interval; Forming a dummy metal pattern under the first photoresist pattern by removing the sacrificial layer exposed to the outside of the first photoresist pattern; Performing a heat treatment to reflow the first photoresist pattern to increase its width to form a second photoresist pattern having a second gap smaller than the first gap and having the dummy metal pattern undercut; ; Forming a transparent conductive material layer having a second thickness thinner than the first thickness on the entire surface of the substrate over the second photoresist pattern; By removing the first photoresist pattern having the second gap and the transparent conductive material layer in contact therewith, the central common electrode and the pixel electrode having the same first width as the second gap and alternate with each other are formed between the dummy metal patterns. Making a step; A method of manufacturing an array wave for a transverse electric field type liquid crystal display device comprising removing the dummy metal pattern, and an array substrate for a transverse electric field type liquid crystal display device manufactured thereby.

Description

Method of forming pattern having narrow width and Method of fabricating array substrate for In-Plane switching mode liquid crystal display device using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing an array substrate for a transverse electric field type liquid crystal display device capable of improving the aperture ratio by providing a pixel electrode and a common electrode having a line width of 2 m or less. It is about.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (hereinafter, referred to as an active matrix LCD), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention because of its excellent resolution and video performance.

Such a liquid crystal display generally includes a color filter substrate having a common electrode, an array substrate having pixel electrodes, and a liquid crystal interposed between the two substrates. By the method of driving a liquid crystal, it is excellent in characteristics, such as transmittance | permeability and aperture ratio.

However, liquid crystal driving by an electric field which is applied to the upper and lower sides has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, in order to overcome the above disadvantages, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed because both the common electrode and the pixel electrode are provided in an array substrate and driven by a transverse electric field.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the drawing, in the general transverse electric field type liquid crystal display device, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, face each other and are spaced apart from each other. The liquid crystal layer 11 is interposed.

On the lower substrate 10, a common electrode 17 having a bar shape and a pixel electrode 30 are alternately formed on the same plane. In this case, the liquid crystal layer 11 includes the common electrode ( 17) and the horizontal electric field L by the pixel electrode 30.

2A and 2B are cross-sectional views respectively showing the on and off states of a general transverse electric field type liquid crystal display device.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by the horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, in the transverse electric field type liquid crystal display device, since the liquid crystals 11a and 11b operate by the horizontal electric field, the viewing angle becomes wide.

Therefore, when viewed from the front, the transverse electric field type liquid crystal display device can be seen in the up / down / left / right directions even without reversal in about 80 to 89 degrees.

Next, referring to FIG. 2B, since no voltage is applied to the liquid crystal display, a horizontal electric field is not formed between the common electrode 17 and the pixel electrode 30. The array state does not change.

3 is a cross-sectional view of a portion of a conventional transverse electric field type liquid crystal display device obtained by cutting a central portion of one pixel area.

As shown in the drawings, the conventional general horizontal transverse electric field type liquid crystal display array substrate 40 has a plurality of gate wirings (not shown) arranged in a horizontal direction parallel to each other at predetermined intervals, and close to the gate wirings (not shown). To cross the common wiring (not shown) parallel to the gate wiring (not shown), the gate and the common wiring (not shown), and particularly to cross the gate wiring (not shown). The data line 50 defining the structure is composed of a lower portion and an upper portion with a gate insulating film 48 therebetween.

Each pixel region P includes a thin film transistor (not shown) including a gate electrode (not shown), a semiconductor layer (not shown), a source and a drain electrode (not shown), and the thin film transistor ( The protection layer 60 is formed to cover the (not shown).

In addition, the drain electrode (not shown) is disposed in the pixel area P through a drain contact hole (not shown) that exposes a drain electrode (not shown) of the thin film transistor (not shown) over the passivation layer 60. A plurality of pixel electrodes 64 electrically connected to each other and having a bar shape, and a plurality of bar electrodes having a bar shape alternately with and branched from the common wiring (not shown). .

In this case, the pixel electrode 64 and the common electrode 62 having a bar shape formed on the passivation layer 48 generally have a single layer structure of transparent conductive material.

However, in the conventional array substrate for a transverse electric field type liquid crystal display device having such a configuration, the common electrode and the pixel electrode having a bar shape formed in each pixel area have a width of 3 μm or more.

The bar-shaped common electrode and the pixel electrode having a width of 3 μm or more are attributable to the limitation of the resolution of the exposure apparatus currently used in patterning.

That is, a metal layer or a semiconductor layer is formed on a substrate, and a photoresist layer is formed thereon for patterning thereof, and the photoresist layer is developed after exposure using an exposure machine used for manufacturing a liquid crystal display. After forming a photoresist pattern having a predetermined width, a metal pattern or a semiconductor pattern of a desired shape is formed by etching the metal layer or the semiconductor layer positioned below the photoresist pattern using the photoresist pattern as an etching mask.

In this case, in the case of the photoresist pattern formed by performing the exposure process and the development process using the exposure machine, at least the photoresist pattern is usually minimized because it cannot be repeatedly stably set to 3 μm or less due to the resolution of the exposure apparatus at the current level. The width is 3 micrometers.

Meanwhile, FIGS. 3A to 3C are cross-sectional views illustrating manufacturing steps of a conventional transverse field type liquid crystal display array substrate, and illustrate a step of forming a pixel electrode and a common electrode.

As shown in FIGS. 3A to 3C, the transparent conductive material layer in the process of forming the pixel electrode 62 and the common electrode 64 having a bar shape as a transparent conductive material reflecting the maximum resolution of the exposure apparatus ( 61 and the substrate 40 having the photoresist layer 90 formed thereon are positioned on the stage 95 of the exposure apparatus, and then subjected to exposure, from the exposure apparatus due to the characteristics of the transparent conductive material layer 61. After the generated light passes through the photoresist layer 90 and the transparent conductive material layer 61 formed under the photoresist layer 90, the generated light is reflected by the chuck 97 provided on the stage 95 of the exposure apparatus. The exposure amount of the photoresist layer 90 is changed by the light reflected by the chuck 97 between the portion overlapped with 97 and the portion not overlapping with the chuck 97. The photoresist pattern ( 91) will vary in width.

Finally, when the transparent conductive material layer 61 is patterned using the photoresist pattern 91 having such a width difference, the common electrode 64 and the pixel electrode 62 having a bar shape are formed. A difference is occurring.

On the other hand, when the bar-shaped common electrode 64 and the pixel electrode 62 has a width difference for each position, when the image is displayed through the liquid crystal display device having the same, the portion having the width difference is uneven. It appears that the display quality is reduced.

On the other hand, the aperture ratio of each pixel region is defined as an area excluding an area occluded by a component included in each pixel region from the total area of each pixel region. In the case of a conventional array substrate for a transverse electric field type liquid crystal display device, Since the width of the bar-shaped pixel electrode and the common electrode, which is a component that covers the opening of the pixel region, can not be reduced to 3 μm or less, there is a problem in realizing a low power consumption product by improving luminance by increasing the aperture ratio. It is true.

The present invention has been made to solve the problems of the conventional transverse electric field type liquid crystal display device. The bar electrode and the common electrode in each pixel area and made of a transparent conductive material can be stably set to 3 μm or less. It is an object of the present invention to provide a method for manufacturing an array substrate for a transverse electric field type liquid crystal display device which can be formed to have a width to improve the aperture ratio.

Furthermore, another object of the present invention is to provide a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, which can prevent the uneven staining of the exposure device from occurring.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a transverse electric field liquid crystal display device, the method including: forming a sacrificial layer having a first thickness of an opaque metal material on a substrate; Forming a photoresist layer over the sacrificial layer; Exposing the photoresist layer using an exposure apparatus; Developing the exposed photoresist layer to form a first photoresist pattern spaced at a first interval; Forming a dummy metal pattern under the first photoresist pattern by removing the sacrificial layer exposed to the outside of the first photoresist pattern; Performing a heat treatment to reflow the first photoresist pattern to increase its width to form a second photoresist pattern having a second gap smaller than the first gap and having the dummy metal pattern undercut; ; Forming a transparent conductive material layer having a second thickness thinner than the first thickness on the entire surface of the substrate over the second photoresist pattern; By removing the first photoresist pattern having the second gap and the transparent conductive material layer in contact therewith, the central common electrode and the pixel electrode having the same first width as the second gap and alternate with each other are formed between the dummy metal patterns. Making a step; Removing the dummy metal pattern.

At this time, the first interval is 3㎛ or more, the second interval is characterized in that 0.5㎛ to 3㎛.

In addition, the heat treatment is characterized in that for 100 seconds to 250 seconds to proceed in a temperature atmosphere of 130 ℃ to 170 ℃.

The sacrificial layer is made of copper or a copper alloy, and the transparent conductive material layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO).

In addition, before the sacrificial layer is formed, gate wirings and data wirings defining pixel regions crossing each other are formed on the substrate, and common wirings parallel to and spaced apart from the gate wirings, and simultaneously formed on the respective pixel regions. Forming a thin film transistor connected to the gate line and the data line.

In this case, the forming of the pixel electrode and the central common electrode may include connecting a first auxiliary pattern which connects one end of the central common electrode to the upper portion of the protective layer in each pixel region, and one end of the pixel electrode. And forming a second auxiliary pattern spaced apart from each other in parallel with the gate line and facing each other.

The forming of the common line may include forming an outermost common electrode parallel to the data line inside the pixel area and branching from the common line. And forming a drain contact hole exposing the drain electrode of the transistor and a common contact hole exposing one end of the outermost common electrode, wherein the second auxiliary pattern is connected to the drain electrode through the drain contact hole. And the first auxiliary pattern is in contact with the outermost common electrode through the common contact hole.

In addition, the common wiring and the source and drain electrodes may be formed of a metal material which is not affected by a low etch ratio with respect to an etchant for patterning the sacrificial layer as a metal material different from the metal material forming the sacrificial layer.

The forming of the first auxiliary pattern and the second auxiliary pattern may include: a shell connected to the first auxiliary pattern corresponding to the data line and the outermost common electrode at a boundary of each pixel area above the passivation layer; And forming a pattern.

In addition, the data line, the pixel electrode, the outermost part, and the central common electrode have a structure symmetrically bent with respect to the center of each pixel area, so that each pixel area forms a double domain.

An array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention includes: a gate wiring and a data wiring formed on a substrate to define a pixel area crossing each other; A common wiring parallel to and spaced apart from the gate wiring; A thin film transistor connected to the gate line and the data line in each pixel area; A protective layer formed over the thin film transistor; A single layer structure of a transparent conductive material having a line width of 0.5 μm to 3 μm is disposed on the passivation layer, and includes a plurality of pixel electrodes and a central common electrode which are alternately formed.

In this case, each pixel area includes an outermost common electrode branched from the common line and parallel to the data line, and the protective layer includes a drain contact hole exposing a drain electrode of the thin film transistor, and the outermost common electrode. A common contact hole exposing one end is provided, and a first auxiliary pattern connecting both ends of the central common electrode and a second auxiliary pattern connecting both ends of the pixel electrode are provided on the protective layer. The first auxiliary pattern contacts the outermost common electrode through the common contact hole, and the second auxiliary pattern contacts the drain electrode through the drain contact hole.

The data line, the pixel electrode, the outermost part, and the central common electrode form a symmetrically bent structure with respect to the central part of each pixel area, so that each pixel area forms a double domain.

A method of forming a fine conductive pattern according to an embodiment of the present invention includes forming a sacrificial layer having a first thickness of an opaque metal material on a substrate; Forming a photoresist layer over the sacrificial layer; Exposing the photoresist layer using an exposure apparatus; Developing the exposed photoresist layer to form a first photoresist pattern spaced at a first interval; Forming a dummy metal pattern under the first photoresist pattern by removing the sacrificial layer exposed to the outside of the first photoresist pattern; Performing a heat treatment to reflow the first photoresist pattern to increase its width to form a second photoresist pattern having a second gap smaller than the first gap and having the dummy metal pattern undercut; ; Forming a transparent conductive material layer having a second thickness thinner than the first thickness on the entire surface of the substrate over the second photoresist pattern; By removing the first photoresist pattern having the second gap and the transparent conductive material layer in contact therewith, the central common electrode and the pixel electrode having the same first width as the second gap and alternate with each other are formed between the dummy metal patterns. Making a step; Removing the dummy metal pattern.

At this time, the first interval is 3㎛ or more, the second interval is characterized in that 0.5㎛ to 3㎛.

And, the heat treatment is characterized in that for 100 seconds to 250 seconds to proceed in a temperature atmosphere of 130 ℃ to 170 ℃.

The sacrificial layer may be made of copper or a copper alloy, and the transparent conductive material layer may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

In the array substrate for a transverse electric field type liquid crystal display device according to the present invention, after introducing a sacrificial layer made of an opaque metal material, patterning the sacrificial layer, and performing a reflow process through heat treatment of the photoresist pattern, a spaced interval between photoresists And the lift-off process is performed to form a bar-shaped common electrode and a pixel electrode made of a transparent conductive material so as to have a line width smaller than the exposure resolution limit of 3 μm, thereby reflecting by the chuck of the exposure machine. There is an effect to prevent the chuck stain to be at the source, and further improve the aperture ratio.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.
2A and 2B are cross-sectional views showing operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.
3A to 3C are cross-sectional views illustrating manufacturing steps of a conventional transverse field type liquid crystal display array substrate, in which a pixel electrode and a common electrode are formed;
4 is a plan view of one pixel region including a switching element in a transverse electric field type liquid crystal display substrate according to an exemplary embodiment of the present invention.
5 is a cross-sectional view of a portion cut along line V-V in Fig. 4; Fig.
FIG. 6 is a cross-sectional view of a portion cut along the cutting line VI-VI of FIG. 4. FIG.
7A to 7J are cross-sectional views of manufacturing steps for a portion cut along the cutting line VV of FIG. 4.
8A to 8J are cross-sectional views of manufacturing steps of a portion cut along the cutting line VI-VI of FIG. 4.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel area including a switching element in a transverse electric field type liquid crystal display substrate according to an exemplary embodiment of the present invention.

As illustrated, the array substrate 101 for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention has a gate insulating film (not shown) interposed therebetween on a transparent insulating substrate (not shown) made of glass or plastic. As a result, a plurality of gate lines 103 and data lines 130 are formed to define a plurality of pixel regions P by crossing the lower portion and the upper portion thereof horizontally and laterally.

In addition, the insulating substrate (not shown) is made of the same material as the gate wiring 103, is spaced apart from the gate wiring 103, penetrates each pixel region P, and a common wiring 109 is formed.

In the pixel region P, the thin film transistor Tr, which is connected to the gate line 103 and the data line 130 and is a switching element, is disposed near the intersection of the gate line 103 and the data line 130. ) Is formed.

In this case, the thin film transistor Tr includes a gate electrode 105, a gate insulating film (not shown), and a source and drain electrodes 133 and 136 spaced apart from each other. .

On the other hand, each pixel region P is formed of the same material on the same layer on which the common wiring 109 is formed, and is branched from the common wiring 109 to have a common outermost side by side with the data wiring 130. The electrode 116 is formed.

In addition, a first auxiliary pattern 172 is formed in each pixel region P to contact the outermost common electrode 116 through a common contact hole 146. In the first auxiliary pattern 172, the first auxiliary pattern 172 is formed. The plurality of central common electrodes 173 having a bar shape parallel to the outermost common electrode 116 are formed to be spaced apart from each other by a predetermined interval.

In this case, as shown in the drawing, the first auxiliary pattern 172 may overlap the components of the pixel line P to correspond to the data line 130 and the neighboring outermost common electrode 116. Since the shell pattern 175 is further formed by branching, the shell pattern 175 may be formed to minimize the influence of the transverse electric field generated between the common electrodes 116 and 173 and the pixel electrode 170 of the data line 130. In this case, the shell pattern may be omitted.

In addition, a second auxiliary pattern 169 connected to the drain electrode 136 of the thin film transistor Tr through the drain contact hole 143 overlaps the common wiring 210 in each pixel area P. And a plurality of pixel electrodes 170 having a bar shape branching from the second auxiliary pattern 169 toward the innermost outermost common electrode 116 and forming the plurality of central common electrodes 173. It is formed alternately with.

In this case, the outermost and central common electrodes 116 and 173 having a bar shape and the pixel electrode 170 are virtual reference lines parallel to the gate wiring 103 positioned at the center of each pixel region P. FIG. The upper and lower portions of the pixel region P have a predetermined angle symmetrically with respect to the center portion of the pixel region P, so that the upper and lower portions of the common electrode 116 and 173 and the pixel electrode 170 are aligned. It is characterized by forming different domain regions by forming differently.

The dual domains are formed by forming the common electrodes 116 and 173 and the pixel electrodes 170 in different directions in one pixel region P. Thus, the display quality is reduced by suppressing the color difference caused by the change in the viewing angle of the user. To improve.

 On the other hand, the plurality of pixel electrodes 170 and the common electrodes 116 and 173 have a configuration in which they are bent in each pixel region P, so that the data line 130 is also referred to as the center of each pixel region P. FIG. It is characterized by having a symmetrically folded configuration.

In this case, the data line 130 is not separately formed for each pixel area P, but has a configuration connected to the entire display area. Therefore, the data line 130 has a central portion of each pixel area P in the display area. It is characterized by a zigzag shape that is bent by reference.

Meanwhile, in the array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention, the common electrodes 116 and 173, the pixel electrode 170, and the data wiring 130 have a central portion of each pixel region P. FIG. Although it is shown as an example to form a double domain structure by forming the configuration bent by the reference, the common electrode 116, 173, the pixel electrode 170 and the data line 130 must be referred to the central portion of each pixel region (P) It is not necessary to form a curved structure, but may be a straight line form.

The common wiring 109 and the drain electrode which overlap each other with the common wiring 109 and the drain electrode 136 are formed in each pixel area P so as to overlap each other with a gate insulating film (not shown) therebetween. 136 forms the first and second storage electrodes 110 and 138, respectively, and the first and second storage electrodes 110 and 138 and the gate insulating layer (not shown) overlapping the storage capacitor StgC )

The most characteristic of the present invention is that the bar-shaped central common electrode 173 and the pixel electrode 170 formed on the protective layer (not shown) covering the thin film transistor Tr are transparent. Conductive material, for example indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) single layer structure, each line width is 3㎛ the minimum line width that can be formed through the maximum resolution of the exposure apparatus It is characteristic that it becomes 0.5-3 micrometers as an example of the line width smaller or the same.

Accordingly, in the case of the array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention having such a configuration, the line width of the common electrode and the pixel electrode is 3 μm or less, compared to the conventional array substrate having a line width of 3 μm or more. Has the advantage that the aperture ratio is improved.

Since the characteristic configuration of the present invention can be better expressed through a cross-sectional structure, a cross-sectional configuration of an array substrate for a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a cross-sectional view of a portion taken along the cutting line VV of FIG. 4, and FIG. 6 is a cross-sectional view of a portion taken along the cutting line VI-VI of FIG. 4. For convenience of description, a region in which the thin film transistor Tr, which is a switching element, is formed is defined as a switching region TrA, and a region in which the storage capacitor StgC is formed is defined as a storage region StgA.

As shown in FIG. 4, gate wirings 103 in FIG. 4 are formed on the transparent insulating substrate 102 and common wirings are spaced apart from the gate wirings 103 in FIG. 3. 109 is formed. In this case, the gate line 103 in FIG. 4 is a portion of the gate line 105 corresponding to the switching region TrA.

Each pixel area P is formed in the common area 109 of FIG. 4 to be adjacent to the data line 130 to form the outermost common electrode 116. The storage area StgA has the common wire. As shown in FIG. 4, the first storage electrode 110 is formed.

Next, an inorganic insulating material, eg, silicon oxide (SiO ₂ ), is formed on the entire surface of the gate wiring (103 in FIG. 4), the gate electrode 105, the common wiring (109 in FIG. 4), and the outermost common electrode 116. Alternatively, a gate insulating film 118 made of silicon nitride (SiNx) is formed.

In addition, an active layer 120a made of pure amorphous silicon and an ohmic contact layer 120b formed of impurity amorphous silicon and spaced apart from each other in the switching region TrA on the gate insulating layer 118. The semiconductor layer 120 is formed.

On the other hand, a data line 130 is formed on the gate insulating layer 118 to define the pixel region P by crossing the gate line 103 (see FIG. 4). In this case, although the semiconductor pattern 121 including the first and second patterns 121a and 121b made of the same material constituting the semiconductor layer 120 is formed under the data line 130, the semiconductor pattern ( 121) may be omitted due to the manufacturing process.

In the switching region TrA, a source electrode 133 is formed on the semiconductor layer 120 by branching from the data line 130, and the drain electrode 136 is spaced apart from the source electrode 133. Formed. In this case, the source electrode 133 and the drain electrode 136 are in contact with the ohmic contact layer 120b spaced apart from each other.

The gate electrode 105, the gate insulating layer 118, the semiconductor layer 120, and the source and drain electrodes 133 and 136 spaced apart from each other, sequentially stacked in the switching region TrA, are thin film transistors Tr as switching elements. To achieve.

The drain electrode 136 extends in the storage region StgA to correspond to the first storage electrode 110 to form the second storage electrode 138. In this case, the first storage electrode 110, the gate insulating layer 118, and the second storage electrode 138 sequentially stacked in the storage region StgA form a storage capacitor StgC.

Next, an organic insulating material, for example, a material having a relatively low dielectric constant value is formed on the data line 130, the source and drain electrodes 133 and 136, and the second storage electrode 138. The protective layer 140 is formed.

The protective layer 140 may be formed of photo acryl having low dielectric constant by overlapping with the shell pattern 175 formed on the data line 130 and the outermost common electrode 116. This is to minimize the parasitic capacitance generated by the parasitic capacitance and to minimize the influence of the unwanted electric field generated by the outermost common electrode 116 formed around the data line 130 and the data line 130.

Meanwhile, the protective layer 140 made of photo acryl having such low dielectric constant has a common contact hole (146 of FIG. 4) exposing one end of the outermost common electrode 116 and the drain. More specifically, a drain contact hole 143 is formed to expose the second storage electrode 138, which is an extended portion of the electrode 136.

Next, a first layer having a single layer structure made of indium tin oxide (ITO), which is a transparent conductive material, is formed on the passivation layer 140 including the common contact hole 146 and the drain contact hole 143. The auxiliary pattern 172 of FIG. 4 and the second auxiliary pattern 169 are formed to face each other.

In this case, the first auxiliary pattern 172 of FIG. 4 is in contact with the outermost common electrode 116 through the common contact hole 146 of FIG. 4, and the second auxiliary pattern 169 is connected to the drain. The second storage electrode 138 is connected to the drain electrode 136 through the contact hole 143.

In addition, the shielding pattern 175 overlaps with the data line 130 and the outermost common electrode 116 adjacent to the data line 130 in a form branching from the first auxiliary pattern 172 of FIG. 4. ) Is selectively formed.

In this case, the shell pattern 175 overlapping the data line 130 and the outermost common electrode 116 and branching from the first auxiliary pattern 172 of FIG. 4 may be omitted.

In addition, in each pixel area P, the plurality of central common electrodes 173 in the form of a bar branching from the first auxiliary pattern (172 of FIG. 4) and having a double layer structure are formed on the passivation layer 140. The outermost common electrode 116 is spaced apart from each other by a predetermined interval.

Each pixel region P branches from the second auxiliary pattern 169 and alternates with a plurality of central common electrodes 173 having a bar shape inside the outermost common electrode 116. A plurality of pixel electrodes 170 having a bar shape are formed.

In this case, the plurality of pixel electrodes 170 and the central common electrode 173 also form a single layer structure made of indium tin oxide (ITO), which is a transparent conductive material, and each line width is smaller than or equal to 3 μm. It is characteristic.

The plurality of pixel electrodes 170 and the central common electrode 173 having a bar shape may be formed to have a minimum line width of 3 μm or less in consideration of the resolution of the exposure apparatus. It is due to this and will be described in detail later through the manufacturing method.

On the other hand, as described above, the horizontal field type liquid crystal display device including the array substrate 101 on which the plurality of bar-shaped pixel electrodes 170 having a line width of 3 μm or less and the central common electrode 173 are formed is provided. In the pixel region P, the aperture ratio may be improved by reducing the line widths of the pixel electrode 170 and the central common electrode 173 as compared with the related art.

Hereinafter, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention having the above-described structure will be described.

7A to 7J are cross-sectional views of manufacturing steps of the portion cut along the cutting line V-V of FIG. 4, and FIGS. 8A to 8J are cross-sectional views of the manufacturing step of the portion cut to the cutting line VI-VI of FIG. 4. to be. For convenience of description, a region in which the thin film transistor Tr, which is a switching element, is formed is defined as a switching region TrA, and a region in which the storage capacitor StgC is formed is defined as a storage region StgA.

First, as shown in FIGS. 7A and 8A, a first metal material such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and molybdenum (MoTi) on the transparent insulating substrate 102 may be used. The first metal layer (not shown) is formed by depositing any one or more materials.

Subsequently, a gate wiring (not shown) extending in one direction by a patterning of the first metal layer (not shown), a common wiring (not shown) extending in parallel with each other, and a gate connected to the gate wiring (not shown) An outermost common electrode 116 connected to the electrode 105 and the common wiring (not shown) is formed.

Next, as shown in FIGS. 7B and 8B, an inorganic insulating material may be formed on the front surface of the gate wiring (not shown), the common wiring (not shown), the gate electrode 103, and the outermost common electrode 116. Silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited to form a gate insulating film 118 on the entire surface.

Subsequently, a pure amorphous silicon layer (not shown), an impurity amorphous silicon layer (not shown), and a second metal material layer (not shown) are formed on the gate insulating layer 118. In this case, the second metal material may be made of any one or two or more of aluminum (Al), aluminum alloy (AlNd), chromium (Cr), molybdenum (Mo), and molybdenum (MoTi).

Next, the second metal material layer (not shown) and the impurity and pure amorphous silicon layer (not shown) are simultaneously patterned through one mask process including diffraction exposure or halftone exposure, or two mask processes are performed. By patterning the second metal material layer (not shown) and the impurity and pure amorphous silicon layer (not shown), respectively, to form the pure amorphous silicon active layer corresponding to the gate electrode 105 in the pixel region P. The semiconductor layer 120 including the ohmic contact layer 120b of impurity amorphous silicon spaced apart from each other by a predetermined distance over the active layer 120a and 120a, and the second metal material formed on the ohmic contact layer 120b. Source and drain electrodes 133 and 136 are spaced apart.

At the same time, a data line 130 defining a pixel region P is formed on the gate insulating layer 118 by crossing the gate line (not shown).

In this case, the drain electrode 136 extends to a portion where the common wiring 113 is formed, and thus the common electrode (not shown) and the drain electrode 136 overlapping each other with the gate insulating layer 118 interposed therebetween. By forming the first and second storage electrodes 110 and 138, the first storage electrode 110, the gate insulating layer 118, and the second storage electrode 138 sequentially stacked in the storage region StgA are connected to a storage capacitor ( StgC).

The source and drain electrodes 133 and 136 spaced apart from the gate electrode 110, the gate insulating layer 118, and the semiconductor layer 120 sequentially stacked in the switching region TrA in each pixel region P may be formed. It forms a thin film transistor (Tr) that is a switching element.

In the exemplary embodiment of the present invention, the second metal material layer (not shown) and the impurity and pure amorphous silicon layer (not shown) are formed by performing one mask process including halftone exposure or diffraction exposure. As an example, the semiconductor pattern including the first and second patterns 121a and 121b is formed of the same material forming the active layer 120a and the ohmic contact layer 120b under the data line 130. It is shown that 121 is formed.

However, the semiconductor layer 120 is formed by first patterning the impurity and the pure amorphous silicon layer (not shown) by first masking, and then forming a second metal material layer (not shown) on the semiconductor layer 120. After patterning, the semiconductor pattern 121 formed under the data line 130 is omitted.

Next, as illustrated in FIGS. 7C and 8C, an organic insulating material, for example, a photoacryl having a relatively low dielectric constant value, for example, the organic insulating material is formed on the data line 130 and the thin film transistor Tr. Coating to form a protective layer 140 on the entire surface of the substrate 102.

Subsequently, a mask process is performed on the protective layer 140 to expose the second contact electrode 138 connected to the drain electrode 136 and the outermost common electrode 116. A common contact hole (not shown) exposing one end is formed.

Next, as shown in FIGS. 7D and 8D, the common wiring (not shown) and the opaque metal material are disposed on the protective layer 140 having the drain contact hole 143 and the common contact hole (not shown). An etchant for patterning the metal material forming the source and drain electrodes 133 and 136 as another material has a large etching ratio with the metal material forming the common wiring (not shown) and the source and drain electrodes 133 and 136. The sacrificial layer 145 may be deposited by depositing a metal material, for example, copper (Cu) or a copper alloy, which may be a material that hardly reacts with a material forming the common wiring (not shown) and the source and drain electrodes 133 and 136. To form.

Next, a photoresist is coated on the sacrificial layer 145 to form a photoresist layer 190.

Thereafter, the substrate 102 having the photoresist layer 190 formed on the sacrificial layer 145 is positioned on the chuck 197 of the stage 195 of the exposure apparatus, and then exposed through an exposure mask (not shown). The photoresist layer 190 is exposed to light.

In this case, since the sacrificial layer 145 is made of an opaque metal material, light emitted from the exposure apparatus is blocked by the sacrificial layer 145 and thus does not reach the chuck 197 of the stage 195. By reflecting by 197, the phenomenon in which the photoresist layer 190 corresponding to the undesired portion is exposed or the exposure amount at the portion corresponding to the chuck 197 and the portion not corresponding to the chuck 197 may be fundamentally suppressed.

Next, as shown in FIGS. 7E and 8E, the first photoresist pattern 191 is formed on the sacrificial layer 145 by developing the exposed photoresist layer 190 (FIGS. 7D and 8D). When the first photoresist pattern 191 is formed to reflect the highest resolution of the exposure apparatus, the minimum line width is about 3 μm, and the minimum width w4 of the separation interval between the first photoresist patterns 191 is It can be formed so that it may become about 3 micrometers.

Next, as illustrated in FIGS. 7F and 8F, the first photoresist pattern 191 may be removed by etching the sacrificial layer (145 of FIGS. 7E and 8E) exposed to the outside of the first photoresist pattern 191. A dummy metal pattern 147 is formed below. In this case, the etching solution is characterized in that the etching ratio for the copper or copper alloy which is a metal material constituting the sacrificial layer (145 of FIGS. 7E and 8E) is large and the etching ratio is low for other metal materials.

Accordingly, the drain contact hole 143 and the common contact hole (not shown) provided in the protective layer 140 may be exposed by removing the sacrificial layers 145 of FIGS. 7E and 8E. Since the outermost common electrode 116 has little effect, the drain electrode 136 and the outermost electrode 116 exposed inside each of the contact holes 143 and the outermost electrode 116 are not etched and the upper surface is exposed. Will be maintained.

Next, as shown in FIGS. 7G and 8G, the substrate 102 having the dummy metal pattern 147 formed under the first photoresist pattern 191 in a temperature atmosphere of 130 ° C. to 170 ° C. for 100 seconds. The second photoresist pattern 192 may be formed by reflowing the first photoresist pattern by performing a heat treatment process for exposing the second photoresist to 250 seconds.

That is, the thickness of the first photoresist pattern 191 is reduced by the heat treatment process having the above-described conditions, and instead, the second photoresist pattern 192 having a wider width is formed. The pattern 147 may have an undercut shape with respect to the second photoresist pattern 192 having a wider width.

In this case, before the heat treatment, the spacing interval w4 between the first photoresist patterns 191 provided at the center of each pixel region P has a minimum value of 3 μm, but after the heat treatment, the first photoresist pattern 191 ) Is spaced apart (w5) between the second photoresist pattern (192) formed by the deformation is characterized in that having a spacing interval less than 3㎛.

Next, as shown in FIGS. 7H and 8H, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the second photoresist pattern 192. A transparent conductive material layer 166 is formed on the entire surface of the substrate 102. In this case, the transparent conductive material layer 166 may be formed to have a thickness thinner than the thickness of the dummy metal pattern 147.

In this case, the dummy metal pattern 147 may be formed with respect to the second photoresist pattern 192 in the transparent conductive material layer formed in direct contact with the protective layer 140 exposed between the second photoresist pattern 192. A transparent conductive material layer having an undercut shape and provided on the top and side surfaces of the second photoresist pattern 192 due to the characteristic that the dummy metal pattern 147 has a thickness greater than that of the transparent conductive material layer 166. The pixel electrode 170, the central common electrode 173, the first and second auxiliary patterns 172 and 169, and the shell pattern 175 are formed by being separated from the 166.

The first auxiliary pattern 172 contacts the outermost common electrode 116 through the common contact hole (not shown), and the drain contact hole 143 in the second auxiliary pattern 169. In contact with the drain electrode 136 through.

Meanwhile, the central common electrode 173 and the pixel electrode 170, which are alternately spaced apart from each other as transparent conductive materials in the pixel region P, have a width w3 of the second photoresist pattern 192. Since the spaced intervals are characterized by achieving a line width having a size of 3㎛ or less.

In addition, since the central common electrode 173 and the pixel electrode 170 are patterned without an exposure process, the central common electrode 173 and the pixel electrode 170 may be prevented from being stained due to poor line width caused by reflection by the chuck.

Next, as illustrated in FIGS. 7I and 8I, the pixel electrode 170 having a bar shape and the central common electrode 173 may be formed, including the transparent conductive material layer (166 of FIGS. 7H and 8H). The substrate 102 having the first and second auxiliary patterns 172 and 169 and the shell pattern 175 is exposed to a developer that reacts with the second photoresist pattern 192 of FIGS. 7H and 8H. The center portion on the protective layer 140 by removing the photoresist pattern 192 of FIGS. 7H and 8H and the transparent conductive material layer 166 of FIGS. 7H and 8H formed in contact with the top and side surfaces thereof. The common electrode 173 and the pixel electrode 170, the first and second auxiliary patterns 172 and 169, and the shell pattern 175 remain. Thus, the process of removing the second photoresist pattern (192 of FIGS. 7H and 8H) together with the transparent conductive material layer (166 of FIGS. 7H and 8H) formed in contact with the upper portion thereof is lifted off. It is called a process.

Next, as shown in FIGS. 7J and 8J, the metal forming the dummy metal pattern 147 of FIGS. 7I and 8I exposed by removing the second photoresist pattern 192 of FIGS. 7H and 8H is removed. The dummy metal pattern may be etched using an etchant having a high etching ratio with respect to the copper or copper alloy as a material and having little effect on the transparent conductive material forming the central common electrode 173 and the pixel electrode 170. By removing 147 of FIGS. 7I and 8I, the array substrate 101 for a transverse electric field type liquid crystal display device according to the embodiment of the present invention is completed.

In the case of the array substrate 101 for a transverse electric field type liquid crystal display device, the line width of each of the central common electrode 173 and the pixel electrode 170 is made of a transparent conductive material and is caused by chuck reflection. The width w3 is 3 μm or less, more precisely 0.5 to 3 μm, thereby improving the aperture ratio compared to an array substrate having a common electrode and a pixel electrode having a line width of 3 μm or more.

Meanwhile, in the exemplary embodiment of the present invention, the pixel electrode 170 and the center common electrode 173 having a line width of 0.5 to 3 μm having a bar shape are formed as an example, but the thickness is about 0.5 to 3 μm. It will be apparent that the process may be performed in any process of forming a metal pattern or a metal wiring requiring a line width.

102: insulating substrate 105: gate electrode
110: first storage electrode 116: outermost common electrode
118: gate insulating film 133: source electrode
136: drain electrode 138: second storage electrode
140: protective layer 143: drain contact hole
147: dummy metal pattern 191: first photoresist pattern
192: second photoresist pattern
P: Pixel Area StgA: Storage Area
StgC: Storage Capacitor Tr: Thin Film Transistor
TrA: switching area
w4: spacing between the first photoresist patterns
w5: spacing between the second photoresist patterns

Claims (17)

Forming a sacrificial layer of a first thickness of opaque metal on the substrate;
Forming a photoresist layer over the sacrificial layer;
Exposing the photoresist layer using an exposure apparatus;
Developing the exposed photoresist layer to form a first photoresist pattern spaced at a first interval;
Forming a dummy metal pattern under the first photoresist pattern by removing the sacrificial layer exposed to the outside of the first photoresist pattern;
Performing a heat treatment to reflow the first photoresist pattern to increase its width to form a second photoresist pattern having a second gap smaller than the first gap and having the dummy metal pattern undercut; ;
Forming a transparent conductive material layer having a second thickness thinner than the first thickness on the entire surface of the substrate over the second photoresist pattern;
By removing the first photoresist pattern having the second gap and the transparent conductive material layer in contact therewith, the central common electrode and the pixel electrode having the same first width as the second gap and alternate with each other are formed between the dummy metal patterns. Making a step;
Removing the dummy metal pattern
Method of manufacturing an array wave for a transverse electric field type liquid crystal display device comprising a.
The method of claim 1,
And said first interval is at least 3 μm, and wherein said second interval is from 0.5 μm to 3 μm.
The method of claim 1,
The heat treatment is performed for 100 seconds to 250 seconds in a temperature atmosphere of 130 ℃ to 170 ℃ manufacturing method of array waves for a transverse electric field type liquid crystal display device.
The method of claim 1,
The sacrificial layer is made of copper or a copper alloy, and the transparent conductive material layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO). Way.
The method of claim 1,
Before forming the sacrificial layer,
A gate line and a data line intersecting each other on the substrate to define a pixel region, and a common line parallel to and spaced apart from the gate line, and simultaneously forming a thin film transistor connected to the gate line and the data line in each pixel region. Forming steps
And forming a plurality of pixel electrodes on the array substrate.
The method of claim 5, wherein
Forming the pixel electrode and the central common electrode,
The first auxiliary pattern connecting all of one end of the central common electrode on the passivation layer in each pixel area and the second auxiliary pattern connecting all of one end of the pixel electrode are spaced apart from each other in parallel with the gate wiring. A manufacturing method of an array substrate for a transverse electric field type liquid crystal display device comprising the step of facing each other.
The method according to claim 6,
The forming of the common wiring may include forming an outermost common electrode in the pixel area and parallel to the data wiring in the pixel area.
The forming of the protective layer includes forming a drain contact hole exposing the drain electrode of the thin film transistor and a common contact hole exposing one end of the outermost common electrode,
Wherein the second auxiliary pattern contacts the drain electrode through the drain contact hole, and the first auxiliary pattern contacts the outermost common electrode through the common contact hole. Method of manufacturing an array substrate.
The method of claim 7, wherein
The common wiring and the source and drain electrodes are metal materials different from those of the sacrificial layer, and the transverse electric field liquid crystal characterized in that the etching solution for patterning the sacrificial layer is made of a metal material which is not affected by low etching ratio. Method of manufacturing array substrate for display device.
The method of claim 7, wherein
Forming the first auxiliary pattern and the second auxiliary pattern,
And forming a shell pattern connected to the first auxiliary pattern to the data line and the outermost common electrode on the boundary of each pixel area above the passivation layer. Method of manufacturing a substrate.
The method of claim 7, wherein
The data line, the pixel electrode, the outermost part, and the central common electrode have a structure symmetrically bent with respect to the center of each pixel area, so that each pixel area is formed to have a dual domain. Method for producing an array substrate for use.
A gate wiring and a data wiring formed on the substrate to cross each other to define a pixel region;
A common wiring parallel to and spaced apart from the gate wiring;
A thin film transistor connected to the gate line and the data line in each pixel area;
A protective layer formed on the thin film transistor;
A plurality of pixel electrodes and a central common electrode formed in a single layer structure of a transparent conductive material having a line width of 0.5 μm to 3 μm over the passivation layer, which are alternately formed.
Array substrate for a transverse electric field type liquid crystal display device comprising a.
The method of claim 11,
Each pixel area includes an outermost common electrode branched from the common line and parallel to the data line.
The protective layer includes a drain contact hole exposing the drain electrode of the thin film transistor and a common contact hole exposing one end of the outermost common electrode.
A first auxiliary pattern connecting both ends of the central common electrode and a second auxiliary pattern connecting both ends of the pixel electrode are provided on the passivation layer.
And the first auxiliary pattern contacts the outermost common electrode through the common contact hole, and the second auxiliary pattern contacts the drain electrode through the drain contact hole. .
The method of claim 11,
The data line, the pixel electrode, the outermost part, and the central common electrode have a structure symmetrically bent with respect to the center of each pixel area so that each pixel area forms a double domain. Board.
Forming a sacrificial layer of a first thickness of opaque metal on the substrate;
Forming a photoresist layer over the sacrificial layer;
Exposing the photoresist layer using an exposure apparatus;
Developing the exposed photoresist layer to form a first photoresist pattern spaced at a first interval;
Forming a dummy metal pattern under the first photoresist pattern by removing the sacrificial layer exposed to the outside of the first photoresist pattern;
Performing a heat treatment to reflow the first photoresist pattern to increase its width to form a second photoresist pattern having a second gap smaller than the first gap and having the dummy metal pattern undercut; ;
Forming a transparent conductive material layer having a second thickness thinner than the first thickness on the entire surface of the substrate over the second photoresist pattern;
By removing the first photoresist pattern having the second gap and the transparent conductive material layer in contact therewith, the central common electrode and the pixel electrode having the same first width as the second gap and alternate with each other are formed between the dummy metal patterns. Making a step;
Removing the dummy metal pattern
Fine conductive pattern forming method comprising a.
15. The method of claim 14,
The first gap is 3 μm or more, and the second gap is 0.5 μm to 3 μm.
15. The method of claim 14,
The heat treatment is a method for forming a fine conductive pattern, characterized in that for 100 seconds to 250 seconds in a temperature atmosphere of 130 ℃ to 170 ℃.
15. The method of claim 14,
The sacrificial layer is made of copper or a copper alloy, and the transparent conductive material layer is indium tin oxide (ITO) or indium zinc oxide (IZO).

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