KR20130024990A - Array substrate for advanced high in plane switching mode liquid crystal display device and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array panel for an AHIPS mode liquid crystal display device capable of improving transmittance and a manufacturing method thereof are provided to improve the etch rate by using an IZO(Indium Zinc Oxide) composite as a common electrode of the AH-IPS mode liquid crystal display. CONSTITUTION: A thin film transistor is formed between a data line and a gate line(105a). A pixel electrode(103b) is formed in a pixel region of a substrate(101). A passivation film(123) is formed on the substrate. A common electrode(125a) is formed on the passivation film. The common electrode is made of a transparent conductive material including an IZO(Indium Zinc Oxide) composite. A pixel electrode connection pattern(125b) electrically connects the pixel electrode and the thin film transistor.

Description

AR substrate for LCD system and its manufacturing method {ARRAY SUBSTRATE FOR ADVANCED HIGH IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an Advanced High In Plane Switching (AH-IPS) type liquid crystal display device and a method of manufacturing the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

The transverse type liquid crystal display device includes a color filter substrate and an array substrate facing each other, and a liquid crystal layer is interposed between the color filter substrate and the array substrate.

The array substrate includes a thin film transistor, a common electrode, and a pixel electrode for each of a plurality of pixels defined in a transparent insulating substrate.

In addition, the common electrode and the pixel electrode are configured to be spaced apart from each other in parallel on the same substrate.

In the color filter substrate, a black matrix is formed at a portion corresponding to a gate wiring, a data wiring, and a thin film transistor on a transparent insulating substrate, and a color filter is formed corresponding to the pixel.

The liquid crystal layer is driven by a horizontal electric field of the common electrode and the pixel electrode.

In the transverse electric field liquid crystal display device having the above configuration, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure luminance, but by design, the common electrode and the pixel are separated by a distance between the common electrode and the pixel electrode. Only a part of both ends of the electrode contribute to the improvement of brightness, and most areas result in light blocking.

Therefore, the proposed technique to maximize the effect of improving the brightness is the FFS (Fringe Field Switching) technology. The FFS technology is characterized in that a high contrast ratio can be obtained without a color shift by precisely controlling the liquid crystal, and thus, there is an advantage in that a high screen quality can be realized compared to a general transverse electric field technology.

Referring to FIG. 1, a FFS (Fringe Field Switching) type liquid crystal display according to the related art having an advantage of realizing such a high screen quality is described below.

1 is a cross-sectional view of an array substrate for a FPS type liquid crystal display device according to the prior art.

As shown in FIG. 1, an array substrate for a liquid crystal display (FFS) type liquid crystal display device according to the prior art includes a plurality of gate wirings 13 extending in one direction on the substrate 11 and spaced in parallel with each other. ; A plurality of data wirings (not shown) that cross the gate wirings 13 and define pixel regions in the crossing areas; A thin film transistor T provided at the intersection of the gate line 13 and the data line (not shown) and including a gate electrode 13a, an active layer 19, a source electrode 23a, and a drain electrode 23b. It is configured to include).

In addition, a transparent pixel electrode 15 is disposed on a front surface of the pixel region with a space spaced apart from the gate wiring 13 and a data wiring (not shown), and a gate insulating layer 17 is disposed on the pixel electrode 15. ) And a plurality of rod-shaped transparent common electrodes 29a are disposed between the passivation layer and the passivation layer 25. In this case, the pixel electrode 15 and the plurality of common electrodes 29a are formed of indium tin oxide (ITO), which is a transparent conductive material.

The pixel electrode 15 is electrically connected to the pixel electrode connection pattern 29b connected to the drain electrode 23b.

According to the above configuration, when the video signal is supplied to the pixel electrode 15 via the thin film transistor T, the common electrodes 29a supplied with the common voltage form a fringe field to form a fringe field. Liquid crystal molecules arranged in a horizontal direction between filter substrates (not shown) are rotated by dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

As described above, according to the conventional FPS type liquid crystal display array substrate, both the pixel electrode and the common electrode are used as an ITO film which is a transparent conductive material, and the pixel electrode is disposed on the same layer as the gate electrode. The common electrode is formed on the top layer in a finger pattern.

Therefore, in the case of the ITO material used as the common electrode of the conventional FPS type liquid crystal display array substrate, since the etching speed is slow, the width of the common electrode to be applied during the manufacturing process of the liquid crystal display device, that is, It is difficult to implement the CD (Critical Dimension) of 2.3 μm or less, and thus the panel transmittance is a weak point in the manufacturing process of the liquid crystal display.

In particular, at the time of patterning for using ITO, which is a transparent conductive material, as a common electrode of a liquid crystal display device, the etching speed of ITO is low and thus there is a limit in forming a fine pattern.

In addition, during ITO patterning, which is a transparent conductive material, a problem may occur that the lower layer under the ITO layer may be damaged by etching due to the continued etching process.

Accordingly, an object of the present invention is to improve the transmittance of a liquid crystal panel by realizing a fine pattern of an advanced high in plane switching (AH-IPS) type liquid crystal display device. The present invention provides an array substrate for an Advanced High In Plane Switching (AH-IPS) type liquid crystal display device and a method of manufacturing the same.

According to an exemplary embodiment of the present invention, an H-IPS array substrate for a liquid crystal display device includes: a gate wiring formed on one surface of a substrate in one direction; A data line crossing the gate line to define a pixel area; A thin film transistor formed at a point of intersection of the gate line and the data line; A pixel electrode formed in the pixel region of the substrate; A protective film formed on an entire surface of the substrate including the pixel electrode and the thin film transistor; A plurality of common electrodes formed of an indium zinc oxide (IZO) composition, which is a transparent conductive material, on the passivation layer and spaced apart from each other; And a pixel electrode connection pattern electrically connecting the pixel electrode and the thin film transistor.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for an H-IPS type liquid crystal display device, comprising: forming a gate wiring on one surface of a substrate in one direction; Forming a thin film transistor at the intersection of the data line defining the pixel area crossing the gate line and the gate line and the data line; Forming a pixel electrode in the pixel region of the substrate; Forming a protective film on an entire surface of the substrate including the pixel electrode and the thin film transistor; And forming a pixel electrode connection pattern electrically connecting the pixel electrode and the thin film transistor together with a plurality of common electrodes spaced apart from each other by using an indium zinc oxide (IZO) composition, which is a transparent conductive material, on the passivation layer. Characterized in that it comprises a.

According to the H-IPS type array substrate and the manufacturing method thereof according to the present invention has the following advantages.

 According to the H-IPS (AH-IPS) type liquid crystal display array substrate and a method for manufacturing the same according to the present invention, IZO (Indium Zinc Oxide) composition which is a transparent conductive material with a fast etching speed instead of the ITO with a slow etching speed By using as a common electrode of the AH-IPS type liquid crystal display device, the etching rate (etch rate) is improved to implement a fine electrode pattern, thereby improving the transmittance compared to the same thickness of ITO .

In particular, according to the H-IPS (AH-IPS) array substrate for a liquid crystal display device and a method of manufacturing the same, using an IZO (Indium Zinc Oxide) composition, which is a transparent conductive material having an excellent etching rate compared to conventional ITO Therefore, it is possible to implement a fine line width of the width of the common electrode, and the distance between the common electrodes can be adjusted, so that the transmittance is improved as compared with the conventional ITO.

1 is a cross-sectional view of an array substrate for a FPS type liquid crystal display device according to the prior art.
2 is a plan view of an array substrate for an AH-IPS type liquid crystal display device according to the present invention.
FIG. 3 is a cross-sectional view of an array substrate for an AH-IPS type liquid crystal display device taken along line III-III of FIG. 2.
4A to 4N are cross-sectional views illustrating a manufacturing process of an array substrate for an AH-IPS type liquid crystal display device according to the present invention.
FIG. 5 is a graph showing transmittance according to a width of a common electrode and a distance between common electrodes in an AH-IPS array substrate according to the present invention.
FIG. 6 is a graph showing etch rates when IZO compositions and ITOs are used in an array substrate for an AH-IPS type liquid crystal display device according to the present invention.
FIG. 7 is a graph illustrating the etching selectivity of the IZO composition and ITO in the AH-IPS type array substrate according to the present invention.

Hereinafter, an array substrate for an AH-IPS type liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view of an array substrate for an AH-IPS type liquid crystal display device according to the present invention.

FIG. 3 is a cross-sectional view of an array substrate for an AH-IPS type liquid crystal display device taken along line III-III of FIG. 2.

The array substrate for the AH-IPS type liquid crystal display device according to the present invention includes a plurality of gates extending in one direction on the substrate 101 and spaced in parallel to each other, as shown in FIGS. 2 and 3. Wiring 105a; A plurality of data lines (117c) intersecting the gate lines (105a) and defining pixel regions in the crossing regions; The thin film transistor T provided at the intersection of the gate line 105a and the data line 117c and includes a gate electrode 105c, an active layer 113a, a source electrode 117a, and a drain electrode 117b. It is configured to include.

Here, a transparent conductive layer formed of any one of a transparent conductive material including indium tin oxide (ITO) and indium zinc oxide (IZO) is formed on a lower surface of the gate wiring 105a and the gate electrode 105c extending from the gate wiring 105a. The pattern 103a is formed. In this case, the transparent conductive layer pattern 103a may be formed on the entire lower surface or a portion of the lower surface of the gate wiring 105a including the gate electrode 105c.

A large area of the transparent pixel electrode 103b is disposed on the front surface of the pixel area with a space spaced apart from the gate line 105a and the data line 117c. The gate insulating film 111 is disposed above the pixel electrode 103b. ) And a plurality of rod-shaped transparent common electrodes 125a are disposed to be spaced apart from each other by a predetermined distance therebetween. In this case, the plurality of common electrodes 125a may be formed of an indium zinc oxide (IZO) composition having an etch rate of several tens of times higher than that of indium tin oxide (ITO). In addition, the Indium Zinc Oxide (IZO) composition may include In ₂ O _3. (40-80 wt%) : And ZnO (20 ~ 60wt%) In 2 O 3 (ZnO) consisting of _2, In ₂ O ₃ (30 ~ 60 wt%): ZnO (30 ~ 55wt%): SnO 2 (5 ~ 15wt%) In 2 O 3 consisting of (ZnO) ₂ and SnO _2, In ₂ O ₃ (40-70 wt%) : In ₂ O ₃ (ZnO) ₃ composed of ZnO (30 to 60 wt%), In ₂ O ₃ (35 to 55 wt%): ZnO (40 to 65 wt%): SnO ₂ (1 to 10 wt%) In ₂ O ₃ (ZnO) ₃ SnO ₂ And In ₂ O ₃ (40 to 80 wt%): ZnO (5 to 20 wt%): Contains ITZO consisting of SnO ₂ (15 to 40 wt%). In particular, In ₂ O ₃ (40-80 wt%) : When In ₂ O ₃ (ZnO) ₂ composed of ZnO (20 to 60 wt%) is used, it has the best electric conduction property when forming a thin film among In ₂ O ₃ (ZnO) _k compositions. In addition, In ₂ O ₃ (30 to 60 wt%): ZnO (30 to 55 wt%): In ₂ O ₃ (ZnO) ₂ SnO ₂ composed of SnO ₂ (5 to 15 wt%), the strength and hardness of IZO Has increasing properties.

And In ₂ O ₃ (40-70 wt%) In the case of using In ₂ O ₃ (ZnO) ₃ composed of ZnO (30 to 60 wt%), the In ₂ O ₃ (ZnO) _k composition has the most excellent electrical conducting properties at the time of bulk formation.

Moreover, In ₂ O ₃ (35 to 55 wt%): ZnO (40 to 65 wt%): In ₂ O ₃ (ZnO) ₃ SnO ₂ composed of SnO ₂ (1 to 10 wt%), the strength and hardness of IZO Has increasing properties.

On the other hand, as an IZO composition, the target which has indium zinc oxide (IZO) as a main component and added 1 or more types at 1-15 weight% of the oxide which has a valency of 2-4 tetravalent is included.

In addition, the pixel electrode 103b is formed by the pixel electrode connection pattern 125b contacting the drain electrode 117b through the pixel electrode contact hole 123a formed in the passivation layer 123 and the gate insulating layer 111. It is electrically connected to the drain electrode 117b.

In addition, both ends of the plurality of rod-shaped common electrodes 125a are connected to a common electrode connection wiring (not shown) disposed in parallel with the data wiring 117c. In this case, the plurality of common electrodes 125a supply a reference voltage for driving the liquid crystal, that is, a common voltage to each pixel.

The pixel electrode 103b overlaps the plurality of common electrodes 125a in the pixel region with the gate insulating layer 111 and the passivation layer 123 therebetween to form a fringe field.

In this way, when a video signal is supplied to the pixel electrode 13b through the thin film transistor T, the common electrodes 125a supplied with the common voltage form a fringe field, thereby forming a thin film transistor substrate and a color filter substrate. Liquid crystal molecules arranged in the horizontal direction between (not shown) are rotated by the dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

As in the above configuration, by using a transparent conductive material added with a functional dopant, such as Sn, Ga, etc. to the IZO as a common electrode of the AH-IPS type liquid crystal display device, Etch rate is improved to enable the implementation of a fine electrode pattern, thereby improving the transmittance compared to the same thickness of ITO.

Therefore, in the case of using the transparent conductive material selected from the above-described IZO composition group instead of the ITO used when forming the common electrode, the etching rate is improved compared to the conventional ITO, thereby enabling the fine electrode pattern to be implemented, thereby The transmittance is improved compared to the thickness of ITO.

A method of manufacturing an array substrate for an AH-IPS type liquid crystal display device according to the present invention having the above configuration will be described with reference to FIGS. 4A to 4M.

4A to 4N are cross-sectional views illustrating a manufacturing process of an array substrate for an AH-IPS type liquid crystal display device according to the present invention.

As shown in FIG. 4A, a plurality of pixel areas including a switching area are defined on the transparent insulating substrate 101, and the first transparent conductive material layer 103 and the first transparent conductive material layer 103 are formed on the transparent insulating substrate 101. The conductive metal layer 105 is sequentially deposited by the sputtering method. Here, the first transparent conductive material layer 103 may be formed of any one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). In addition, the first conductive metal layer 205 may include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), or molybdenum. At least one selected from the group of conductive metals, including titanium (MoTi), copper / mortitanium (Cu / MoTi), is used.

Next, a photoresist having a high transmittance is coated on the first conductive metal layer 105 to form a first photosensitive film 107.

Subsequently, as illustrated in FIG. 4B, an exposure process is performed on the first photosensitive film 107 using the first diffraction mask 109 including the light blocking portion 109a, the transflective portion 109b, and the transmissive portion 109c. Proceed. In this case, the light blocking portion 109a of the first diffraction mask 109 is positioned above the first photoresist layer 107 corresponding to the gate electrode formation region, and the transflective portion 109b of the diffraction mask 109 is formed. It is located above the first photosensitive film 107 corresponding to the pixel electrode formation region. In addition to the first diffraction mask 109, a mask using a diffraction effect of light, for example, a half-tone mask or other mask may be used.

 Next, as shown in FIG. 4C, after the exposure process, the first photoresist layer 107 is selectively removed through the development process to form the gate forming region 107a and the pixel electrode forming region 107b. do. At this time, the gate formation region 107a maintains the thickness of the first photoresist film 107 because the light is not transmitted, but the pixel electrode formation region 107b is partially removed by transmitting a portion of the light. That is, the pixel electrode forming region 107b has a thickness thinner than that of the gate forming region 107a.

Subsequently, the first conductive metal layer 105 and the first transparent conductive material layer 103 are patterned using the gate forming region 107a and the pixel electrode forming region 107b of the first photoresist film as a gate wiring 105a. The gate electrode 105c and the pixel electrode 103b protruding from the gate wiring 105a are formed. In this case, the dummy conductive metal layer pattern 105b is also formed at the time of patterning the first conductive metal layer 105 and the first transparent conductive material layer 103. In addition, as illustrated in FIG. 2, the pixel electrode 103b is disposed with a space spaced apart from the gate line 105a and the data line 117c on the entire surface of the pixel area.

Next, as shown in FIG. 4D, the pixel electrode forming region 107b is formed along with a portion of the thickness of the gate forming region 107a on the gate wiring 105a and the gate electrode 105c through an ashing process. Remove it. In this case, an upper portion of the dummy conductive metal layer pattern 105b is exposed to the outside.

Subsequently, as shown in FIG. 4E, the exposed dummy conductive metal layer pattern 105b is removed using the gate forming region 107a, which is partially etched by an ashing process, as a blocking film, and then gate formation of the first photoresist film is performed. Remove area 107a. At this time, the transparent conductive material layer pattern 103a under the gate electrode 105c is left without being etched.

Next, as shown in FIG. 4F, after the remaining gate forming region 107a is removed, a gate made of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate including the pixel electrode 105b. An insulating layer 111 is formed, and an amorphous silicon layer (a-Si: H) 113 and an amorphous silicon layer (n + or p +) 115 containing impurities and a second conductive metal layer are formed on the gate insulating layer 111. (117) is laminated one by one. In this case, the amorphous silicon layer (a-Si: H) 213 and the amorphous silicon layer (n + or p +) 215 including impurities are deposited by a chemical vapor deposition method (CVD), and the The second conductive metal layer 117 is deposited by a sputtering method. Although the chemical vapor deposition method and the sputtering method are described only as the vapor deposition method here, other vapor deposition methods may be used as necessary. In this case, the second conductive metal layer 117 may include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), or molybdenum. At least one selected from the group of conductive metals including titanium (MoTi) and copper / mortium (Cu / MoTi) is used.

 Subsequently, as illustrated in FIG. 4G, a photoresist having high transmittance is coated on the second conductive metal layer 117 to form a second photosensitive layer 119.

Next, an exposure process is performed on the second photosensitive film 119 by using a diffraction mask 121 including the light blocking part 121a, the transflective part 121b, and the transmitting part 121c. In this case, the light blocking portion 121a of the diffraction mask 121 is positioned above the second photoresist layer 119 corresponding to the source and drain electrode formation regions, and the transflective portion 121b of the diffraction mask 121 is formed. The second photoresist layer 119 is positioned above the channel formation region of the thin film transistor. In addition to the second diffraction mask 121, a mask using a diffraction effect of light, for example, a half-tone mask or other mask may be used.

 Subsequently, as shown in FIG. 4H, the second photoresist layer 119 is etched through the exposure process and then the source and drain electrode formation region 119a and the channel formation region 119b are formed. . At this time, since the source and drain electrode forming region 119a is in a state where light is not transmitted, the thickness of the second photoresist layer 119 is maintained as it is, but the channel forming region 119b is partially transmitted to a predetermined thickness. Removed. That is, the channel forming region 119b has a thickness thinner than that of the source and drain electrode forming region 119a.

Next, the second conductive metal layer 117, the amorphous silicon layer 115 containing impurities and the amorphous silicon layer 113 are formed using the source and drain electrode forming regions 119a and the channel forming regions 119b as masks. By sequentially patterning, the active layer 113a and the ohmic contact layer 115a are formed on the gate insulating layer 111 corresponding to the gate electrode 105c.

Subsequently, as illustrated in 4i, the channel forming region 119b is completely removed along with a part of the thickness of the source and drain electrode forming region 119a through an ashing process. In this case, an upper surface of the second conductive metal layer 117 overlapping the channel region is exposed to the outside.

Next, as shown in FIG. 4J, the exposed portion of the second conductive metal layer 117 is etched using the source and drain electrode forming region 119a of the second photoresist film, in which the portion of the thickness is removed, as a mask. A source electrode 117a and a drain electrode 117b spaced apart from each other are formed together with the data wiring (not shown, see 117c of FIG. 2) perpendicular to the wiring 103a.

Subsequently, the ohmic contact layer 115a exposed between the source electrode 117a and the drain electrode 117b is also etched and spaced apart from each other. At this time, a channel region is formed in the active layer 113a under the etched ohmic contact layer 115a.

Next, as shown in FIG. 4K, the source and drain electrode forming regions 119a of the second photoresist film are completely removed, and then an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate to form a protective film 123. Subsequently, a third photoresist layer (not shown) is formed by applying a photo-resist having high transmittance on the passivation layer 123.

Subsequently, although not shown in the drawing, an exposure and development process is performed by a photolithography process technique using an exposure mask (not shown) to remove the third photoresist film (not shown) to form a third photoresist pattern (not shown). do.

Next, as shown in FIG. 4L, the protective layer 223 and the gate insulating layer 211 below are selectively etched using a third photoresist pattern (not shown) as a mask to expose the pixel electrode 103b. The pixel electrode contact hole 123a is formed. At this time, when the pixel electrode contact hole 123a is formed, the drain electrode 117b is also exposed.

Subsequently, as shown in FIG. 4M, the third photoresist layer pattern (not shown) is removed, and an IZO (Indium Zinc Oxide) composition target is used on the passivation layer 123 including the pixel electrode contact hole 123a. The second transparent conductive material layer 125 is deposited by DC magnetron sputtering.

At this time, the Indium Zinc Oxide (IZO) composition target is In ₂ O ₃ (40-80 wt%) : And ZnO (20 ~ 60wt%) In 2 O 3 (ZnO) consisting of _2, In ₂ O ₃ (30 ~ 60 wt%): ZnO (30 ~ 55wt%): SnO 2 (5 ~ 15wt%) In 2 O 3 consisting of (ZnO) ₂ and SnO _2, In ₂ O ₃ (40-70 wt%) : In ₂ O ₃ (ZnO) ₃ composed of ZnO (30 to 60 wt%), In ₂ O ₃ (35 to 55 wt%): ZnO (40 to 65 wt%): SnO ₂ (1 to 10 wt%) In ₂ O ₃ (ZnO) ₃ SnO ₂ And In ₂ O ₃ (40 to 80 wt%): ZnO (5 to 20 wt%): Contains ITZO consisting of SnO ₂ (15 to 40 wt%). In particular, In ₂ O ₃ (40-80 wt%) : When In ₂ O ₃ (ZnO) ₂ composed of ZnO (20 to 60 wt%) is used, it has the best electric conduction property when forming a thin film among In ₂ O ₃ (ZnO) _k compositions. In addition, In ₂ O ₃ (30 to 60 wt%): ZnO (30 to 55 wt%): In ₂ O ₃ (ZnO) ₂ SnO ₂ composed of SnO ₂ (5 to 15 wt%), the strength and hardness of IZO Has increasing properties.

And In ₂ O ₃ (40-70 wt%) In the case of using In ₂ O ₃ (ZnO) ₃ composed of ZnO (30 to 60 wt%), the In ₂ O ₃ (ZnO) _k composition has the most excellent electrical conducting properties at the time of bulk formation.

Moreover, In ₂ O ₃ (35 to 55 wt%): ZnO (40 to 65 wt%): In ₂ O ₃ (ZnO) ₃ SnO ₂ composed of SnO ₂ (1 to 10 wt%), the strength and hardness of IZO Has increasing properties.

On the other hand, as an IZO composition, the target which has indium zinc oxide (IZO) as a main component and added 1 or more types at 1-15 weight% of the oxide which has a valency of 2-4 tetravalent is included.

Although the present invention describes the case where the IZO composition is used when forming the common electrode used as the uppermost layer, the same applies to the case where the pixel electrode is formed instead of the common electrode as the uppermost layer.

Next, although not shown in the figure, a fourth photosensitive film (not shown) is formed by applying a high transmittance photo-resist on the second transparent conductive material layer 125.

Subsequently, although not shown, a fourth photoresist pattern (not shown) is formed by performing an exposure and development process by a photolithography process technique using an exposure mask (not shown) to remove the fourth photoresist layer (not shown). do.

Next, as shown in FIG. 4N, the second transparent conductive layer 125 is etched using the fourth photoresist pattern (not shown) as a mask to form the pixel electrode contact hole together with the plurality of common electrodes 125a. The pixel electrode connection pattern 125b electrically connected to the pixel electrode 103b is formed at the same time through 123a.

Subsequently, although not shown in the drawing, the fourth photosensitive film pattern (not shown) is removed to complete the manufacturing process of the array substrate for an H-IPS type liquid crystal display device according to the present invention.

Subsequently, although not shown in the drawing, the FPS type liquid crystal display device according to the present invention is manufactured by performing a process of filling a liquid crystal layer between the array substrate and the color filter substrate together with the color filter substrate manufacturing process.

FIG. 5 is a graph showing transmittance according to a width of a common electrode and a distance between common electrodes in an AH-IPS array substrate according to the present invention.

FIG. 6 is a graph showing etch rates when IZO compositions and ITOs are used in an array substrate for an AH-IPS type liquid crystal display device according to the present invention.

FIG. 7 is a graph illustrating the etching selectivity of the IZO composition and ITO in the AH-IPS type array substrate according to the present invention.

As shown in FIG. 5, since the transmission efficiency increases when the width w of the electrode is about 2.0 μm or less and the distance d between the electrodes is about 3.5 μm, the width w of the electrode is finely patterned accordingly. It is most important to do it.

In addition, as shown in FIG. 6, the etch rate shown in the case of using ITO and IZO as the common electrode forming material of the liquid crystal display may be known. In the case of using the IZO composition of the present invention, conventional ITO Rather than the case, it can be seen that the etching rate (etch rate) is improved several tens to hundreds of times.

7 illustrates a comparison of etching selectivity of ITO and IZO composition used as a common electrode forming material of a liquid crystal display device, which is greater than the case of using ITO when IZO compositions, ie, IZO, IGZO, and IGO, are used. It can be seen that the etching selectivity is large.

 Therefore, according to the present invention, instead of the conventional etch slow ITO, using a IZO (Indium Zinc Oxide) composition of a high-speed transparent conductive material as a common electrode of the AH-IPS type liquid crystal display device By using, the etching rate (etch rate) is improved to implement a fine electrode pattern, thereby improving the transmittance compared to the same thickness of ITO.

In particular, since the present invention uses an indium zinc oxide (IZO) composition, which is a transparent conductive material having an excellent etching rate compared to the conventional ITO, it is possible to realize a fine line width of the width of the common electrode and to provide a distance between the common electrodes. distance) is also adjustable, thereby improving the transmittance compared to using the conventional ITO.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

101: insulating substrate 103a: transparent conductive layer pattern
103b: pixel electrode 105a: gate wiring
105c: gate electrode 107: photosensitive film
109: first diffraction mask 111: gate insulating film
113a: active layer 115a: ohmic contact layer
117a: source electrode 117b: drain electrode
117c: data wiring 119: second photosensitive film
121: second diffraction mask 123: protective film
125a: common electrode 125b: pixel electrode connection pattern

Claims (9)

A gate wiring formed on one surface of the substrate in one direction;
A data line crossing the gate line to define a pixel area;
A thin film transistor formed at a point of intersection of the gate line and the data line;
A pixel electrode formed in the pixel region of the substrate;
A protective film formed on an entire surface of the substrate including the pixel electrode and the thin film transistor;
A plurality of common electrodes formed of an indium zinc oxide (IZO) composition, which is a transparent conductive material, on the passivation layer and spaced apart from each other; And
And a pixel electrode connection pattern electrically connecting the pixel electrode and the thin film transistor to each other. The method of claim 1, wherein the common electrode,
In ₂ O ₃ (40-80 wt%) : And ZnO (20 ~ 60wt%) In 2 O 3 (ZnO) consisting of _2, In ₂ O ₃ (30 ~ 60 wt%): ZnO (30 ~ 55wt%): SnO 2 (5 ~ 15wt%) and _{In 2 O 3 (ZnO) 2} SnO 2 consisting _{of, In 2 O 3 (40 ~} 70 wt%) : ZnO (30 ~ 60wt%) In 2 O 3 (ZnO) ₃ and consisting of, In ₂ O ₃ (35 to 55 wt%): ZnO (40 to 65 wt%): In ₂ O ₃ (ZnO) ₃ consisting of SnO ₂ (1 to 10 wt%) SnO ₂ and In ₂ O ₃ (40 to 80 wt%): ZnO (5 to 20 wt%): An array substrate for a liquid crystal display device comprising any one of IZO compositions comprising ITZO composed of SnO ₂ (15 to 40 wt%). The liquid crystal according to claim 1, wherein the IZO composition comprises a target containing indium zinc oxide (IZO) as a main component and at least one kind of oxide having a valence of 2 to 4 valences added at 1 to 15 wt%. Array board for display device. The array substrate of claim 1, wherein the pixel electrode connection pattern and the common electrode are formed of an IZO composition having the same material layer. Forming a gate wiring in one direction on one surface of a substrate;
A data line crossing the gate line to define a pixel area;
Forming a thin film transistor at an intersection of the gate line and the data line;
Forming a pixel electrode in the pixel region of the substrate;
Forming a protective film on an entire surface of the substrate including the pixel electrode and the thin film transistor; And
Forming a pixel electrode connection pattern electrically connecting the pixel electrode and the thin film transistor with a plurality of common electrodes spaced apart from each other by using an indium zinc oxide (IZO) composition, which is a transparent conductive material, on the passivation layer; Configured by
Method of manufacturing array substrate for liquid crystal display device. The method of claim 5, wherein the common electrode,
In ₂ O ₃ (40-80 wt%) : And ZnO (20 ~ 60wt%) In 2 O 3 (ZnO) consisting of _2, In ₂ O ₃ (30 ~ 60 wt%): ZnO (30 ~ 55wt%): SnO 2 (5 ~ 15wt%) and _{In 2 O 3 (ZnO) 2} SnO 2 consisting _{of, In 2 O 3 (40 ~} 70 wt%) : ZnO (30 ~ 60wt%) In 2 O 3 (ZnO) ₃ and consisting of, In ₂ O ₃ (35 to 55 wt%): ZnO (40 to 65 wt%): In ₂ O ₃ (ZnO) ₃ consisting of SnO ₂ (1 to 10 wt%) SnO ₂ and In ₂ O ₃ (40 to 80 wt%): ZnO (5 to 20 wt%): A method for manufacturing an array substrate for a liquid crystal display device, comprising any one of IZO compositions containing ITZO composed of SnO ₂ (15 to 40 wt%). The liquid crystal according to claim 5, wherein the IZO composition comprises a target containing indium zinc oxide (IZO) as a main component and at least one kind of oxide having a valence of 2 to 4 valences added at 1 to 15 wt%. Method of manufacturing array substrate for display device. The method of claim 5, wherein the pixel electrode connection pattern and the common electrode are formed of an IZO composition formed of the same material layer. 6. The method of claim 5, wherein the IZO composition is formed by forming a common electrode by DC magnetron sputtering.

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