KR20130006975A

KR20130006975A - Light emitting device and method for fabricating the same

Info

Publication number: KR20130006975A
Application number: KR1020110062689A
Authority: KR
Inventors: 박건; 김선모; 오충석; 황세광; 송호근; 원준호; 박지수
Original assignee: (주)세미머티리얼즈; 박건
Priority date: 2011-06-28
Filing date: 2011-06-28
Publication date: 2013-01-18

Abstract

The embodiment relates to a light emitting device and a method of manufacturing the light emitting device.
A light emitting device according to an embodiment includes a substrate; A first conductive semiconductor layer formed on the substrate; An active layer including an inclined side surface on the first conductivity type semiconductor layer; And a second conductivity type semiconductor layer formed on the active layer.

Description

LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME}

The embodiment relates to a light emitting device and a method of manufacturing the light emitting device.

Light Emitting Device (LED) is a semiconductor PN junction device that converts electrical energy into light energy, and is a light emitting semiconductor that emits current through a compound semiconductor terminal and emits light by combining electrons and holes in the vicinity of the PN junction or in the active layer. It is an emitting device.

According to the prior art, the LED is formed by epitaxially growing a gallium nitride (GaN) semiconductor layer on a sapphire substrate, and many dislocations are generated due to the crystal lattice difference between the sapphire substrate and gallium nitride, and the potential is non-emitting recombination. There is a problem in that the internal luminous efficiency of the light emitting device is reduced by acting as a defect that is a (non-radiative recombination) site.

In addition, according to the prior art, the multi-quantum well (MQW) constituting the active layer in the gallium nitride semiconductor layer formed on the sapphire substrate may be formed by a plurality of cycles of wells and barriers of InGaN / GaN. Due to the lattice mismatch and the difference in polar nature due to the lattice structure difference, a strong built-in electric field, or piezo-electric field, is applied to multi-quantum wells as the amount of In doping increases. An electric field is generated, and due to this effect, there is a problem in that a quantum-confined stark effect (QCSE) phenomenon in which recombination efficiency decreases due to spatial separation of electrons and holes occurs.

In addition, according to the prior art, the area from which the light emitted from the active layer is extracted to the outside is limited, which limits the light extraction efficiency.

Embodiments provide a light emitting device including a high quality light emitting structure and a method of manufacturing the same.

In addition, the embodiment is to provide a light emitting device and a method of manufacturing the same that can alleviate the piezo-electric field (phenzo-electric field) phenomenon in the active layer to increase the internal luminous efficiency.

In addition, in the prior art, the area of the active layer is limited to the area corresponding to the size of the chip, so that the ultimate increase in the area of the light emitting layer is limited, and the light extraction efficiency is limited. Therefore, the area of the light emitting layer is increased through the present embodiment. By providing a light emitting device and a method of manufacturing the light emitting efficiency is increased.

The light emitting device according to the embodiment includes a substrate; A first conductivity type semiconductor layer formed on the substrate; An electron storage layer including an inclined side surface on the first conductivity type semiconductor layer; An active layer formed on the electron storage layer; And a second conductivity type semiconductor layer formed on the active layer.

In addition, the manufacturing method of the light emitting device according to the embodiment comprises the steps of preparing a substrate; Forming a first conductivity type semiconductor layer on the substrate; Forming an electron storage layer including an inclined side surface on the first conductivity type semiconductor layer; Forming an active layer on the electron storage layer; And forming a second conductivity type semiconductor layer on the active layer.

According to the light emitting device and the manufacturing method of the light emitting device according to the embodiment, by implementing a high-quality light emitting device is blocked by the dislocation (dislociton) by forming an inclined side using a void (void) to increase the internal light emitting efficiency of the light emitting device Can be.

In addition, according to the embodiment, by forming the active layer on the inclined side, strain in the active layer can be alleviated, so that the piezo-electric field in the active layer can be alleviated. Accordingly, the quantum-confined stark effect (QCSE) phenomenon, in which the recombination efficiency decreases due to the spatial separation of electrons and holes, can be solved, thereby increasing the internal light emitting efficiency.

In addition, in the prior art, the area of the active layer is limited to the area corresponding to the chip size, so that the ultimate increase in the area of the light emitting layer is limited, thereby limiting the light extraction efficiency. By forming, the side surface area of the active layer is increased to increase the area of the light emitting layer, and also provide an escape path of the light generated in the active layer, thereby increasing the internal luminous efficiency and contributing to the increase of the external light extraction efficiency.

1 is a cross-sectional view of a light emitting device according to an embodiment.
2 to 6 are cross-sectional views of a method of manufacturing a light emitting device according to the embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

Embodiment of the present invention can be modified in various other forms, the scope of the present invention is not limited to the embodiments described below,

In addition, in the description of the embodiments, the shape and size of elements in the drawings may be exaggerated for clarity.

(Example)

1 is a cross-sectional view of a light emitting device 100 according to an embodiment.

The light emitting device 100 according to the embodiment includes a substrate 102, a first conductive semiconductor layer 112 formed on the substrate 102, and a side surface inclined on the first conductive semiconductor layer 112. An electron storage layer 105 including the active layer 114, an active layer 114 formed on the electrode storage layer 105, and a second conductive semiconductor layer 116 formed on the active layer 114. It may include.

According to the light emitting device according to the embodiment, the internal light emitting efficiency of the light emitting device can be increased by forming a high-quality light emitting device with a potential (dislociton) cut off by forming an inclined side surface using a void (void) in the active layer.

In an embodiment, the inclined side surface S may extend from a lower side to an upper side of the electron storage layer 105.

In addition, the electron storage layer 105 including the inclined side surface S may include a first electron storage layer 105a having a first void (not shown) interposed on the first conductivity-type semiconductor layer 112 ( 4) and an electron storage layer 105b (see FIG. 4) having a second void (not shown) interposed on the first electron storage layer 105a.

In addition, the electron storage layer 105 may be formed in a plurality of spaced apart in the lateral direction, the inclined side surface (S) may be interposed between the plurality of spaced apart electron storage layer in the horizontal direction.

In an embodiment, the active layer 114 may be thinly formed along the unevenness of the electron storage layer 105. For example, the active layer 114 having a thickness of about 20 to 80 nm is distributed on the unevenness of the electron storage layer 105 formed to a thickness of about 100 to 800 nm, and the unevenness is included to include the side inclined to the electron storage layer. As it grows, the active layer is deposited along the surface, thereby increasing the surface area of the active layer.

Accordingly, according to the embodiment, by forming the active layer on the inclined side surface, the side surface area of the active layer is increased to increase the area of the light emitting layer, and also provides an escape path of light generated in the active layer, thereby increasing the internal light emitting efficiency. On the other hand, it can contribute to the increase of external light extraction efficiency.

According to the embodiment, the active layer is formed on the electron storage layer including the V-shaped side to trap electrons and holes, so that the internal luminous efficiency is very high, and the light emitting area is high, thereby increasing the light extraction efficiency.

In addition, according to the light emitting device according to the embodiment, the internal light emitting efficiency of the light emitting device can be increased by forming a high-quality light emitting device is blocked by the dislocation (dislociton) by forming an inclined side using a void (void).

In addition, according to the embodiment, by forming the active layer on the inclined side, strain in the active layer can be alleviated, so that the piezo-electric field in the active layer can be alleviated.

An embodiment may include a buffer layer 104 on the substrate 102. For example, the buffer layer 104 may mitigate lattice mismatch between the substrate 102 and the light emitting structure 110. The material of the buffer layer 104 may be a Group III-V compound semiconductor such as GaN, InN, It may be formed of at least one of AlN, InGaN, AlGaN, InAlGaN, AlInN, but is not limited thereto.

In addition, the embodiment may include a light-transmitting ohmic layer 124 formed on the light emitting structure 110. The transmissive ohmic layer 124 may be formed on the light emitting structure to function as a carrier diffusion layer.

In addition, the embodiment may include a second pad electrode 132 and a first pad electrode 131 electrically connected to the first conductive semiconductor layer 112 on the light-transmitting ohmic layer 124.

According to the light emitting device according to the embodiment, the internal light emitting efficiency of the light emitting device can be increased by implementing a high quality light emitting device with dislocations blocked by forming an inclined side surface using a void.

In addition, in the prior art, the area of the active layer is limited to the area corresponding to the size of the chip, and thus the ultimate increase in the area of the light emitting layer is limited, thereby limiting the light extraction efficiency. By forming a side surface area of the active layer is increased to increase the light emitting layer area, and also provide an escape path (pathways) of light generated in the active layer to increase the internal luminous efficiency and contribute to the increase in the external light extraction efficiency.

Hereinafter, a method of manufacturing a light emitting device according to an embodiment will be described with reference to FIGS. 2 to 6.

First, as shown in FIG. 2, a substrate 102 is prepared, and a buffer layer 104 is formed on the substrate 102.

The substrate 102 may include an insulating substrate or a conductive substrate. For example, the substrate 102 may use at least one of sapphire (Al ₂ O ₃ ), silicon carbide (SiC), GaAs, GaN, ZnO, GaP, Ge, Ga ₂ 0 ₃ , but is not limited thereto. .

In an embodiment, the buffer layer 104 may be formed on the substrate 102. The buffer layer 104 may mitigate lattice mismatch between the substrate 102 and the light emitting structure 110. The material of the buffer layer 104 may be formed of at least one of Group III-V compound semiconductors, for example, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN, but is not limited thereto.

Next, as shown in FIG. 3, the first conductivity-type semiconductor layer 112 is formed on the substrate 102 or the buffer layer 104.

The first conductive semiconductor layer 112 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, GaP, AlGaP, InGaP, AlInGaP, InP, AlGaAs, InGaAs, and AlInGaAs. It is not limited.

The first conductive semiconductor layer 112 may form an N-type GaN layer using a chemical vapor deposition method (CVD), molecular beam epitaxy (MBE), or sputtering or hydroxide vapor phase epitaxy (HVPE). .

For example, the first conductive semiconductor layer 112 includes n-type impurities such as trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and silicon (Si) in the chamber. Silane gas (SiH ₄ ) to be injected may be formed.

Thereafter, an electron storage layer 105 including an inclined side surface S is formed on the first conductivity type semiconductor layer 112. For example, the electron storage layer 105 may be a gallium nitride semiconductor layer, but may be formed to a thickness of about 100 ~ 800nm, but is not limited thereto.

In an embodiment, the electron storage layer 105 having the inclined side may be formed at about 200 ° C. to 300 ° C. lower than a typical active layer growth temperature. For example, the electron storage layer 105 including the inclined side may be formed at about 700 ~ 900 ℃, but is not limited thereto.

According to the embodiment, the electron storage layer 105 may be formed through a plurality of void forming processes in the process of forming the electron storage layer 105 having an inclined side surface.

Specifically, when the first, second, and third voids are formed, the result is not three-stage voids, but the voids may form to form a V-shaped side, and the electron storage layer including the V-shaped side large and distinctly in μm. Can be formed.

For example, as shown in FIG. 4, the electron storage layer 105 including the inclined side surface S includes first electrons having a first void (not shown) interposed on the first conductivity type semiconductor layer 112. The storage layer 105a, the second electron storage layer 105b having a second void (not shown) interposed on the first electron storage layer 105a, and a third void (not shown) on the second electron storage layer 105c. It may include, but is not limited to, the third electronic storage layer 105c interposed therebetween.

For example, when the first electron storage layer 105a is grown at about 700 to 900 ° C. by a MOCVD method, a first void may be formed therebetween, and the first void may be formed in the first conductive semiconductor layer ( 112) may be located in the dislocation portion extending from the substrate during growth.

Thereafter, when the second electron storage layer 105b and the third electron storage layer 105c are continuously grown in situ, a second void and a third void tend to be generated at a position where the first void is formed. As a result of forming the first, second and third voids, the voids can be gathered instead of the three-stage voids to form a V-shaped inclined side, and form an electron storage layer including a V-shaped side that is large and distinctly in μm. can do.

A second void (not shown) interposed on the first electron storage layer 105a and a third void (not shown) interposed on the second electron storage layer 105b and the second electron storage layer 105c. The third electronic storage layer 105c may be included, but is not limited thereto.

In the prior art, the area of the active layer is limited to the area corresponding to the size of the chip, and thus the ultimate increase in the area of the light emitting layer is limited, so that the light extraction efficiency is limited. According to the embodiment, the active layer is formed on the inclined side. As a result, the side surface area of the active layer is increased to increase the area of the light emitting layer, and also provides an escape path of light generated in the active layer, thereby increasing the internal light emitting efficiency and contributing to the increase of the external light extraction efficiency.

Thereafter, an active layer 114 is formed on the electromagnetic field layer 105.

In addition, according to the embodiment, the active layer is formed on the electron storage layer including the V-shaped side to trap electrons and holes, so that the internal luminous efficiency is very high, the light emitting area is high, the light extraction efficiency can be increased.

The active layer 114 may be formed of at least one of a single quantum well structure, a multi quantum well structure (MQW), a quantum-wire structure, or a quantum dot structure.

For example, the active layer 114 may be formed of any one or more pair structures of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, but is not limited thereto.

In addition, the active layer 114 may be formed by randomly or patterning the two-dimensional plane as shown in Figure 4b. When the active layer 114 is patterned or formed in a random form, the surface area of the active layer is significantly increased, and as the area of the light emitting layer is increased, the internal light emission efficiency is increased and the escape path of the emitted light is expanded to increase the external light extraction efficiency. Can be.

The active layer 114 may be formed by injecting trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn) to form a multi-quantum well structure. no.

Thereafter, a second conductive semiconductor layer 116 is formed on the active layer 114.

The second conductive type semiconductor layer 116 is a second conductive type dopant is doped III-V compound semiconductor, for example _{-5, In x Al y Ga 1 -x-} y N (0≤x≤1, 0≤y≤ And 1, 0 ≦ x + y ≦ 1). When the second conductivity type semiconductor layer 116 is a P type semiconductor layer, the second conductivity type dopant may include Mg, Zn, Ca, Sr, Ba, or the like as a P type dopant.

The second conductive semiconductor layer 116 is injected with a material containing p-type impurities such as trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and magnesium (Mg) in the chamber. But may be formed, but is not limited thereto.

Next, as shown in FIG. 5, a light transmitting ohmic layer 124 is formed on the light emitting structure 110. The translucent ohmic layer 124 may be formed on the light emitting structure 110 to function as a carrier diffusion layer.

For example, the translucent ohmic layer 124 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), and GZO (GZO). gallium zinc oxide), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), IZON (IZO Nitride), ZnO, AGZO (Al-Ga ZnO), IGZO (In-Ga) ZnO), IrOx, RuOx, NiO and the like, and may be formed, but are not limited to these materials.

Next, as shown in FIG. 6, after removing a portion of the light emitting structure 110, the second pad electrode 132 is electrically connected to the first conductive semiconductor layer 112 on the light-transmitting ohmic layer 124. One pad electrode 131 may be formed.

The first pad electrode 131 may include Ti / Au, and the second pad electrode 132 may include Ni / Au, but is not limited thereto.

Although the embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above.

Claims

Board;
A first conductive semiconductor layer formed on the substrate;
An electron storage layer including an inclined side surface on the first conductivity type semiconductor layer;
An active layer formed on the electron storage layer;
And a second conductivity type semiconductor layer formed on the active layer.

The method according to claim 1,
Wherein,
A light emitting device formed on the upper surface of the electron storage layer.

The method according to claim 1,
The electron storage layer including the inclined side,
A first electron storage layer having a first void interposed on the first conductive semiconductor layer; And
And a second electron storage layer having a second void interposed on the first electron storage layer.

The method according to claim 1,
The electron storage layer,
And a plurality of spaced apart in the lateral direction, wherein the inclined side is interposed between the plurality of electron storage layers spaced in the horizontal direction.

Preparing a substrate;
Forming a first conductivity type semiconductor layer on the substrate;
Forming an electron storage layer including an inclined side surface on the first conductivity type semiconductor layer;
Forming an active layer on the electron storage layer; And
Forming a second conductive semiconductor layer on the active layer; manufacturing method of a light emitting device comprising a.

6. The method of claim 5,
Wherein,
The manufacturing method of the light emitting device is formed on the upper surface of the electron storage layer.

6. The method of claim 5,
Forming the total storage layer comprising the inclined side,
Forming a first preservation layer having a first void interposed on the first conductivity type semiconductor layer; And
Forming a second preservation layer having a second void interposed thereon on the first preservation layer.