KR20130001071A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A liquid crystal display and a manufacturing method thereof are provided to form a concavo-convex region on the lower part of a pixel electrode, thereby reducing the gap between the pixel electrode and a common electrode and increasing the storage capacity between the common electrode and the pixel electrode. CONSTITUTION: A pixel electrode(160) is formed on a second gate insulating layer(140b) which includes a stepped portion(A) and a groove portion(B). A second passivation layer(171) includes a concavo-convex structure corresponding to the stepped portion and the groove portion of the second gate insulating layer on the pixel electrode. A common electrode(183) corresponds to the groove portion between the stepped portions of the second gate insulating layer. The common electrode is formed on the second passivation layer.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a liquid crystal display device and a method of manufacturing the same, which can reduce power consumption.

Liquid crystal display devices (liquid crystal display device) due to the characteristics such as light weight, thin, low power consumption driving, the application range is gradually increasing. According to this trend, the liquid crystal display device is used in office automation equipment, audio / video equipment, and the like.

The liquid crystal display displays an image by changing an electrical signal into visual information by using a property in which light transmittance of a liquid crystal, which is an intermediate state material of a crystal, is changed to a liquid according to an applied voltage. A typical liquid crystal display device is composed of two substrates provided with electrodes and a liquid crystal layer interposed between the two substrates. Such a liquid crystal display device is lighter in weight, smaller in volume, and operates with less power than other liquid crystal display devices having the same screen size.

The liquid crystal display device displays an image because each pixel of the liquid crystal display panel on the front side selectively transmits the light generated from the light source on the rear side as a kind of optical switch. That is, the conventional cathode ray tube (CRT) controls the brightness by adjusting the intensity of the electron beam, whereas the LCD displays the screen by controlling the intensity of light generated from the light source.

In the liquid crystal display panel of the liquid crystal display device as described above, the color filter substrate (upper substrate) on which the color filter is formed and the thin film transistor substrate (lower substrate) on which the thin film transistor (TFT) is formed are bonded together with the liquid crystal layer interposed therebetween. Consists of a structure.

In a thin film transistor substrate of a general liquid crystal display panel, a gate line and a data line cross each other, and a thin film transistor (TFT) is formed at an intersection of the gate line and the data line.

The thin film transistor includes a gate electrode and a source / drain electrode with a gate insulating layer interposed therebetween, and the drain electrode is electrically connected to the pixel electrode.

A protective layer is formed on the gate insulating film including the source / drain electrodes and the pixel electrode, and a common electrode wiring and a common electrode pattern are formed on the protective layer.

As described above, the common electrode wiring is formed on the gate line and the data line and the common electrode pattern is formed on the pixel electrode in the thin film transistor substrate included in the general transverse electric field type liquid crystal display device.

However, a general liquid crystal display device has a problem in that the parasitic capacitance is formed between the gate line, the data line, and the common electrode wiring to generate vertical crosstalk, thereby degrading image quality.

In addition, in the general liquid crystal display, when the protective layer is designed to have a large thickness, parasitic capacitance may be reduced, but there is a problem in that power consumption increases due to a decrease in storage capacity due to an increase in the distance between the pixel electrode and the common electrode pattern.

Here, in the WVGA class high resolution model, the size of the pixel may be reduced, which may greatly reduce the storage capacity between the pixel electrode and the common electrode pattern.

An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can reduce power consumption by improving the response speed of liquid crystals.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a gate line and a data line crossing each other to define a pixel area, and a gate electrode and a gate insulating layer, a semiconductor layer, a source, A thin film transistor having a drain electrode, a pixel electrode electrically connected to the drain electrode of the thin film transistor, a first protective layer formed on the thin film transistor, the gate line and the data line, and a region corresponding to the pixel electrode A second protective layer having a thickness smaller than the first protective layer, and a common voltage line and a common electrode formed on the first and second protective layers, respectively, wherein the gate insulating layer includes a plurality of stepped portions and A groove part is provided.

A method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention includes forming a gate electrode, a gate line, and a gate pad on a base substrate, and on the base substrate including the gate electrode, the gate line, and the gate pad. Forming a gate insulating film having a plurality of stepped portions and groove portions in the semiconductor layer, sequentially forming a semiconductor pattern and a pixel electrode on the gate insulating film, and source and drain electrodes on the gate insulating film including the semiconductor pattern And forming a data line, forming a first passivation layer corresponding to the data line, forming a second passivation layer on the pixel electrode, and a common voltage on each of the first and second passivation layers. Forming a wiring and a common electrode, wherein the gate insulating film is coated with an insulating material on the base substrate. The method may further include forming the plurality of stepped portions and the groove portions by patterning the photo processes.

According to an exemplary embodiment of the present invention, a liquid crystal display and a method of manufacturing the same may reduce the gap between the pixel electrode and the common electrode formed on the uneven portion to increase the storage capacity Cst between the pixel electrode and the common electrode. have.

In addition, the present invention reduces the distance between the pixel electrode and the common electrode, so that even if the same driving voltage is applied between the pixel electrode and the common electrode, the effective voltage between the pixel electrode and the common electrode is increased so that the use of liquid crystal having a low dielectric constant is avoided. You can do that.

In addition, the present invention can reduce the power consumption by improving the response speed of the liquid crystal using a liquid crystal having a low dielectric constant.

1 is a plan view illustrating unit pixels of a thin film transistor substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate cut along lines II through II 'of FIG. 1.
3A to 3I are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
4 is a cross-sectional view illustrating a thin film transistor substrate according to another exemplary embodiment of the present invention.
5 is a view showing a relationship between voltage and transmittance in a conventional liquid crystal display device and a liquid crystal display device of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate cut along lines I to I 'and II to II' of FIG. 1. to be.

1 and 2, in the thin film transistor substrate according to the exemplary embodiment of the present invention, a plurality of gate lines 110 and a plurality of data lines 120 cross each other to define a pixel region, and the gate A thin film transistor (TFT) 150 for driving the liquid crystal cell is formed at the intersection of the line 110 and the data line 120.

Although not shown in the drawing, a gate pad electrically connected to the gate line 110 is formed at one side of the gate line 110, and a data pad electrically connected to the data line 120 is formed at one side of the data line 120. do.

The thin film transistor 150 provided in the pixel region includes a gate electrode 151 formed on the base substrate 130, a first gate insulating layer 140a formed on the gate electrode 151, and the base substrate 130. And a semiconductor pattern 153 formed on the first gate insulating layer 140a and source / drain electrodes 155 and 157 formed on the semiconductor pattern 153.

The first passivation layer 170 is formed on the first gate insulating layer 140a including the source / drain electrodes 155 and 157, and the common electrode wiring 181 is formed on the first passivation layer 170. .

The drain electrode 157 of the thin film transistor 150 is electrically connected to the pixel electrode 160 of the pixel region.

The display area in which an image is displayed among the pixel areas includes a base substrate 130, a second gate insulating layer 140b formed on the base substrate 130, and a pixel electrode formed on the second gate insulating layer 140b ( 160, a second passivation layer 171 formed on the pixel electrode 160, and a common electrode 183 formed on the second passivation layer 171.

The common electrode 183 may be electrically connected to the common electrode wiring 181.

A second passivation layer having a different thickness on a portion corresponding to the pixel electrode 160 and a portion corresponding to the data line 120 through a photolithography process using a half tone mask on the pixel electrode 160. 171 is formed.

The second gate insulating layer 140b together with the first gate insulating layer 140a forms a gate insulating layer 140.

The second gate insulating layer 140b includes a step portion A and a groove portion B formed between the step portion A. FIG. The second gate insulating layer 140b including the step portion A and the groove portion B is formed through a photo process using a mask.

The pixel electrode 160 is formed on the second gate insulating layer 140b having the stepped portion A and the groove B.

The second passivation layer 171 formed on the pixel electrode 160 may also include an uneven structure corresponding to the stepped portion A and the groove portion B of the second gate insulating layer 140b.

In this case, the common electrode 183 is formed on the second passivation layer 183 to correspond to the groove B between the stepped portions A of the second gate insulating layer 140b.

Therefore, a gap between the pixel electrode 160 formed on the stepped portion A of the second gate insulating layer 140b and the common electrode 183 formed on the second protective layer 183 to correspond to the groove B. Will be reduced. As a result, the storage capacity between the common electrode 183 and the pixel electrode 160 increases.

When the gap between the common electrode 183 and the pixel electrode 160 decreases, the level of the voltage provided to the common electrode 183 and the pixel electrode 160 is reduced, so that the common electrode 183 and the pixel are the same as before. The liquid crystal located between the electrodes 160 can be driven.

As described above, the present invention may reduce power consumption by reducing the level of the voltage provided to the common electrode 183 and the pixel electrode 160, thereby reducing power consumption.

In addition, since the gap between the common electrode 183 and the pixel electrode 160 is reduced even when the liquid crystal having a low dielectric constant (or rotational viscosity) is used, the same driving voltage as the conventional drive voltage is the common electrode 183 and the pixel electrode. Even if it is provided at 160, the liquid crystal having a low dielectric constant can be sufficiently driven.

In this case, since the liquid crystal having a low dielectric constant has a low rotational viscosity, the response speed of the liquid crystal may be improved.

Therefore, the present invention can improve the response speed of the liquid crystal by using the liquid crystal having a low dielectric constant.

3A to 3I are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, the gate electrode 151 is formed through a photo process using a mask by depositing a metal layer on the base substrate 130.

Here, the metal layer may be a single metal such as aluminum (Al), aluminum alloy (AlNd), tungsten (W), chromium (Cr), molybdenum (Mo), or aluminum (Al) / chromium (Cr) (or phybdenum (Mo)). One or more metals selected from the group of conductive metals, and the like.

Although not shown in the drawing, the gate electrode 151 is formed on the base substrate 130 and the gate line and the gate pad are simultaneously formed.

Referring to FIG. 3B, a gate insulating layer 140 is formed on the base substrate 130 including the gate electrode 151. The gate insulating layer 140 may be formed of silicon oxide (SiO 2) or silicon nitride (SiN x).

Next, a photo process using a mask is performed to form a second gate insulating layer 140b having a stepped portion A and a groove portion B, as shown in FIG. 3C.

As shown in FIG. 3D, a semiconductor layer is formed on the base substrate 130 on which the gate insulating layer 140 is formed, and a semiconductor pattern 153 corresponding to the gate electrode 151 is formed through a photo process using a mask. do.

Referring to FIG. 3E, a metal layer is formed on the base substrate 130 on which the semiconductor pattern 153 is formed, and the pixel electrode 160 is formed in the pixel region through a photo process using a mask.

The pixel electrode 160 is formed on the second gate insulating layer 140b having the stepped portion A and the groove B.

Referring to FIG. 3F, a metal layer is formed on the base substrate 130 on which the pixel electrode 160 is formed, and source and drain electrodes 155 and 157 are formed on the semiconductor pattern 153 through a photo process using a mask. The data line 120 is formed around the pixel area.

3G and 3H, a predetermined thickness of protection is performed on the base substrate 130 including the semiconductor pattern 153, the source and drain electrodes 155 and 157, the data line 120, and the pixel electrode 160. Layer 170 is stacked. Subsequently, a second passivation layer 171 is formed in a region corresponding to the pixel electrode 160 by a photo process using a halftone mask.

The second passivation layer 171 is a region corresponding to the pixel electrode 160 and has a smaller thickness than the first passivation layer 170 formed in a region not corresponding to the pixel electrode 160.

The second passivation layer 171 is formed thicker than the region corresponding to the pixel electrode 160 in the region corresponding to the data line 120.

This is to maintain a constant capacitance between the data line 120 and the common electrode wiring described later.

Although not shown in the drawing, a contact hole may be formed in the gate pad and the data pad at the same time as the second protective layer 171 is formed. In addition, a second protective layer 171 may be formed and a contact hole for connecting the drain electrode 157 and the pixel electrode 160 may be formed.

Referring to FIG. 3I, a metal layer is formed on the first and second passivation layers 170 and 171, and a photo process using a mask is performed on a region corresponding to the common electrode wiring 181 and the pixel electrode 160. The common electrode 183 is formed.

In this case, the common electrode 183 is formed to correspond to the groove portion B of the second gate insulating layer 140b.

Thus, the gap between the pixel electrode 160 and the common electrode 183 is reduced and the storage capacity is increased.

In addition, when the gap between the common electrode 183 and the pixel electrode 160 decreases, the common electrode 183 is reduced in the same manner as before by reducing the level of the voltage provided to the common electrode 183 and the pixel electrode 160. And the liquid crystal positioned between the pixel electrode 160 can be driven.

As described above, the present invention may reduce power consumption by reducing the level of the voltage provided to the common electrode 183 and the pixel electrode 160, thereby reducing power consumption.

In addition, since the gap between the common electrode 183 and the pixel electrode 160 is reduced even when the liquid crystal having a low dielectric constant (or rotational viscosity) is used, the same driving voltage as the conventional drive voltage is the common electrode 183 and the pixel electrode. Even if it is provided at 160, the liquid crystal having a low dielectric constant can be sufficiently driven.

Accordingly, the present invention can improve the response speed of the liquid crystal by using a liquid crystal having a low dielectric constant by reducing the gap between the pixel electrode 160 and the common electrode pattern 183.

4 is a cross-sectional view illustrating a thin film transistor substrate according to another exemplary embodiment of the present invention.

As shown in FIG. 4, a thin film transistor substrate according to another exemplary embodiment of the present invention may include a gate line (110 of FIG. 1) and a data line 120 intersecting vertically, and a gate line (110 of FIG. 1). And a thin film transistor 150 formed at an intersection of the data line 120.

The thin film transistor 150 includes a gate electrode 151 formed on the base substrate 130, a gate insulating film 240 formed on the gate electrode 151 and the base substrate 130, and the gate insulating film 240. And a semiconductor pattern 153 formed on the semiconductor pattern 153 and source / drain electrodes 155 and 157 formed on the semiconductor pattern 153.

The first passivation layer 170 is formed on the gate insulating layer 240 including the source / drain electrodes 155 and 157, and the common electrode wiring 181 is formed on the first passivation layer 170.

In addition, the thin film transistor substrate according to another embodiment of the present invention is a gate insulating layer 240 formed on the base substrate 130, a plurality of stepped portion 300 and the step difference formed on the gate insulating layer 240 A pixel electrode 260 is formed on the unit 300 and electrically connected to the drain electrode 157 of the thin film transistor 150.

The stepped part 300 may be made of an organic insulating material to improve the bonding force between the base substrate 130 and the gate insulating layer 240.

The stepped part 300 is coated with an organic insulating material, for example, photo acryl or benzocyclobutene (BCB) on the base substrate 130 and patterned through a photo process using a mask to form the gate insulating layer ( 240).

A second passivation layer 271 having a thickness different from that of the first passivation layer 170 is formed on the pixel electrode 260, and a common electrode 283 is formed on the second passivation layer 271.

The common electrode 283 may be electrically connected to the common electrode wiring 181.

In this case, the common electrode 283 is formed on the second protective layer 271 so as to correspond to the groove provided between the stepped portions 300.

Therefore, the distance between the pixel electrode 260 formed on the stepped portion 300 and the common electrode 283 formed on the second passivation layer 271 corresponding to the groove portion is reduced. As a result, the storage capacity between the common electrode 283 and the pixel electrode 260 increases.

When the gap between the common electrode 283 and the pixel electrode 260 decreases, the level of the voltage provided to the common electrode 283 and the pixel electrode 260 is reduced, so that the common electrode 283 and the pixel are the same as before. The liquid crystal located between the electrodes 260 can be driven.

As described above, according to the present invention, power consumption may be reduced because the liquid crystal is driven by reducing the level of the voltage provided to the common electrode 283 and the pixel electrode 260.

In addition, since the distance between the common electrode 283 and the pixel electrode 260 is reduced even when the liquid crystal having a low dielectric constant (or rotational viscosity) is used, the same driving voltage as the conventional drive voltage is applied to the common electrode 283 and the pixel electrode. Even if it is provided at 260, the liquid crystal having a low dielectric constant can be sufficiently driven.

In this case, since the liquid crystal having a low dielectric constant has a low rotational viscosity, the response speed of the liquid crystal may be improved.

Therefore, the present invention can improve the response speed of the liquid crystal by using the liquid crystal having a low dielectric constant.

5 is a view showing a relationship between voltage and transmittance in a conventional liquid crystal display device and a liquid crystal display device of the present invention.

Referring to FIG. 5, the conventional liquid crystal display has a transmittance of 80 when the driving voltage applied between the pixel electrode and the common electrode is 4V.

In contrast, the liquid crystal display device 1 of the present invention having the step portion and the groove portion on the gate insulating layer and the thickness of the protective layer being the same as the conventional liquid crystal display device has a transmittance of 95 when the driving voltage is 4V.

In addition, the liquid crystal display device 2 of the present invention having a stepped portion and a groove portion on the gate insulating layer and having a thickness of the protective layer thinner than a conventional liquid crystal display device has a transmittance of 100 when the driving voltage is 4V.

As described above, when the thickness of the passivation layer is reduced on the gate insulating layer and the thickness of the protective layer is reduced, the distance between the pixel electrode and the common electrode can be reduced, so that the same driving voltage as in the conventional liquid crystal display device is applied. Permeate oil can be obtained.

110: gate line 120: data line
130: base substrate 140, 240: gate insulating layer
140a: first gate insulating layer 140b: second gate insulating layer
150: thin film transistor 151: gate electrode
153: semiconductor pattern 155: source electrode
157: drain electrode 160, 260: pixel electrode
170: first protective layer 171, 271: second protective layer
181: common voltage wiring 183, 283: common electrode
300: step part

Claims (12)

A gate line and a data line crossing each other to define a pixel area;
A thin film transistor formed at an intersection of the gate line and the data line and having a gate electrode, a gate insulating layer, a semiconductor layer, a source and a drain electrode;
A pixel electrode electrically connected to the drain electrode of the thin film transistor;
A first passivation layer formed on the thin film transistor, the gate line and the data line;
A second protective layer formed in a region corresponding to the pixel electrode and having a thickness smaller than that of the first protective layer; And
And a common voltage line and a common electrode formed on the first and second protective layers, respectively.
The gate insulating layer includes a plurality of stepped portions and grooves. The method according to claim 1,
And the common electrode is formed on the second passivation layer so as to correspond to the groove portion of the gate insulating layer. The method according to claim 1,
And the common voltage line and the common electrode are electrically connected to each other. The method according to claim 1,
And the pixel electrode is formed on the gate insulating layer to correspond to the plurality of stepped portions and the groove portion. The method according to claim 1,
And the first and second protective layers are formed on the same layer. The method according to claim 1,
And the second protective layer includes an uneven structure corresponding to a plurality of stepped portions and groove portions of the gate insulating layer. Forming a gate electrode, a gate line, and a gate pad on the base substrate;
Forming a gate insulating layer having a plurality of stepped portions and grooves on the base substrate including the gate electrode, the gate line, and the gate pad;
Sequentially forming a semiconductor pattern and a pixel electrode on the gate insulating layer;
Forming source and drain electrodes and a data line on the gate insulating layer including the semiconductor pattern;
Forming a first passivation layer corresponding to the data line and simultaneously forming a second passivation layer on the pixel electrode; And
And forming a common voltage line and a common electrode in each of the first and second protective layers.
And forming the plurality of stepped portions and the groove portions by applying an insulating material on the base substrate and patterning the same through a photo process. The method of claim 7, wherein
And the common electrode is formed on the second passivation layer so as to correspond to a groove portion of the gate insulating layer. The method of claim 7, wherein
And the common voltage line and the common electrode are electrically connected to each other. The method of claim 7, wherein
And the pixel electrode is formed on the gate insulating layer to correspond to the plurality of stepped portions and the groove portion. The method of claim 7, wherein
And the first and second protective layers are formed on the same layer. The method of claim 7, wherein
And the second protective layer includes a concave-convex structure corresponding to a plurality of stepped portions and grooves of the gate insulating layer.

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