KR20120134265A - Method of manufacturing chip-embedded printed circuit board - Google Patents

Method of manufacturing chip-embedded printed circuit board Download PDF

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Publication number
KR20120134265A
KR20120134265A KR1020110053055A KR20110053055A KR20120134265A KR 20120134265 A KR20120134265 A KR 20120134265A KR 1020110053055 A KR1020110053055 A KR 1020110053055A KR 20110053055 A KR20110053055 A KR 20110053055A KR 20120134265 A KR20120134265 A KR 20120134265A
Authority
KR
South Korea
Prior art keywords
copper foil
identifier
circuit board
printed circuit
inner layer
Prior art date
Application number
KR1020110053055A
Other languages
Korean (ko)
Inventor
박재현
김기훈
Original Assignee
아페리오(주)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아페리오(주) filed Critical 아페리오(주)
Priority to KR1020110053055A priority Critical patent/KR20120134265A/en
Publication of KR20120134265A publication Critical patent/KR20120134265A/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4697Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936Marks, inscriptions, etc. for information

Abstract

The present invention is characterized by stamping an identifier for distinguishing the strip from the panel by using a laser direct image (LDI) equipment in the outer edge of the strip in the step of forming a copper foil circuit of the inner layer containing the component. In the step of forming an outer layer by laminating an insulating layer such as a prepreg (PREPREG) on the inner layer and removing the outer layer copper foil corresponding to the portion where the identifier is imprinted, the inner layer is imprinted on the inner layer through a translucent insulating layer. Identified identifiers can be checked. In addition, even after the final application of the solder resist, by removing the solder resist of the portion corresponding to the stamped identifier site and open, the identifier stamped on the inner layer can be confirmed even after the final product is completed. In addition, even if the above-described open process is omitted, using the X-ray equipment, the imprinted identifier of the inner layer can be confirmed.

Description

Manufacturing method of component embedded printed circuit board {METHOD OF MANUFACTURING CHIP-EMBEDDED PRINTED CIRCUIT BOARD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed circuit board having embedded components, and more particularly, to a method for manufacturing a printed circuit board for tracking components embedded in a printed circuit board.

Recently, an embedded printed circuit board (PCB) technology for manufacturing an active element such as a semiconductor chip in a printed circuit board has been generalized. The printed circuit board according to the present invention may include various active devices and passive devices including semiconductor chips, which will be collectively referred to as components.

If the part is embedded in the board, the size of the electronic part is reduced, which helps to reduce the size and weight of the electronic device, and can remove the parasitic elements, thereby increasing the operating frequency of the circuit, as well as causing external electromagnetic waves. It has the advantage of blocking the effects of.

After the printed circuit board is manufactured and completed, a test operation is usually performed to cover a defect such as an electrical open or a short circuit by performing a bare board test (BBT) process. In the case of a component-embedded printed circuit board, Since stress should be avoided as much as possible, it is not easy to conduct test inspections after manufacturing.

Therefore, for the component printed circuit board, it is necessary to determine whether there is a defect every time the unit process passes in the manufacturing stage, and for a unit that has been determined to be defective, a unit is produced when the process is completed. You should be able to track your perceptions. Hereinafter, in describing a method of manufacturing a printed circuit board according to the present invention, one panel is composed of a plurality of strips, and one strip is composed of a plurality of units. Once the process is complete, each unit becomes a product.

Accordingly, an object of the present invention is to provide a method for manufacturing a printed circuit board that can trace back a defective unit of a component embedded printed circuit board.

In order to achieve the above object, the method of manufacturing a printed circuit board according to the present invention is characterized in that the panel and the strip to distinguish from each other. The present invention is characterized by stamping an identifier for distinguishing the strip from the panel by using a laser direct image (LDI) equipment in the outer edge of the strip in the step of forming a copper foil circuit of the inner layer containing the component. Subsequently, in the step of forming an outer layer by laminating an insulating layer such as a prepreg (PREPREG) and copper foil on the inner layer, when the outer layer copper foil corresponding to the portion where the identifier is imprinted is removed and opened, the inner layer is formed through the translucent insulating layer. It is possible to check the identifier imprinted on the. In addition, even after the final application of the solder resist, by removing the solder resist of the portion corresponding to the stamped identifier site and open, the identifier stamped on the inner layer can be confirmed even after the final product is completed. In addition, even if the above-described open process is omitted, using the X-ray equipment, the imprinted identifier of the inner layer can be confirmed.

In the method for manufacturing a component embedded printed circuit board according to the present invention, since each panel as well as strips can be managed separately during the board manufacturing process step, a defective unit map in each unit process can be created to complete the product. This has the advantage of being able to trace back the cause of the failure.

1A to 1D are views illustrating a process of manufacturing a component embedded printed circuit board according to the present invention.

The present invention provides a method for manufacturing a component-embedded printed circuit board, comprising: (a) mounting a component on a second copper foil and laminating the first insulating layer and the first copper foil so that the first insulating layer surrounds the component. Forming an inner layer; (b) forming an identifier on the first copper foil; And (c) laminating a second insulating layer and a third copper foil on the first copper foil, laminating a third insulating layer and a fourth copper foil on the second copper foil, and forming an outer layer by laminating. Provided is a substrate manufacturing method.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are views illustrating a process of manufacturing a component embedded printed circuit board according to the present invention.

Referring to Figure 1A, there is shown an inner layer in which component 300 is embedded. The first copper foil 200 and the second copper foil 210 are formed above and below the component 300, and the first insulating layer 100 is interposed between the components 300 to surround the component 300. In addition, the component 300 may be firmly attached onto the second copper foil 210 through an insulator 400 such as an adhesive, and may form a circuit by connecting the electric terminal of the component 300 and the second copper foil 210 to each other. .

The method of manufacturing the inner layer of FIG. 1A is mounted on the second copper foil 210 by using an adhesive, and the resin-based first insulating layer 100 and the first copper foil 200 such as prepreg. ) Can be formed by laminating and laminating.

Referring to FIG. 1B, the present invention is characterized by marking an identifier for distinguishing a panel and a strip on the first copper foil 200 after fabricating an inner layer. In Fig. 1B, identifiers are stamped on the plurality of strips constituting the panel as indicated by " A " The method of marking an identifier may write a panel number and a strip number directly on the first copper foil using laser direct image (LDI) equipment. In another embodiment of the present invention, the identifier may be generated by including the identifier in the circuit pattern mask during the exposure etching of the first copper foil 200 according to the circuit pattern. Although FIG. 1B illustrates that an identifier is formed on the first copper foil 200, an identifier may be formed on the second copper foil 210.

The right side of FIG. 1B illustrates a plan view of the left "A" region. Looking at the top view shown in FIG. 1B, panel number 3 and strip number 1 are engraved on the first copper foil 200.

Referring to Fig. 1C, an outer layer is formed by laminating an insulating layer such as prepreg and copper foil on an inner layer having an identifier stamped thereon. In FIG. 1C, the insulating layer laminated on the first copper foil 200 is referred to as the second insulating layer 110, and the copper foil thereon is referred to as a third copper foil 220. In addition, the insulating layer laminated under the 2nd copper foil 210 is made into the 3rd insulating layer 120, and the copper foil on it is called the 4th copper foil 230. FIG.

According to a preferred embodiment of the present invention, as shown in " B " in Fig. 1C, the semi-transparent agent is opened by opening the third copper foil 220 on the portion of the first copper foil 200 with the identifier imprinted thereon. The identifier may be identified through the second insulating layer 110. At this time, as another embodiment of the present invention, if there is an X-ray see-through equipment, it is of course possible to check the identifier without opening the third copper foil 220.

Finally, Figure 1d is a view showing a step of applying the solder resist 500, the second resist layer semi-transparent by opening the solder resist 500 on the portion of the first copper foil 200 is also identified with the solder resist An identifier may be identified through 110. At this time, as another embodiment of the present invention, if there is an X-ray see-through device, it is of course possible to check the identifier without opening the solder resist 500.

The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

As described above, according to the present invention, since each panel as well as strips can be managed separately during the substrate manufacturing process step, a defective unit map in each unit process can be prepared, thereby reversing the cause of the defects in product completion. It has the advantage of being tracked.

100: first insulating layer
110: second insulating layer
120: third insulating layer
200: first copper foil
210: second copper foil
220: third copper foil
230: fourth copper foil
300: parts
400: insulator
500: solder resist

Claims (4)

A method of manufacturing a component-embedded printed circuit board,
(a) forming an inner layer such that the first insulating layer surrounds the component by mounting a component on a second copper foil and laminating a first insulating layer and the first copper foil;
(b) forming an identifier on the first copper foil; And
(c) laminating a second insulating layer and a third copper foil on the first copper foil, laminating a third insulating layer and a fourth copper foil on the second copper foil, and forming an outer layer by laminating
≪ / RTI >
The method of claim 1,
Locally removing and opening a third copper foil over the first copper foil portion having the identifier formed thereon
Printed circuit board manufacturing method further comprising.
The method of claim 1,
Applying a solder resist on the third copper foil and the fourth copper foil
Printed circuit board manufacturing method further comprising.
The method of claim 3,
Locally removing and opening the solder resist on the first copper foil portion on which the identifier is formed
Printed circuit board manufacturing method further comprising.
KR1020110053055A 2011-06-02 2011-06-02 Method of manufacturing chip-embedded printed circuit board KR20120134265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110053055A KR20120134265A (en) 2011-06-02 2011-06-02 Method of manufacturing chip-embedded printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110053055A KR20120134265A (en) 2011-06-02 2011-06-02 Method of manufacturing chip-embedded printed circuit board

Publications (1)

Publication Number Publication Date
KR20120134265A true KR20120134265A (en) 2012-12-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110053055A KR20120134265A (en) 2011-06-02 2011-06-02 Method of manufacturing chip-embedded printed circuit board

Country Status (1)

Country Link
KR (1) KR20120134265A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110831339A (en) * 2019-11-14 2020-02-21 江苏上达电子有限公司 Graphic design method for avoiding ink bubbles

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110831339A (en) * 2019-11-14 2020-02-21 江苏上达电子有限公司 Graphic design method for avoiding ink bubbles

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