KR20120129083A

KR20120129083A - Method for Manufacturing Semiconductor Device

Info

Publication number: KR20120129083A
Application number: KR1020110047130A
Authority: KR
Inventors: 서재욱
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2011-05-19
Filing date: 2011-05-19
Publication date: 2012-11-28

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a stepped part between a cell region and a peripheral circuit region by forming a line pattern using a partition mask. CONSTITUTION: A cell region(1000a) and a peripheral circuit region(1000b) are formed on a semiconductor substrate. A polymer layer is etched using a cutting mask. A polymer pattern is formed in the etched polymer layer. A second amorphous carbon layer(160) is formed in the upper part of the polymer pattern. A SiON is formed in the upper part of a first silicon oxide nitride layer(130).

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for simplifying a SPT (Spacer Patterning Technology) process.

As the integration density of semiconductor devices increases rapidly, the pattern becomes finer and more sophisticated, but the photolithography process technology has not been followed due to its fundamental limitations. In order to integrate as many elements as possible in a small area, the size of the individual elements should be made small. For this purpose, the pitch, which is the sum of the widths of the patterns and the spacing between the patterns, should be made small. Due to the resolution limitation of the photolithography process, there are many difficulties in forming a fine pitch in accordance with the design rule of the semiconductor device which is drastically reduced. In particular, the photolithography process for forming the device isolation region defining the active region of the substrate and the photolithography process for forming the line and space pattern have limitations in implementing desired fine patterns. Currently, semiconductor technology trends are introducing process technology to realize patterns below 40nm, and recently, high NA (Phase Shift Mask), PSM (Phase Shift Mask), low wavelength, OPC (Optical Proximity Correction) and OAI The company is overcoming optical limitations by applying Resolution Enhancement Technology (RET) such as Off Axis Illumination. In addition, new technologies such as immersion, double patterning, and double exposure are being introduced. However, these techniques are currently only in the research stage to compensate for the problems caused when applied to the actual process, and are difficult to apply to the actual process. In particular, as the size of the pattern decreases, it is inevitable to reduce the thickness of the photoresist in terms of the photolithography process. Thus, reducing the thickness of the photoresist has been proposed as a factor of reducing the process margin in the etching process. It is urgent to introduce new technologies to implement.

Double patterning technology, which is used to overcome the resolution limitations in the photolithography process, is being researched to realize a 40nm-class pattern and has been shown to be mass-produced. The technique is briefly disclosed. After forming a center pattern that is repeatedly formed at a predetermined pitch using a photolithography process, spacers are formed on both sidewalls of the center pattern, and the spacers are removed. It is a method of patterning the etching target by using.

When the spacer patterning method is used, a step occurs between the cell region and the peripheral circuit region, thereby reducing a margin of the mask process in a subsequent process and having a non-uniform pattern of the cell region. In order to prevent this, the mask process is performed by performing gap fill characteristics and planarization in a cell using an SOC film or an MFHM film. There is a problem that a defect occurs. In addition, using an SOC film, an MFHM film, or the like has a problem of increasing the process cost.

In order to solve the above-mentioned conventional problems, the present invention forms a hole-type pattern using a cutting mask before forming a spacer pattern using a spacer patterning process, and lines using a partition mask. By forming a pattern, a method of manufacturing a semiconductor device capable of preventing a step between a cell region and a peripheral circuit region and applying a flat plate process is provided.

The present invention provides a method of forming a pad insulating film, a first amorphous carbon layer, a first silicon oxynitride layer, and a polymer layer on a semiconductor substrate having a cell region and a peripheral circuit region, using a hole-type cutting mask. Etching a polymer layer to form a polymer pattern, forming a second amorphous carbon layer and a second silicon oxynitride layer on the polymer pattern and the first silicon oxide nitride film, using the line type partition mask Etching the second amorphous carbon layer and the second silicon oxynitride layer to form a second silicon oxynitride layer pattern, forming a spacer material on the second silicon oxynitride layer pattern and the polymer pattern, exposing a cell region Etching the spacer material using a mask to form a spacer pattern, and removing the polymer pattern; The method provides a method of manufacturing a semiconductor device, comprising forming a fine pattern by etching the first silicon oxynitride layer and the first amorphous carbon layer using a pattern as a mask.

Preferably, the spacer material is characterized in that it comprises an oxide or a nitride (Nitride).

Preferably, the removing of the polymer pattern may be performed using a strip process, but using plasma in an oxygen atmosphere.

Preferably, the cutting mask is formed in a hole type.

Preferably, the partition mask is formed in a line type.

According to the present invention, before forming a spacer pattern using a spacer patterning process, a hole type pattern is formed by using a cutting mask and a line pattern is formed by using a partition mask to form a cell region and a peripheral circuit region. There is an advantage that can prevent the step, the application of the flat plate process.

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

Referring to FIG. 1A, a pad oxide film 100, a pad nitride film 110, a first amorphous carbon layer 120, and a first silicon oxide are formed on a semiconductor substrate including a cell region 1000a and a peripheral circuit region 1000b. The nitride film 130 and the polymer layer 140 are formed.

Referring to FIGS. 1B and 1C, after the photoresist film is formed on the polymer layer 140, the first photoresist pattern 150 is formed by an exposure and development process using a hole-type cutting mask. The polymer layer 140 is etched using the first photoresist pattern 150 as an etch mask to form a polymer pattern 145. Thereafter, the first photoresist pattern 150 is removed.

Referring to FIG. 1D, a second amorphous carbon layer 160 and a second silicon oxynitride layer 170 are formed on the polymer pattern 145 and the first silicon oxynitride layer 130.

Next, after the photoresist film is formed on the second silicon oxynitride film 170, the second photoresist film pattern 180 is formed by an exposure and development process using a line type partition mask exposing the cell region. The second silicon oxynitride layer 170 and the second amorphous carbon layer 160 are etched using the second photoresist pattern 180 as an etch mask to form a line type second silicon oxynitride layer pattern (not shown) and the second amorphous carbon layer. Pattern 165 is formed. Thereafter, the second photoresist layer pattern 180 and the second silicon oxynitride layer pattern are removed.

Referring to FIG. 1E, a spacer material 190 is formed on the second amorphous carbon layer pattern 165 and the polymer pattern 145. At this time, the spacer material 190 is preferably ULTO (Ultra Low Temp Oxide), specifically, it is preferable to include an oxide (Oxide) or a nitride (Nitride).

Referring to FIGS. 1F and 1G, after forming a photoresist film on the spacer material 190, the third photoresist pattern 200 may be exposed and developed using a mask that exposes the cell region 1000a. To form. The second amorphous carbon layer pattern 165 is exposed by etching back the spacer material 190 of the cell region 1000a using the third photoresist pattern 200 as an etch mask, and using a strip process. The second amorphous carbon layer pattern 165 is removed to form the spacer pattern 195. In this case, the stripping process is performed using plasma in an O ₂ atmosphere.

1H and 1I, after the exposed polymer pattern 145 of the cell region 1000a is removed, the first silicon oxynitride layer 130 and the first amorphous carbon layer using the spacer pattern 195 as a mask. The 120 is etched to complete the fine pattern.

As described above, the present invention forms a hole-type pattern using a cutting mask before forming a spacer pattern using a spacer patterning process, and forms a line pattern using a partition mask to form a cell. There is an advantage that can prevent the step between the region and the peripheral circuit region, and can be applied to the flat plate process.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims

Forming a pad insulating film, a first amorphous carbon layer, a first silicon oxynitride film, and a polymer layer on a semiconductor substrate having a cell region and a peripheral circuit region;
Etching the polymer layer using a cutting mask to form a polymer pattern;
Forming a second amorphous carbon layer and a second silicon oxynitride layer on the polymer pattern and the first silicon oxide nitride layer;
Etching the second amorphous carbon layer and the second silicon oxynitride layer by using a partition mask to form a second silicon oxynitride layer pattern;
Forming a spacer material on the second silicon oxynitride layer pattern and the polymer pattern;
Etching the spacer material using a mask exposing a cell region to form a spacer pattern; And
Removing the polymer pattern, and etching the first silicon oxynitride layer and the first amorphous carbon layer using the spacer pattern as a mask to form a fine pattern
And forming a second insulating film on the semiconductor substrate.

The method of claim 1,
And the spacer material comprises an oxide or a nitride.

The method of claim 1,
The removing of the polymer pattern may be performed using a strip process, but using a plasma in an oxygen atmosphere.

The method of claim 1,
The cutting mask is a manufacturing method of a semiconductor device, characterized in that formed in a hole (hole) type.

The method of claim 1,
The partition mask is a semiconductor device manufacturing method, characterized in that formed in a line (line) type.