KR20120037254A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20120037254A
KR20120037254A KR1020100098895A KR20100098895A KR20120037254A KR 20120037254 A KR20120037254 A KR 20120037254A KR 1020100098895 A KR1020100098895 A KR 1020100098895A KR 20100098895 A KR20100098895 A KR 20100098895A KR 20120037254 A KR20120037254 A KR 20120037254A
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KR
South Korea
Prior art keywords
pattern
layer
forming
semiconductor device
manufacturing
Prior art date
Application number
KR1020100098895A
Other languages
Korean (ko)
Inventor
허중군
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100098895A priority Critical patent/KR20120037254A/en
Publication of KR20120037254A publication Critical patent/KR20120037254A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

Abstract

According to the present invention, after forming a photoresist pattern for forming a fine contact hole on a semiconductor substrate having a lower layer, depositing a polymer on the entire surface including the photoresist pattern, and removing the photoresist pattern to form a spacer pattern Provided is a method of manufacturing a semiconductor device capable of forming a fine contact hole by etching a lower layer using a spacer pattern.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a fine pattern of a semiconductor device, which simplifies a process in SPT (Spacer Patterning Technology).

As the integration density of semiconductor devices increases rapidly, the pattern becomes finer and more sophisticated, but the photolithography process technology has not been followed due to its fundamental limitations. In order to integrate as many elements as possible in a small area, the size of the individual elements should be made small. For this purpose, the pitch, which is the sum of the widths of the patterns and the spacing between the patterns, should be made small. Due to the resolution limitation of the photolithography process, there are many difficulties in forming a fine pitch in accordance with the design rule of the semiconductor device which is drastically reduced. In particular, the photolithography process for forming the device isolation region defining the active region of the substrate and the photolithography process for forming the line and space pattern have limitations in implementing desired fine patterns. Currently, semiconductor technology trends are introducing process technology to realize patterns below 40nm, and recently, high NA (Phase Shift Mask), PSM (Phase Shift Mask), low wavelength, OPC (Optical Proximity Correction) and OAI The company is overcoming optical limitations by applying Resolution Enhancement Technology (RET) such as Off Axis Illumination. In addition, new technologies such as immersion, double patterning, and double exposure are being introduced. However, these techniques are currently only in the research stage to compensate for the problems caused when applied to the actual process, and are difficult to apply to the actual process. In particular, as the size of the pattern decreases, it is inevitable to reduce the thickness of the photoresist in terms of the photolithography process. Thus, reducing the thickness of the photoresist has been proposed as a factor of reducing the process margin in the etching process. It is urgent to introduce new technologies to implement.

Double patterning technology, which is used to overcome the resolution limitations in the photolithography process, is being researched to realize a 40nm-class pattern and has been shown to be mass-produced. The technique is briefly disclosed. After forming a center pattern that is repeatedly formed at a predetermined pitch using a photolithography process, spacers are formed on both sidewalls of the center pattern, and the spacers are removed. It is a method of patterning the etching target by using.

1A to 1E are diagrams showing a method of manufacturing a semiconductor device according to the prior art, (i) shows a cross-sectional view and (ii) shows a plan view.

Referring to FIG. 1A, an insulating layer 100, a polysilicon layer 110, an amorphous carbon layer 120 (a-Carbon), a silicon oxynitride layer 130, and an antireflection layer 140 are sequentially deposited on a semiconductor substrate. . Here, the insulating film 100 and the polysilicon layer 110 have hydrophilic properties, whereas the amorphous carbon layer 120 has hydrophobic properties.

Next, after the photoresist film is formed on the anti-reflection film 140, the photoresist pattern 150 is formed by an exposure and development process using a fine pattern or a fine contact hole mask.

Referring to FIG. 1B, the anti-reflection film 140, the silicon oxynitride layer 130, and the amorphous carbon layer 120 are etched until the polysilicon layer 110 is exposed using the photoresist pattern 150 as an etch mask. A pattern (not shown), a silicon oxynitride layer pattern 135, and an amorphous carbon layer pattern 125 are formed. Thereafter, the antireflection film pattern is removed. Here, the silicon oxynitride layer pattern 135 and the amorphous carbon layer pattern 125 are referred to as a partition pattern.

Referring to FIG. 1C, a spacer material 160 is deposited on the silicon oxynitride layer pattern 135, the amorphous carbon layer pattern 125, and the polysilicon layer 110. In this case, the material for the spacer is formed as an oxide (Oxide) has a disadvantage that takes a lot of deposition equipment and deposition time when depositing the material for the spacer.

Referring to FIG. 1D, spacers 160 may be formed on sidewalls of the silicon oxynitride layer pattern 135 and the amorphous carbon layer pattern 125 by etching the spacer material 160. Next, the silicon oxynitride layer pattern 135 and the amorphous carbon layer pattern 125 are removed. In this case, the removal of the partition patterns 135 and 125 is a method using plasma, which is not a general photolithography equipment, but is removed using another etching equipment, and thus, a process step is added, and a process cost is added. There is a problem.

Referring to FIG. 1E, the contact hole 180 is formed by etching the polysilicon layer 110 until the insulating layer 100 is exposed using the spacer 170 as a barrier layer.

In the above-described method of manufacturing a semiconductor device, the spacer patterning technology according to the prior art has a problem in that the process is complicated and the process cost increases due to many process steps.

In order to solve the above problems, the present invention forms a photoresist pattern for forming a fine contact hole on a semiconductor substrate provided with a lower layer, and then deposits a polymer on the entire surface including the photoresist pattern. Provided is a method of manufacturing a semiconductor device capable of forming a spacer pattern using a polymer by removing a photoresist pattern and etching a lower layer using a spacer pattern to form fine contact holes.

The present invention provides a method of forming a photoresist pattern defining a hard mask layer and a contact hole on an etched layer, forming a polymer spacer on sidewalls of the photoresist pattern, removing the photoresist pattern, and using the polymer spacer as a mask. Forming a hard mask pattern by etching the hard mask layer using the hard mask layer, and forming a contact hole by etching the etched layer using the hard mask pattern as a mask. do.

The method may further include forming an anti-reflection film between the hard mask layer and the photoresist pattern.

Preferably, the photosensitive film pattern is characterized in that the pillar pattern.

Preferably, the pillar pattern is formed through a single exposure process using a single exposure mask or a double exposure process using a line and space mask.

Preferably, the forming of the polymer spacers is characterized in that formed by a spin coating method.

Preferably, the hard mask layer is characterized in that the laminated structure of the amorphous carbon layer and the silicon oxynitride film.

Preferably, the polymer spacer is characterized in that it comprises a polymer combination containing silicon (Si).

Preferably, the etched layer is characterized in that it comprises a laminated structure of an insulating film and a polysilicon layer.

Preferably, the insulating film is characterized in that it comprises a TEOS (Tetraethylosilicate) film.

Preferably, a baking process is performed between the forming of the photoresist pattern and the forming of the polymer spacer, thereby controlling CD (Critical Dimension) of the polymer spacer.

Preferably, the step of removing the photoresist pattern is characterized by using a negative developer.

According to the present invention, after forming a photoresist pattern for forming a fine contact hole on a semiconductor substrate having a lower layer, depositing a polymer on the entire surface including the photoresist pattern, and removing the photoresist pattern to form a spacer pattern Since the lower layer may be etched using the spacer pattern to form a fine contact hole, there is an advantage of reducing the process step and cost.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A to 2D are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention, (i) shows a cross-sectional view, and (ii) shows a top view.

Referring to FIG. 2A, an insulating layer 200, a polysilicon layer 210, an amorphous carbon layer 220, an amorphous carbon layer, a silicon oxynitride layer 230 (SiON), and an antireflection layer 240 (BARC) are sequentially formed on a semiconductor substrate. To be deposited. In this case, the insulating film 200 and the polysilicon layer 210 are referred to as an etched layer, and the amorphous carbon layer 220 and the silicon oxynitride film 230 are referred to as a hard mask layer.

Here, the insulating film 200 preferably includes a PETEOS (Plasma Enhanced Tetraethylosilicate) film. Here, the insulating layer 200 and the polysilicon layer 210 have hydrophilic characteristics, whereas the amorphous carbon layer 220 has hydrophobic characteristics.

Next, after the photoresist film is formed on the antireflection film 240, the photoresist pattern 250 is formed by an exposure and development process using a micro pattern or a micro contact hole mask. In this case, the photoresist film may be formed of a photoresist film (Thermal Acid Generator) in which an acidic component diffuses well when heat is applied. Here, the photoresist pattern 250 may be formed in a pillar-shaped pillar pattern, and the pillar pattern may be formed through a single exposure process using a single exposure mask or double exposure using a line and space mask. Exposure) is preferably formed through the process.

Referring to FIG. 2B, a polymer layer 260 is formed on the photoresist pattern 250 and the anti-reflection film 240. In this case, the polymer 260 layer is preferably deposited by a spin coating method in track equipment. In addition, after depositing the polymer 260 layer, a baking process may be performed to control the deposition degree of the polymer 260 layer and to control the CD (Critical Dimension) of the polymer 260 layer.

Referring to FIG. 2C, the polymer 260 isotropically etched to form spacers 270 on sidewalls of the photoresist pattern 250 and to remove the photoresist pattern 250. The spacer 270 forming process using the polymer 260 layer as in the present invention has an advantage of shortening the process time and cost compared with the spacer forming process using the insulating film of the prior art. The spacer 270 using the polymer 260 layer may include a polymer combination containing silicon (Si) for an etching selectivity with the photoresist pattern 250.

Here, the method of removing the photoresist pattern 250 is a bake process in a photoresist pattern 250 formed of a thermal acid generator which diffuses acidic components well by using a developer having a negative characteristic or by applying heat. The acidic component may be generated to remove the developer.

Referring to FIG. 2D, the anti-reflection film 240, the silicon oxynitride film 230, the amorphous carbon layer 220, and the poly may be formed using the spacer 270 as a barrier layer until the insulating film 200 is exposed. The silicon layer 210 is etched to form the contact hole 280.

As described above, the present invention forms a photoresist pattern for forming a fine contact hole on a semiconductor substrate provided with a lower layer, and then deposits a polymer on the entire surface including the photoresist pattern, and then removes the photoresist pattern Since the spacer pattern may be formed, the lower layer may be etched using the spacer pattern, and fine contact holes may be formed, thus reducing the process steps and cost.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (11)

Forming a photoresist pattern defining a hard mask layer and a contact hole on the etched layer;
Forming a polymer spacer on sidewalls of the photoresist pattern;
Removing the photoresist pattern;
Etching the hard mask layer using the polymer spacer as a mask to form a hard mask pattern;
Forming a contact hole by etching the etched layer using the hard mask pattern as a mask
A method of manufacturing a semiconductor device, comprising. The method of claim 1,
And forming an antireflection film between the hard mask layer and the photosensitive film pattern. The method of claim 1,
The photosensitive film pattern is a manufacturing method of a semiconductor device, characterized in that the pillar pattern. The method of claim 3, wherein
The pillar pattern may be formed through a single exposure process using a single exposure mask or through a double exposure process using a line and space mask. The method of claim 1,
The forming of the polymer spacer is a method of manufacturing a semiconductor device, characterized in that formed by spin (Spin) coating method. The method of claim 1,
The hard mask layer is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of an amorphous carbon layer and a silicon oxynitride film. The method of claim 1,
And the polymer spacer comprises a polymer combination containing silicon (Si). The method of claim 1,
The etched layer includes a stacked structure of an insulating film and a polysilicon layer. The method of claim 8,
The insulating film comprises a TEOS (Tetraethylosilicate) film manufacturing method of a semiconductor device. The method of claim 1,
And forming a photosensitive film pattern and forming a polymer spacer to control a CD (critical dimension) of the polymer spacer. The method of claim 1,
The removing of the photoresist pattern may include removing the photoresist using a negative developer.
KR1020100098895A 2010-10-11 2010-10-11 Method for manufacturing semiconductor device KR20120037254A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489839A (en) * 2012-06-11 2014-01-01 南亚科技股份有限公司 Hard mask spacer structure and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489839A (en) * 2012-06-11 2014-01-01 南亚科技股份有限公司 Hard mask spacer structure and fabrication method thereof

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