KR20120115020A - Fabricating method of array substrate for lcd - Google Patents

Abstract

PURPOSE: A method for manufacturing an array substrate for a liquid crystal display device is provided to eliminate an active tail due to an amorphous silicon thin film pattern which is formed in a lower portion of a data line during 4-mask processes. CONSTITUTION: A protection film is formed on a substrate. A contact hole is formed using a third mask. The contact hole exposes one area of a drain electrode. A second conductive film(130) is formed on the substrate. A pixel electrode(180) is formed using a fourth mask. The pixel electrode is directly connected to the drain electrode through the contact hole.

Description

Manufacturing method of array substrate for liquid crystal display device {FABRICATING METHOD OF ARRAY SUBSTRATE FOR LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate of a liquid crystal display device. The liquid crystal display device improves transmittance of a liquid crystal panel by removing an active tail generated when a signal wiring pattern is formed on the array substrate of the liquid crystal display device. It relates to a method for manufacturing an array substrate for use.

Various portable devices such as mobile phones and laptop computers, and information electronic devices that realize high resolution and high quality images such as HDTVs, have been applied to flat panel display devices. The demand for) is increasing. Such flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and organic light emitting diodes (OLEDs), but mass production technologies, ease of driving, Liquid crystal displays (LCDs) are currently in the spotlight for their realization and realization of large-area screens. In particular, an active matrix liquid crystal display device using a thin film transistor as a switch element is suitable for displaying a dynamic image.

According to the driving method, the liquid crystal display includes a twisted nematic (TN) method and a transverse electric field (In Plane Switching, IPS mode) method. In particular, the transverse electric field method has a wider viewing angle than the vertical electric field method. As a result, it is currently applied to many liquid crystal display devices.

FIG. 1 is a plan view illustrating one pixel in a conventional transverse electric field type liquid crystal display array substrate, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

As shown in the drawing, a gate wiring 16 and a data wiring 17 are formed on the array substrate 10 of the transverse electric field liquid crystal display device, which is arranged vertically and horizontally on the transparent array substrate 10 to define a pixel region. The thin film transistor which is a switching element is formed in the intersection area | region.

The above-described thin film transistor includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor has a gate insulating film 15a for insulation between the gate electrode 21 and the source and drain electrodes 22 and 23 and the source electrode 22 by the gate voltage supplied to the gate electrode 21. An active pattern 24 forming a conductive channel between the drain electrode and the drain electrode 23, an n + amorphous silicon pattern 25 for ohmic contact, and a protective film 15b covering an upper portion thereof.

Here, the common electrode 8 and the pixel electrode 18 for generating the transverse electric field are alternately arranged in the direction parallel to the data line 17 in the pixel region. In this case, the pixel electrode 18 is electrically connected to the drain electrode 23 through the contact hole 40 formed in the passivation layer, and the common electrode 8 is the common wiring 8l disposed in parallel with the gate wiring 16. ).

The transverse electric field type liquid crystal display array substrate 10 having such a structure is currently manufactured by a photolithography process using four masks. In the four-mask process, unlike the conventional five-mask process, the photoresist layer pattern is used. By simultaneously patterning the pattern 24 and the source / drain electrodes 22 and 23, one mask can be omitted.

However, in the array substrate 10 manufactured according to the 4-mask process, the amorphous silicon thin film pattern 24 ′ and the n + amorphous silicon thin film pattern 25 ′ are formed under the data line 17. It is formed simultaneously with the source / drain electrodes 22 and 23. The active pattern 24 and the amorphous silicon thin film pattern 24 ', which are the same material, are formed on the side surfaces of the active substrate 24 due to etching characteristics to reduce the transmittance of the array substrate 10. There is a disadvantage that tail (active tail, AT) occurs.

In detail, during the above-described 4-mask process, wet etching and dry etching are sequentially performed after patterning of the photoresist pattern in the second mask process. First, in accordance with the isotropy of the wet etching. An under cut is generated in the metal layer for forming the lower source / drain electrodes 22 and 23 and the data line 17 of the photoresist pattern, and the upper part is cut under the anisotropy of the vacuum dry etching. Less etching than the metal layer of the primary active tail (AT) is generated.

In addition, after the ashing process of the photoresist pattern, secondary active tails AT having a wider width are generated by secondary wet etching and wet etching.

As shown in FIG. 3, the dry etching process includes an upper electrode 2 and a lower electrode 3 in the vacuum chamber 1, and the lower electrode 3 grounded by applying an RF voltage to the upper electrode 2. Discharges SiFx gas formed by chemical reaction with the substrate 6 on the lower electrode 3 through the pump 4 so as to form a fluorine gas introduced into the plasma state, and is particularly used during etching of amorphous silicon. That's how it works. However, as the width becomes very wide due to two wet etching and dry etching processes during the 4-mask process, the transmittance is affected, and in particular, the transmittance of light is significantly reduced in the vicinity of the data line 17 so that the liquid crystal It is a major cause of deterioration of the image quality of the display device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a method of manufacturing an array substrate for a liquid crystal display device which removes an active tail due to an amorphous silicon thin film pattern formed under a data line in a 4-mask process. The purpose is to provide.

In order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device according to a preferred embodiment of the present invention, providing a substrate; Forming a gate electrode, a gate wiring and a common wiring on the substrate by using a first mask; Sequentially forming a first insulating film, an amorphous silicon thin film, a first conductive film, and a photosensitive film on the substrate; Selectively patterning the photoresist layer using a second mask to form a photoresist pattern, and performing a first etching process through the photoresist pattern, wherein the pattern of the amorphous silicon thin film is at least greater than that of the first conductive layer. Over etching to have a small width; Performing an ashing process and a second etching process on the photoresist pattern to form an active pattern, a source electrode, a drain electrode, and a data line; Forming a protective film over the substrate; Forming a contact hole exposing a region of the drain electrode by using a third mask; And forming a second conductive layer on the substrate, and forming a pixel electrode directly connected to the drain electrode through the contact hole by using a fourth mask.

The first etching process may include: wet etching the first conductive layer; And dry etching the amorphous silicon thin film.

Dry etching the amorphous silicon thin film may be performed using an atmospheric pressure plasma dry etching method.

The atmospheric plasma dry etching may be performed under a gas condition of 15 lpm of CF4, 550 lpm of air, and 400 lpm of O2.

The atmospheric plasma dry etching is characterized in that the progress at a speed of less than 3.15m / min less than 4.5m / min.

The atmospheric pressure plasma dry etching may be performed through seven or less gas supply means.

The amorphous silicon thin film has a thickness of 2000 kPa.

The amorphous silicon thin film may further include an n + amorphous silicon thin film.

The first conductive film is a multilayer structure of a MoTi layer and a Cu layer laminated on the MoTi layer.

According to a preferred embodiment of the present invention, when etching the amorphous silicon thin film pattern in the 4-mask process, by applying an isotropic atmospheric pressure plasma dry etching process to replace the anisotropic vacuum dry etching process, the active tail is formed on the lower portion of the data wiring There is an effect of manufacturing the array substrate for the liquid crystal display device having improved transmittance by removing the.

1 is a plan view illustrating one pixel in a conventional array substrate for a transverse electric field type liquid crystal display device.
FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.
3 is a schematic structural diagram of a vacuum dry etching apparatus.
4 is a plan view showing a part of an array substrate for a liquid crystal display device manufactured by a manufacturing method according to a preferred embodiment of the present invention.
5 is a structural diagram illustrating an atmospheric pressure plasma etching apparatus applied to an array substrate manufacturing method according to an embodiment of the present invention.
6A through 6H are plan views sequentially illustrating a manufacturing process of a part of the array substrate illustrated in FIG. 4.

Hereinafter, an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. The drawings referred to with respect to the following embodiments are not intended to limit the connection form and arrangement of the components to the illustrated forms, and in particular, the scale of some components to aid in understanding the technical structure and shape of the present invention. Exaggerated or reduced.

4 is a plan view showing a part of an array substrate for a liquid crystal display device manufactured by a manufacturing method according to a preferred embodiment of the present invention. In the following description, the technical concept of the present invention is described as an example of one pixel including a thin film transistor including a gate pad portion, a data pad portion, and a pixel portion for convenience. In an actual array substrate, N (N is one or more natural numbers) gate wirings And M (M is one or more natural numbers) data wires intersect, and there are MxN pixels.

As shown in the drawing, a gate wiring 116 and a data wiring 117 are formed on an array substrate 110 according to an embodiment of the present invention, which are arranged vertically and horizontally on the substrate to define pixels. In addition, a thin film transistor T as a switching element is formed in an intersection area between the gate line 116 and the data line 117, and a common electrode 108 for driving a liquid crystal (not shown) by generating a transverse electric field in the pixel. And pixel electrodes 118 are alternately formed.

The thin film transistor T includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 electrically connected to the pixel electrode 118. . In addition, the thin film transistor T includes an active pattern (not shown) that forms a conductive channel between the source electrode 122 and the drain electrode 123 by the gate voltage supplied to the gate electrode 121.

A portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel area to form a first contact hole 140a formed in a passivation layer (not shown). Is electrically connected to the pixel electrode wiring 118l and the pixel electrode 118 through the.

As described above, the common electrode 108 and the pixel electrode 118 for generating the transverse electric field are alternately arranged in the pixel. At this time, the common electrode 108 and the common electrode wiring 108 ′ are disposed in parallel with the gate wiring 116 through the second contact hole 140b formed in the gate insulating film and the protective film, respectively. , 108l ') is electrically connected to the upper common wiring 108l'.

The common electrode 108 described above may be made of the same opaque conductive material as the common electrode wiring 108 ′ and may be made of the same transparent conductive material as the pixel electrode 118 and the pixel electrode wiring 118l.

In this case, a portion of the pixel electrode wiring 118l overlaps a portion of the common wiring 108l below the gate insulating layer and the passivation layer to form a storage capacitor. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. In addition to signal retention, these storage capacitors play a role in stabilizing gray scale display and reducing flicker and afterimage.

The gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in the edge region of the array substrate 110 configured as described above. The scan signal and the data signal applied from the driving circuit unit are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate wiring 116 and the data wiring 117 extend in the direction of the driving circuit portion and are connected to the gate pad wiring 116p and the data pad wiring 117p, respectively, and the gate pad wiring 116p and the data pad wiring 117p. ) Receives a scan signal and a data signal from the driving circuit unit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad wiring 116p and the data pad wiring 117p, respectively.

In addition, the data pad electrode 127p is electrically connected to the data pad wiring 117p through the third contact hole 140c, and the gate pad electrode 126p is connected to the gate pad wiring (140d) through the fourth contact hole 140d. 116p).

In addition, the structure of the pixel illustrated in FIG. 4 is a two-domain structure in which the common electrode 108, the pixel electrode 118, and the data wiring 117 are bent, and liquid crystal molecules are arranged in two directions. The viewing angle is further improved compared to conventional mono-domains. However, the present invention is not limited to the transverse electric field type liquid crystal display device having the two-domain structure. As such, when the common electrode 108, the pixel electrode 118, and the data line 117 are formed in a bent structure to form a multi-domain structure in which the driving directions of the liquid crystal molecules are symmetric, the birefringence characteristics of the liquid crystal are obtained. The color shift phenomenon can be minimized by canceling the abnormal light by each other.

Here, the array substrate according to the embodiment of the present invention uses a diffraction mask or a half-tone mask (hereinafter referred to as a half-tone mask in the case of referring to a diffraction mask) and an active pattern and a single mask process. It is manufactured in a four-mask process by forming source / drain electrodes and data wirings.

In addition, the method for manufacturing an array substrate for a liquid crystal display device using a four-mask process according to an embodiment of the present invention, the conventional vacuum dry etching method in the dry etching proceeds after the patterning of the photosensitive film pattern during the second mask process It is characterized in that the atmospheric pressure plasma etching method is applied.

5 is a view showing an example of an atmospheric pressure plasma etching apparatus applied to the array substrate manufacturing method according to an embodiment of the present invention, as shown in the upper electrode disposed to have a separation distance of 0.8mm ~ 0.1mm ( In the chamber 100 having the 102 and the lower electrode 103, an RF voltage is applied to the upper electrode 102 to form a fluorine gas between the grounded lower electrode 103 and a plasma gas. Is contacted with the substrate 106 on the stage at atmospheric pressure to discharge the SiFx gas formed by the chemical reaction.

At this time, according to the etching recipe, the over-etching of the amorphous silicon layer under the photosensitive pattern is possible, so that the active tail can be removed and more detailed numerical values for the etching recipe can be obtained. The following will be described later in the array substrate manufacturing method.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

6A through 6H are plan views sequentially illustrating a manufacturing process of a part of the array substrate illustrated in FIG. 4.

First, as shown in FIG. 6A, a gate electrode 121, a gate wiring, and a common wiring 108l are formed in a pixel portion of an array substrate 110 made of a transparent insulating material such as glass, and the array substrate 110 is formed. The gate pad wiring line 116p is formed in the gate pad part of (). In this case, the common wiring 108l is formed above and below the pixel region in a direction substantially parallel to the gate wiring 116.

This step is a first mask process, in which the gate electrode 121, the gate wiring, the common wiring 108l, and the gate pad wiring 116p deposit a first conductive layer on the entire surface of the array substrate 110 and then pass through the first mask. It is formed by selectively patterning.

Here, aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum are used as the first conductive films. Low resistance opaque conductive materials such as alloys can be used. In addition, the first conductive film may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked. The first conductive film may be a multilayer structure of a MoTi layer and a Cu layer stacked thereon.

Next, as shown in FIG. 6B, the gate insulating film 115a and the amorphous silicon thin film are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate wiring, the common wiring 108l, and the gate pad wiring 116p are formed. 120, the n + amorphous silicon thin film 125 and the second conductive film 130 are sequentially formed.

Next, as shown in FIG. 6C, as a second mask process, a photosensitive film 170 made of a photosensitive material such as a photoresist is formed on the entire surface of the array substrate 110. Light is selectively irradiated to the photosensitive film 170 through the diffraction mask 180 according to the present invention.

The above-described diffraction mask 180 is applied with a first transmission region I and a slit pattern, which transmit all of the irradiated light, to block a portion of the second transmission region II, which transmits only part of the light, and blocks some of the irradiated light. The blocking region III is formed, and according to this structure, only the light transmitted through the diffraction mask 180 is irradiated to the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the diffraction mask 180 is developed, the light irradiated through the blocking region III and the second transmission region II of the mask is exposed as shown in FIG. 6D. The first photoresist pattern 170a to the fifth photoresist pattern 170e having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist 170 is completely formed in the first transmission region I through which all light is transmitted. The surface of the second conductive layer 130 is exposed to be removed.

In this case, the first photoresist pattern 170a to the fourth photoresist pattern 170d formed in the blocking region III may be thicker than the fifth photoresist pattern 170e formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all light is transmitted through the first transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist may be used.

Next, as shown in FIG. 6E, the first conductive film 130 formed below the first conductive film pattern 170a to the fifth photosensitive film pattern 170e as a mask is used as the first wet type. After etching selectively, the amorphous silicon thin film 120 and the n + amorphous silicon thin film 125 are selectively removed through the atmospheric pressure plasma dry etching shown in FIG. 5.

At this time, the amorphous silicon thin film and the n + amorphous silicon thin film have a thickness of about 2000 μs, and are etched at a scan speed of 3.15 m / min under a gas condition of 15 l of CF4, 550 lpm of air, and 400 lpm of O2. Do this.

It is anisotropically etched when the etching is performed at the scan rate of 4.5 m / min under the above-described gas conditions, and when the scan rate is lowered at a speed lower than that, the side etching proceeds to the inside of the photoresist patterns 170a 'to 170d'. The amorphous silicon thin film 120 and the n + amorphous silicon thin film 125 may be over-etched (e). Here, the optimum over-etching width for effective active tail is about 0.7 ~ 0.8 um on one side, the maximum ratio of the over-etching is 70% compared to the conventional, atmospheric pressure plasma dry etching at a speed of less than 4.5m / min 3.15m / min or more Proceed with over etching. At this time, it is appropriate that the number of atmospheric plasma etching apparatus heads used, that is, the number of means for supplying gas to the substrate is seven.

The atmospheric plasma etching process is characterized in that the gate insulating film 115a is not etched so that the breakdown of the insulating film according to the increased etching time does not occur.

According to the above-described atmospheric pressure plasma etching process, an active pattern 124 made of an amorphous silicon thin film is formed in the pixel portion of the array substrate 110, and a data wiring made of a second conductive film is formed in the data wiring portion of the array substrate 110. 117 is formed. In addition, a data pad line 117p formed of a second conductive layer is formed in the data pad portion of the array substrate 110.

In addition, the first n + amorphous silicon thin film pattern 125 ′ and the second conductive layer formed of the n + amorphous silicon thin film and the second conductive layer, respectively, and patterned in the same shape as the active pattern 124. The film pattern 130 'is formed.

The first amorphous silicon is formed of an amorphous silicon thin film and an n + amorphous silicon thin film under the data wire 117 and the data pad wire 117p, respectively, and is patterned in the same form as the data wire 117 and the data pad wire 117p. The thin film pattern 120 ′, the second n + amorphous silicon thin film pattern 125 ″, and the second amorphous silicon thin film pattern 120 ″ and the third n + amorphous silicon thin film pattern 125 ′ ″ are formed. It is over-etched by plasma dry etching (e).

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a to the fifth photoresist pattern 170e is performed, as illustrated in FIG. 7E, the second transmission region II may be formed. 5 The photoresist pattern is completely removed.

In this case, the first photoresist pattern to the fourth photoresist pattern may include the sixth photoresist pattern 170a 'to the ninth photoresist pattern 170d' from which the thickness of the fifth photoresist pattern is removed to correspond to the blocking region III. Only the electrode region and the drain electrode region and the upper portion of the data line 117 and the data pad line 117p remain.

Subsequently, as illustrated in FIG. 6F, the second conductive layer is subjected to the second wet etching process using the remaining sixth photoresist pattern 170a ′ through the ninth photoresist pattern 170d ′ as a mask. The source electrode 122 and the drain electrode 123 are formed through the second dry etching process to remove a portion of the first n + amorphous silicon thin film pattern and the second conductive film pattern. In this case, an ohmic contact layer formed of an n + amorphous silicon thin film on the active pattern 124 and ohmic contact between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123 ( 125n) is formed.

In addition, since the n + amorphous silicon thin film pattern 120 'and the amorphous silicon thin film pattern 125' 'under the first dry etching data line 117 are over-etched, the active tail is already removed.

As described above, in the exemplary embodiment of the present invention, the active pattern 124, the source / drain electrodes 122 and 123, and the data line 117 may be formed through one mask process by using a diffraction mask.

Thereafter, as shown in 6g, as a third mask process, the passivation layer 115b ′ to the entire surface of the array substrate 110 on which the active patterns 124, the source / drain electrodes 122 and 123, and the data lines 117 are formed. 115b ″) and first to fourth contact holes 140a (140b, 140c and 140d in FIG. 4) through a mask. In this case, the protective films 115b 'to 115b ″ are inorganic insulating films such as silicon nitride films. The first passivation layer 115b 'may be formed of only one layer, or may have a multilayer structure including a second passivation layer 115b ″ made of an organic insulating layer such as photoacryl.

This protects the back channel of the active pattern 124 by forming the first passivation layer 115b 'as the inorganic insulating layer, and the organic passivation layer having the low dielectric constant such as photoacryl. In order to realize the high opening ratio structure, the data wiring 117 and the common electrode 108 can be overlapped with each other.

Next, as shown in FIG. 6H, as the fourth mask process, the array substrate on which the above-described passivation layers 115b ′ to 115b ″ and the first to fourth contact holes 140a and 140b, 140c, and 140d of FIG. 4 are formed is formed. After forming a third conductive film made of a transparent conductive material on the entire surface of the 110, the pixel electrode wiring 118l electrically connected to the drain electrode 123 through the first contact hole 140a by selectively patterning using a mask. ) And a common electrode wiring (108 'in FIG. 4) electrically connected to the common wiring (108l' in FIG. 4) through the second contact hole (140b in FIG. 4).

Further, by selectively patterning the third conductive layer through a fourth mask process, a plurality of common electrodes 108 and pixel electrodes 118 are alternately disposed in the pixel region to generate a transverse electric field, and the third contact hole is formed. A data pad electrode 127p and a gate pad electrode 126p electrically connected to the data pad wiring 117p and the gate pad wiring 116p are formed through the 140c and the fourth contact hole 140d, respectively. .

In this case, the plurality of common electrodes 108 are connected to the common electrode wiring (108 ′ in FIG. 4), and the pixel electrode 118 is connected to the pixel electrode wiring 118l.

The third conductive layer may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO) to form the common electrode 108 and the pixel electrode 118. It includes a transparent conductive material having excellent transmittance.

The array substrate for a liquid crystal display device of the present invention manufactured according to this step is effectively removed the lower active tail of the data line formed by the 4-mask process, thereby improving the transmittance of the liquid crystal display device.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

110: array substrate 115a: gate insulating film
116p: Gate Pad Wiring 117: Data Wiring
117p: data pad electrode 121: gate electrode
120 '', 120 '' 124,: Amorphous Silicon Thin Film Pattern
125 ', 125'',125''': n + amorphous silicon thin film pattern
170a ', 170b', 170c ': photosensitive film pattern

Claims (9)

Providing a substrate;
Forming a gate electrode, a gate wiring, and a common wiring on the substrate by using a first mask;
Sequentially forming a first insulating film, an amorphous silicon thin film, a first conductive film, and a photosensitive film on the substrate;
Selectively patterning the photoresist layer using a second mask to form a photoresist pattern, and performing a first etching process through the photoresist pattern, wherein the pattern of the amorphous silicon thin film is at least greater than that of the first conductive layer. Over etching to have a small width;
Performing an ashing process and a second etching process on the photoresist pattern to form an active pattern, a source electrode, a drain electrode, and a data line;
Forming a protective film over the substrate;
Forming a contact hole exposing a region of the drain electrode by using a third mask; And,
Forming a second conductive layer on the substrate and forming a pixel electrode directly connected to the drain electrode through the contact hole by using a fourth mask;
Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 1,
The first etching process,
Wet etching the first conductive layer; And,
Dry etching the amorphous silicon thin film
Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 2,
Dry etching the amorphous silicon thin film,
A method of manufacturing an array substrate for a liquid crystal display device, characterized in that it is carried out by an atmospheric plasma dry etching method. The method of claim 3, wherein
The atmospheric plasma dry etching,
15 lpm CF4, 550 lpm air, 400 lpm O2 gas conditions for producing an array substrate for a liquid crystal display device. The method of claim 3, wherein
The atmospheric plasma dry etching,
A method of manufacturing an array substrate for a liquid crystal display device, characterized in that the speed is less than 4.5m / min 3.15m / min or more. The method of claim 3, wherein
The atmospheric plasma dry etching,
A method of manufacturing an array substrate for a liquid crystal display device, characterized in that it is carried out through seven or less gas supply means. The method of claim 1,
The amorphous silicon thin film has a thickness of 2000 kPa, the method of manufacturing an array substrate for a liquid crystal display device. The method of claim 1,
The amorphous silicon thin film, the manufacturing method of the array substrate further comprises an n + amorphous silicon thin film. The method of claim 1,
And the first conductive film has a multi-layered structure of a MoTi layer and a Cu layer stacked on top of the MoTi layer.

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