KR20120105834A - Semiconductor package and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to reduce the entire thickness of the semiconductor package by burying a bump on an insulating layer to mount a chip. CONSTITUTION: A first circuit layer(101a,101b) is formed on both sides of a core insulating layer(100). A first insulating layer(102a,102b) includes a second circuit layer(107a,107b) with a second bump pad. The first insulating layer has a first open section and a second open section to form a connection via(106a,106b). A first bump(112) is formed on the first open section. A first chip(110) is formed on the first bump.

Description

Semiconductor package and manufacturing method of the same

The present invention relates to a semiconductor package and a method of manufacturing the same.

In order to meet the technical requirements of high performance and thinning, materials, surface treatments, structures, and the like used in substrates for semiconductor packages have been developed.

Recently, in order to meet the demand of high performance and thinning, a semiconductor package having a package on package (PoP) structure is used, and in general, two semiconductors each composed of a memory and a processor are used.

However, in order to meet the trend of high performance of the product, the number of signals increases and the increase of input / output (I / O) pads used for power and ground requires a substrate for a semiconductor package having a new structure.

In other words, as the performance of electronic devices increases, the number of I / O pads to be formed on the same area of package substrates increases and the thickness of electronic devices needs to be reduced. It is gradually increasing.

The present invention is to solve the above-mentioned problems of the prior art, an aspect of the present invention is to provide a semiconductor package and a method of manufacturing the same to reduce the overall thickness of the semiconductor package of the package on package (PoP) structure.

Another aspect of the present invention is to provide a semiconductor package and a method of manufacturing the same, which enable bumps to be formed on a semiconductor package substrate through a simple process.

Another aspect of the present invention is to provide a semiconductor package and a method of manufacturing the same, which can implement fine pitch bumps.

The semiconductor package of the present invention,

A core insulating layer having both surfaces of the first circuit layer including the first bump pads;

A first open part formed on the core insulating layer to expose the first bump pad and a second open part for forming a connection via, the connection via and the connection via for interlayer connection with the first circuit layer A first insulating layer having a second circuit layer including a second bump pad formed on the first insulating layer;

A first bump formed on the first open part; And

A first chip formed on the first bumps;

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The second bump pad is formed on the first insulating layer.

Here, it is preferable that the first bump has a structure in which a part of the first bump is embedded in a thickness direction with respect to the first insulating layer.

The display device may further include a second insulating layer formed on the first insulating layer and having a third open part exposing a region where the first bump and the first chip are to be formed.

In addition, the second insulating layer is preferably a solder resist layer.

The second insulating layer may further include a fourth open part exposing the second bump pad.

In addition, the second bump formed in the fourth open portion; preferably further includes.

The package may further include a package including a second chip formed on the second bumps.

Another semiconductor package manufacturing method of the present invention,

Preparing a core insulating layer having a first circuit layer including first bump pads on both surfaces thereof;

A first insulating layer is formed on the core insulating layer, and a first open portion through which the first bump pad is exposed to form a first bump and a second open portion for forming a connection via are formed on the first insulating layer. step;

Forming a second circuit layer on the first insulating layer, the second circuit layer including a connection via for interlayer connection with the first circuit layer and a second bump pad formed on the connection via;

Plating the first open part to form a bump via;

Disposing a solder formed on a first chip on the bump via; And

Performing a reflow process on the bump vias and the solder to form the first bumps;

Including,

The second bump pad is formed on the first insulating layer.

Here, the step of forming the second open portion,

Forming a second open portion to expose the first bump pad to form a connection via for interlayer connection between the first circuit layer and the second circuit layer.

In addition, the step of forming the second circuit layer,

Forming a seed layer on the inner walls of the first and second openings and the first insulating layer including the exposed first bump pads;

Forming a plating resist pattern having an opening corresponding to the second opening, on the seed layer;

Filling the opening through plating to form a second circuit layer including a connection via and a second bump pad formed on the connection via;

Removing the plating resist pattern; And

Removing the seed layer;

It is preferable to include.

Further, in the forming of the second circuit layer,

It is preferable that the said plating is copper plating.

In addition, after the forming of the second circuit layer,

Forming a second insulating layer on the second circuit layer, and forming a third open portion exposing a region in which the first chip to be mounted on the first bump and the first bump is formed on the second insulating layer; step;

It is preferable to further include.

In addition, after the forming of the third open portion,

Forming a fourth open part exposing the second bump pad to the second insulating layer, and forming a second bump in the fourth open part; And

Forming a package including a second chip on the second bump;

It is preferable to further include.

Further, in the forming of the bump vias,

The bump via is preferably formed through tin plating.

Moreover, it is preferable that the said tin plating is electrolytic plating.

In addition, the bump via is preferably formed to correspond to each other and the solder formed on the first chip.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

The semiconductor package and the method of manufacturing the same of the present invention have a structure in which a bump for chip mounting is partially embedded in an insulating layer, and a solder resist is removed in an area of the semiconductor package substrate on which the chip is mounted. A reduction effect can be expected, and in addition, an overall thickness of a semiconductor package having a package on package (PoP) structure can be expected to be reduced.

In addition, the present invention can form bumps for chip mounting through a simple process of performing tin plating on the open portion formed on the semiconductor package substrate, thereby simplifying the manufacturing process and reducing the manufacturing cost. have.

In addition, since the bumps are partially embedded in the insulating layer of the semiconductor package substrate, there is an effect that bridge defects connected between bumps can be prevented even when fine bumps are formed.

1 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention;
2 is a cross-sectional view showing a semiconductor package of a package on package structure according to the present invention;
3 to 11 are flowcharts illustrating a method of manufacturing the semiconductor package of FIG. 1 according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings.

In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms.

As used herein, the term “bump via” refers to a via formed for bump formation, and “connection via” refers to a via for interlayer connection.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Semiconductor package

1 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention, Figure 2 is a cross-sectional view showing a semiconductor package of a package on package structure according to the present invention.

Hereinafter, the semiconductor package of the present invention will be described with reference to FIGS. 1 and 2.

1 and 2, the semiconductor package 200 includes a core insulating layer 100 having both surfaces of first circuit layers 101a and 101b including first bump pads and on the core insulating layer 100. A first opening and a second opening for forming a connection via to expose the first bump pad, the connection vias 106a and 106b for interlayer connection with the first circuit layer and the connection via ( First insulating layers 102a and 102b having second circuit layers 107a and 107b including second bump pads formed on 106a and 106b, first bumps 112 formed in the first openings, and And a first chip 110 formed on the first bump 112, and the second bump pad is formed on the first insulating layers 102a and 102b.

As the insulating layers 100, 102a, and 102b, conventional resin insulating materials may be used. The resin insulating material may be thermosetting resin such as FR-4, Bismaleimide Triazine (BT), Ajinomoto Build up Film (ABF), thermoplastic resin such as polyimide, or the like. Resin impregnated with a reinforcing material such as a fiber or an inorganic filler, for example, prepreg may be used, and thermosetting resin and / or photocurable resin may be used, but is not particularly limited thereto.

Preferably, the first bump 112 may have a structure in which a portion of the first bump 112 is embedded in the thickness direction with respect to the first insulating layer 102a.

Referring to FIG. 1, a plurality of first bumps 112 are formed so that a part of the first bumps 112 are embedded in the first insulating layer 102a. Even when a fine pitch bump is implemented, a bridge phenomenon is not connected between bumps. It can be expected that the effect can be prevented.

Here, the first bumps 112 are formed by melting and bonding the vias formed through tin plating and the reflow process of the solder attached to the first chip 110, which will be described later. do.

The first circuit layers 101a and 101b may be used without limitation as long as they are used as conductive metals for circuits in the circuit board field, and copper is typically used.

In addition, the core insulating layer 100 may be provided with a first circuit layer including a circuit pattern and a soldering pad in addition to the first bump pad.

Preferably, the semiconductor package 200 is formed on the first insulating layers 101a and 101b and has a second insulating layer having a third open portion exposing a region where the first bump and the first chip are to be formed. 108a, 108b) may be further included.

In addition, the second insulating layers 108a and 108b may further include a fourth open portion (not shown) that exposes the second bump pads.

Here, the second insulating layer may be a solder resist layer.

The solder resist layer functions as a protective layer to protect the outer circuit pattern of the outermost layer, and is formed for electrical insulation, and is open (not shown) to expose the second circuit layers 107a and 107b of the outermost layer. ) Is formed. The solder resist layer may be composed of, for example, a solder resist ink, a solder resist film, or an encapsulant, as is known in the art, but is not particularly limited thereto.

Preferably, as shown in FIG. 2, the semiconductor package 200 includes a second bump 120 formed on a fourth open part (not shown) and a second chip 301 formed on the second bump 120. It may further include a package 300 including).

Here, the package 300 refers to a semiconductor package in which the second chip 301 is mounted on a printed circuit board.

As shown in FIG. 2, the connection vias 106a are formed on the first circuit layers 101a and 101b, and considering the arrangement of the first chips 110, the connection vias 106a are formed in the region where the first bumps 112 are formed. It is preferable to arrange | position in the excluded area. For example, when the plurality of first bumps 112 are formed at the center of the semiconductor package substrate corresponding to the lower portion of the first chip 110, the second bumps 120 are formed outside the center. The connecting vias 106a are also preferably formed on the outer side.

As shown in FIGS. 1 and 2, the first chip 110 is a processor such as a central processing unit (CPU), and the second chip 301 is a DRAM, a flash memory, a ROM, and the like. The memory may be the same, but is not limited thereto.

Meanwhile, the semiconductor package 200 may design a circuit pattern differently from the upper part according to the needs of the operator, such as the lower part of the core insulating layer 100 of FIGS. It is possible to form the solder ball 121 for the connection.

1 and 2, when the solder ball 121 is formed, the second circuit layer 107b in contact with the solder ball refers to a soldering pad.

Manufacturing method of semiconductor package

3 to 11 are flowcharts illustrating a method of manufacturing the semiconductor package of FIG. 1 according to the present invention.

First, referring to FIG. 3, a core insulating layer 100 having first circuit layers 101a and 101b including first bump pads on both surfaces thereof is prepared, and a first insulating layer is formed on the core insulating layer 100. 102a and 102b and first openings 103a exposing the first bump pads to form the first bumps 112 on the first insulating layers 102a and 102b and second openings for forming vias. The part 103b is formed.

The first circuit layers 101a and 101b may be used without limitation as long as they are used as conductive metals for circuits in the circuit board field, and copper is typically used.

As the insulating layer, a conventional resin insulating material may be used. The resin insulating material may be thermosetting resin such as FR-4, Bismaleimide Triazine (BT), Ajinomoto Build up Film (ABF), thermoplastic resin such as polyimide, or the like. Resin impregnated with a reinforcing material such as a fiber or an inorganic filler, for example, prepreg may be used, and thermosetting resin and / or photocurable resin may be used, but is not particularly limited thereto.

When the first open part 103a is formed, the first open part 103a is formed to expose the first bump pad of the first circuit layer 101a corresponding to the position where the first bump 112 is to be formed. do.

The first open part 103a and the second open part 103b may be performed by conventional laser processing, such as a Yag laser, but are not limited thereto. When processing with the laser, since the size of the open portion of the fine pitch can be implemented, it is advantageous to form fine pitch bumps.

The second open part 103b may expose the first bump pad to form connection vias 106a and 106b for interlayer connection between the first circuit layers 101a and 101b and the second circuit layers 107a and 107b. To form.

Next, as shown in FIGS. 4 to 7, the connection vias 106a and 106b and the connection vias 106a and 106b for the interlayer connection with the first circuit layers 101a and 101b on the first insulating layer 102a. Second circuit layers 107a and 107b including second bump pads formed on 106b are formed.

In more detail, referring to FIG. 4, a seed layer is formed on an inner wall of the first open part 103a and the second open part 103b including the exposed first bump pads and on the first insulating layer 102a. Form 104a.

In this case, the seed layer may be an electroless plating layer. The electroless plating is preferably chemical copper plating, but is not limited thereto.

The electroless plating layer described above may include, for example, a degreasing process, a soft etching process, a pre-catalyst process, a catalyst treatment process, an activator process, an electroless plating process, and It is formed using a general catalyst precipitation method including an oxidation treatment process. Detailed description of the catalyst precipitation method, which is a known technique, will be omitted.

Next, referring to FIG. 5, a plating resist pattern 105 having an opening corresponding to the second open part 103b is formed on the seed layer 104a.

Here, the plating resist pattern 105 is preferably formed such that the opening is larger than the second open portion 103b in the longitudinal direction in consideration of the formation of the second bump pad.

In addition, as the plating resist pattern 105, a photosensitive resist such as a dry film or a positive liquid photo resist (P-LPR) may be used, and after the photosensitive resist is applied to the seed layer, The openings can be formed by exposing ultraviolet rays to a portion corresponding to the circuit formation region and removing the exposed portions using a developer.

Next, referring to FIGS. 6 and 7, the openings of the plating resist patterns 105 are filled with plating to include connection vias 106a and 106b and second bump pads formed on the connection vias 106a and 106b. The second circuit layers 107a and 107b are formed, and the plating resist pattern 105 and the seed layer 104a underneath are removed to seed the layers 104a and 104b and the connection vias 106a and 106b and the second bumps. Second circuit layers 107a and 107b including pads are formed.

In this case, an electroplating process is performed in the opening of the plating resist pattern 105, and the electroplating is preferably copper plating, but is not limited thereto.

Here, the plating resist pattern 105 is removed using a stripping solution such as sodium hydroxide (NaOH) or potassium hydroxide (KOH), and the seed layers 104a and 104b are removed by quick etching or flash etching. Removed.

The second bump pads are formed on the first insulating layers 102a and 102b.

Next, referring to FIG. 8, second insulating layers 108a and 108b are formed on the second circuit layers 107a and 107b, and the first bumps 112 and the first bumps 112 and 108b are formed on the second insulating layers 108a and 108b. The third open part exposing the region where the first chip 110 to be mounted on the first bump is to be formed is formed.

In this case, the second insulating layers 108a and 108b may be solder resist layers.

The solder resist layer functions as a protective layer to protect the outermost layer circuit and is formed for electrical insulation, and then exposes the second circuit layers 107a and 107b of the outermost layer to form the second bumps 120. An open portion (not shown) may be formed. The solder resist layer may be composed of, for example, a solder resist ink, a solder resist film, or an encapsulant, as is known in the art, but is not particularly limited thereto.

Next, referring to FIG. 9, a bump via 109 is formed by plating the first open part 103a.

In this case, the bump via is formed by performing tin plating. In addition, tin plating is preferably performed by electrolytic plating.

In more detail, in a work panel (not shown) state in which a plurality of semiconductor package substrates are separated from each other, a contact point of a work panel to which an electric signal is supplied corresponds to an inner layer pad of the semiconductor package substrate. When electrically connected to the first circuit layer 101a, electricity is supplied through the first circuit layer 101a formed under the bump via 109 to perform electrolytic tin plating.

The bump via 109 may be formed to correspond to each other with the solder 111 formed on the first chip 110.

For example, the bump via 109 is formed to correspond to the position and the number of solders 111 formed on the first chip 110, so that the first chip 110 is disposed on the first insulating layer 102a. In this case, the bump via 109 and the solder 111 correspond to each other as shown in FIG. 1.

Next, referring to FIGS. 10 and 11, after the solder 111 formed on the first chip 110 is disposed on the bump via 109, a reflow process may be performed on the bump via 109 and the solder 111. Is performed to form the first bumps 112 through melting and bonding.

Although not shown, before the step of disposing the solder 111 formed on the first chip 110 of FIG. 10, the first chip 110 is formed and a semiconductor is formed on the substrate mounting surface of the first chip 110. A process of forming the solder 111 for mounting on the package substrate is performed.

Subsequently, as shown in FIG. 2, a fourth open part (not shown) is further formed on the second insulating layers 108a and 108b to expose the second bump pads, and the second bump ( The package 300 including the second chip 301 may be formed on the second bump 120.

The solder 111 attached to the first chip 110 is formed to mount the chip on the semiconductor package substrate, which will be omitted in the corresponding description.

However, in order to form bumps during the process of mounting the first chip 110 on the semiconductor package substrate disclosed in the present invention, in addition to the solder 111 attached to the first chip 110, a separate solder (via of the semiconductor package substrate) is used. Solder bumps on top) are not required.

In general, in order to mount the chip on the semiconductor package substrate, the solder attached to the chip and the solder bumps attached to the semiconductor package substrate are melt-bonded to each other.

However, in the present invention, as shown in FIGS. 9 to 11, tin plating is performed on the first openings 103a and solder attached to the first chip 110 to the bump vias 109 formed therefrom. Since the (111) is melted and bonded, the step of forming solder bumps on the semiconductor package substrate side can be omitted, and the effect of simplifying the overall semiconductor package manufacturing process can be expected.

In addition, since the first bump 112 of the present invention is partially embedded in the first insulating layer 102a, the gap between the semiconductor package substrate and the first chip 110 mounted on the semiconductor package substrate is reduced. The effect can be expected, which can be expected to reduce the overall thickness of the Package on Package (PoP) package.

In addition, since the first bumps 112 of the present invention are buried in the first insulating layer 102a, even when the fine pitch bumps are implemented, bridges connected to each other between the bumps can be prevented. You can expect the effect.

Meanwhile, the semiconductor package 200 may design a circuit pattern differently from the upper part according to the needs of the operator, such as the lower part of the core insulating layer 100 of FIGS. It is possible to form a solder ball 121 for the connection.

1 and 2, when the solder balls 121 are formed, the second circuit layer 107b in contact with the solder balls is a soldering pad.

Although the present invention has been described in detail with reference to specific embodiments, it is intended to describe the present invention in detail, and the semiconductor package and its manufacturing method according to the present invention are not limited thereto. It is apparent that modifications and improvements are possible to those skilled in the art.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: core insulating layer 101a, 101b: first circuit layer
102a, 102b: first insulating layer 103a: first open portion
103b: second open portions 104a and 104b: seed layer
105: plating resist pattern 106a, 106b: connection via
107a and 107b: second circuit layer 108a and 108b: second insulating layer
109: bump via 110: first chip
111 solder 112 first bump
120: second bump 200, 300: semiconductor package
301: second chip

Claims (16)

A core insulating layer having both surfaces of the first circuit layer including the first bump pads;
A first open part formed on the core insulating layer to expose the first bump pad and a second open part for forming a connection via, the connection via and the connection via for interlayer connection with the first circuit layer A first insulating layer having a second circuit layer including a second bump pad formed on the first insulating layer;
A first bump formed on the first open part; And
A first chip formed on the first bumps;
Including,
The second bump pad is formed on the first insulating layer. The method of claim 1,
The first bump may have a structure in which a portion of the first bump is embedded in a thickness direction with respect to the first insulating layer. The method of claim 1,
A second insulating layer formed on the first insulating layer and having a third open portion exposing a region where the first bump and the first chip are to be formed;
A semiconductor package further comprising. The method of claim 3,
The second insulating layer is a semiconductor package is a solder resist layer. The method of claim 3,
The second insulating layer further includes a fourth open part exposing the second bump pad. The method of claim 5,
A second bump formed on the fourth open part;
A semiconductor package further comprising. The method according to claim 6,
A package including a second chip formed on the second bumps;
A semiconductor package further comprising. Preparing a core insulating layer having a first circuit layer including first bump pads on both surfaces thereof;
A first insulating layer is formed on the core insulating layer, and a first open portion through which the first bump pad is exposed to form a first bump and a second open portion for forming a connection via are formed on the first insulating layer. step;
Forming a second circuit layer on the first insulating layer, the second circuit layer including a connection via for interlayer connection with the first circuit layer and a second bump pad formed on the connection via;
Plating the first open part to form a bump via;
Disposing a solder formed on a first chip on the bump via; And
Performing a reflow process on the bump vias and the solder to form the first bumps;
Including,
The second bump pad is formed on the first insulating layer. 9. The method of claim 8,
Forming the second open portion,
And forming a second open portion to expose the first bump pad to form a connection via for interlayer connection between the first circuit layer and the second circuit layer. 10. The method of claim 9,
Forming the second circuit layer,
Forming a seed layer on the inner walls of the first and second openings and the first insulating layer including the exposed first bump pads;
Forming a plating resist pattern having an opening corresponding to the second opening, on the seed layer;
Filling the opening through plating to form a second circuit layer including a connection via and a second bump pad formed on the connection via;
Removing the plating resist pattern; And
Removing the seed layer;
≪ / RTI > The method of claim 10,
In the step of forming the second circuit layer,
The plating is a copper plating semiconductor package manufacturing method. 9. The method of claim 8,
After forming the second circuit layer,
Forming a second insulating layer on the second circuit layer, and forming a third open portion exposing a region in which the first chip to be mounted on the first bump and the first bump is formed on the second insulating layer; step;
The semiconductor package manufacturing method further comprising. The method of claim 12,
After forming the third open portion,
Forming a fourth open part exposing the second bump pad to the second insulating layer, and forming a second bump in the fourth open part; And
Forming a package including a second chip on the second bump;
The semiconductor package manufacturing method further comprising. 9. The method of claim 8,
In forming the bump vias,
The bump via is formed by tin plating. 15. The method of claim 14,
The tin plating is a semiconductor package manufacturing method of electrolytic plating. 9. The method of claim 8,
The bump via may be formed to correspond to each other and the solder formed on the first chip.

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