KR20120097979A

KR20120097979A - Semiconductor device

Info

Publication number: KR20120097979A
Application number: KR1020110017610A
Authority: KR
Inventors: 김종삼
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2011-02-28
Filing date: 2011-02-28
Publication date: 2012-09-05

Abstract

1. A pumping voltage generation circuit of a semiconductor device, the method comprising: a first pumping voltage detector configured to detect a level of a pumping voltage based on a target level set in an activation period of an enable signal and a target level set in an inactivation section of the enable signal; Detects the level of the pumping voltage, and generates an oscillation signal in response to output signals of the second pumping voltage detector and the first or second pumping voltage detector having a relatively slower operating speed than the first pumping voltage detector. An oscillation signal generator for varying the frequency of the oscillation signal in response to the signal, and a pumping voltage generator for generating a pumping voltage by performing a charge pumping operation at a speed corresponding to the frequency of the oscillation signal.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a pumping voltage generation circuit of a semiconductor device.

Most semiconductor devices including DRAM generate and use an internal voltage having a different level from the power supply voltage in addition to a power supply voltage (VDD, VSS, etc.) supplied from an external source. Typically, the internal voltage is charge pumped or voltage down converted using a reference voltage corresponding to the target level, an external power supply voltage VDD, and an external ground voltage VSS. Internal voltage is generated by the method.

In the case of DRAM, an internal voltage generated using a charge pumping method includes a boost voltage VPP and a back bias voltage VBB. In addition, the internal voltages generated by the voltage drop conversion scheme include the core voltage VCORE and the bit line precharge voltage VBLP.

The boosted voltage VPP has a higher voltage level than the external power supply voltage VDD and is mainly used for driving a word line. On the other hand, the back bias voltage VBB is a negative voltage lower than the ground voltage VSS, and is mainly used as a body (bulk) bias of a cell transistor (NMOS transistor).

1 is a block diagram illustrating a pumping voltage generation circuit of a semiconductor device according to the prior art.

For reference, the pumping voltage PUMPING_VOL illustrated in FIG. 1 means the above-mentioned boosted voltage VPP or back bias voltage VBB.

Referring to FIG. 1, a pumping voltage generation circuit of a semiconductor device according to the related art may operate in an activation section of an enable signal ENABLE and have a first pumping voltage detector 100 of a differential amplification type having a relatively high operation speed. And an output signal DET_A of the second pumping voltage detector 110 of the current sensing type and the first pumping voltage detector 100 operating in an inactive section of the enable signal ENABLE and having a relatively slow operation speed. An oscillation signal generator 120 generating an oscillation signal OSC in response to the output signal DET_B of the second pumping voltage detector 110 and a pumping voltage by performing a charge pumping operation in response to the oscillation signal OSC. And a pumping voltage generator 140 generating (PUMPING_VOL).

Here, since the first pumping voltage detector 100 uses a pumping voltage detection method of a differential amplifier type, the pumping voltage (PUMPING_VOL) is effective because the offset is small and the response speed is high due to the characteristics of the differential amplifier type. You can expect a degree of scattering of.

In addition, since the second pumping voltage detector 110 uses a current sensing type pumping voltage detection method, the level of the pumping voltage PUMPING_VOL that is detected according to the temperature change due to the characteristic of the current sensing type is changed. Modulation effects can be expected.

On the other hand, the pumping voltage detection method of the differential amplification type has the disadvantage that there is no modulation characteristic that the level of the pumping voltage (PUMPING_VOL) changes with the change of temperature, and the pumping voltage detection method of the current sensing type has a slow response speed. In the related art, in order to select a pumping voltage detection method that is most effective according to the use of the semiconductor device, the first pumping voltage detection unit 100 and the second pumping unit are enabled according to an enable signal ENABLE in one semiconductor device. It is designed to select and use any one of the pumping voltage detector 110.

However, the pumping voltage detection method according to the related art has a first pumping voltage detection unit 100 of a differential amplification type having a relatively high operating speed according to an enable signal ENABLE and a second current sensing type having a relatively slow operating speed. Any one of the pumping voltage detectors 110 is selected, and the output signal DET_A of the first pumping voltage detector 100 and the output signal DET_B of the second pumping voltage detector 110 are all one oscillation signal. Since the oscillation signal OSC is applied to the generation unit 120 to generate the oscillation signal OSC, the following problem may occur due to a relationship between the operating speed of the detection unit and the frequency of the oscillation signal OSC generated by the oscillation signal generation unit 120. May occur.

First, the oscillation signal OSC having a relatively high frequency is oscillated by designing the oscillation signal generator 120 in anticipation of selecting the first pumping voltage detector 100 of the differential amplification type having a relatively high operating speed. The generation unit 120 is configured to generate, but when the actual operating environment of the semiconductor device is different from the expected environment requiring the modulation characteristics according to the temperature fluctuation, the second pumping voltage detection unit 110 of the current sensing type is selected Will be used. At this time, since the operation speed of the second pumping voltage detector 110 of the current sensing type is relatively very slow, the operating speed of the second pumping voltage detector 110 and the oscillation signal generated by the oscillation signal generator 120 (OSC) The problem of poor relationship between the frequencies of) occurs.

For example, assuming that the first pumping voltage detector 100 of the differential amplification type expected to be selected at the time of design has an operating speed of about 100 ns, an oscillation signal OSC having a period of about 50 ns is generated to correspond thereto. In this case, the oscillation signal generator 120 is designed. However, since the operating speed of the second pumping voltage detector 110 of the current sensing type that is actually selected in the process of using the semiconductor device generally ranges from 1000 ns to 10 us, the level change of the pumping voltage PUMPING_VOL is changed to the second pumping voltage detector. After the oscillation signal OSC is generated to sense the 110 and operate the pumping voltage generator 140, the oscillation signal OSC is generated 20 times until a signal for stopping the pumping voltage generator 140 is generated again. Toggling up to 200 times causes excessive operation of the pumping voltage generator 140, thereby causing a problem that the level of the pumping voltage PUMPING_VOL fluctuates too much. Of course, the opposite case may occur and the level of the pumping voltage PUMPING_VOL fluctuates too small.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a pumping voltage generation circuit of a semiconductor device capable of generating a pumping voltage having a stable target level regardless of fluctuations in the pumping voltage detection operation. There is this.

According to an aspect of the present invention for achieving the above object, the first pumping voltage detection unit for operating in the activation period of the enable signal; A second pumping voltage detector operating in an inactive section of the enable signal, the second pumping voltage detector having a relatively slower operating speed than the first pumping voltage detector; An oscillation signal generation unit generating an oscillation signal in response to an output signal of the first or second pumping voltage detector, and varying a frequency of the oscillation signal in response to the enable signal; And a pumping voltage generator configured to generate the pumping voltage by performing a charge pumping operation at a speed corresponding to the frequency of the oscillation signal.

The present invention described above has the effect of generating a pumping voltage having a stable target level by varying the frequency of the oscillation signal in response to the fluctuation of the pumping voltage detection operation.

1 is a block diagram illustrating a pumping voltage generation circuit of a semiconductor device according to the prior art.
2 is a block diagram illustrating a pumping voltage generation circuit of a semiconductor device according to an embodiment of the present invention.
3 is a circuit diagram illustrating in detail a first pumping voltage detector among components of a pumping voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating in detail a second pumping voltage detector among components of a pumping voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention.
FIG. 5 is a circuit diagram illustrating in detail an oscillation signal generation unit among components of a pumping voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention illustrated in FIG. 2.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

2 is a block diagram illustrating a pumping voltage generation circuit of a semiconductor device according to an embodiment of the present invention.

For reference, the pumping voltage PUMPING_VOL illustrated in FIG. 2 means the above-mentioned boosted voltage VPP or back bias voltage VBB.

Referring to FIG. 2, the first pumping voltage detector 200 and the enable signal ENABLE are disabled to detect the level of the pumping voltage PUMPING_VOL based on the target level set in the activation section of the enable signal ENABLE. The second pumping voltage detector 210 and the first pumping voltage detector detect a level of the pumping voltage PUMPING_VOL based on the target level set in the section, and have a relatively slower operating speed than the first pumping voltage detector 200. An oscillation signal OSC is generated in response to the output signal DET_A of 200 or the output signal DET_B of the second pumping voltage detector 210, but in response to the enable signal ENABLE. An oscillation signal generator 220 that varies the frequency of the oscillation signal, and a pumping voltage generator 240 that generates a pumping voltage PUMPING_VOL by performing a charge pumping operation at a speed corresponding to the frequency of the oscillation signal OSC. .

Here, the oscillation signal generator 220 generates an oscillation signal OSC having a relatively high frequency in the activation section of the enable signal ENABLE, and generates a relatively low frequency in the inactivation section of the enable signal ENABLE. Generate an oscillation signal (OSC) having a.

In addition, since the pumping voltage detection method of the differential amplification type (differential amp. Type) uses the pumping voltage detection method, the first pumping voltage detection unit 200 has a relatively high operating speed but is always based on a constant target level regardless of temperature fluctuation. It will work.

On the other hand, since the second pumping voltage detector 210 uses a current sensing type pumping voltage detection method, the second pumping voltage detector 210 operates based on a target level that is relatively slow but operates in response to a temperature change. Done.

In the above-described pumping voltage generation circuit of the semiconductor device according to the embodiment of the present invention, the enable signal ENABLE is activated so that the first pumping voltage detection unit 200 having a relatively high operating speed is selected to output the output signal DET_A. When applied to the oscillation signal generator 220, the oscillation signal generator 220 also controls to generate an oscillation signal OSC having a relatively high frequency, thereby operating speed and oscillation signal of the first pumping voltage detector 200 ( OSC) frequency can be matched.

Similarly, when the enable signal ENABLE is deactivated and the second pumping voltage detector 210 having a relatively slow operation speed is selected and the output signal DET_B is applied to the oscillation signal generator 220, the oscillation signal generator The control unit 220 may generate the oscillation signal OSC having a relatively low frequency to match the relationship between the operating speed of the second pumping voltage detector 210 and the frequency of the oscillation signal OSC.

3 is a circuit diagram illustrating in detail a first pumping voltage detector among components of a pumping voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention.

For reference, the first pumping voltage detector 210 illustrated in FIG. 3 is a circuit diagram on the assumption that the pumping voltage PUMPING_VOL is the back bias voltage VBB.

Referring to FIG. 3, the first pumping voltage detection unit 200 among the components of the pumping voltage generation circuit of the semiconductor device according to an embodiment of the present invention divides the level of the back bias voltage VBB to divide the distribution voltage DET. The logic voltage of the level detection signal DET_A is determined by comparing the divided voltage generator 202 to generate the voltage with the level of the divided voltage DET and the level of the back bias reference voltage VREFB. And a voltage level detector 204 whose operation is controlled on / off in response to ENABLE.

Referring to the operation of the first pumping voltage detector 200 shown in FIG. 3, the divided voltage obtained by dividing the level of the back bias voltage VBB while the enable signal ENABLE is activated as logic 'high' When (DET) is lower than the level of the back bias reference voltage VREFB-the voltage level region of the back bias voltage VBB is lower than 0 V, which means that it is higher than the target level set in the absolute value. By deactivating the detection signal DET_A, the oscillation signal OSC generated by the oscillation signal generator 220 does not oscillate, and thus, the pumping voltage generator 240 does not perform the charge pumping operation so that the back bias voltage is prevented. The operation to generate (VBB) stops. That is, the state in which the divided voltage DET dividing the level of the back bias voltage VBB is lower than the level of the back bias reference voltage VREFB means that the level of the back bias voltage VBB is sufficiently low. The level of the bias voltage VBB is controlled so as not to be lowered anymore.

On the contrary, when the enable signal ENABLE is logic 'high', the divided voltage DET which divides the level of the back bias voltage VBB is higher than the level of the back bias reference voltage VREFB. Since the voltage level region of the back bias voltage VBB is lower than 0 V, it means a state lower than the target level set at the absolute value. When the voltage level region of the back bias voltage VBB is lower, the oscillation signal generator 220 activates the level detection signal DET_A. The generated oscillation signal OSC is oscillated, and accordingly, the pumping voltage generator 240 performs the charge pumping operation to generate the back bias voltage VBB. That is, the state in which the divided voltage DET dividing the level of the back bias voltage VBB is higher than the level of the back bias reference voltage VREFB means that the level of the back bias voltage VBB is not sufficiently low. The level of the back bias voltage VBB is controlled to be lower.

In addition, when the enable signal ENABLE is deactivated to logic 'low', the voltage is detected because the detection signal DET_A remains inactive regardless of what level the divide voltage DET has. It does not perform the operation.

Although not directly shown in the drawings, the circuit configuration of the differential amplification type detecting the level of the boost voltage VPP is very similar to that of the differential amplification type detecting the level of the back bias voltage VBB shown in FIG. It has a similar form, only some circuit configuration changes, and the essential operation remains the same, which will not be described in more detail here.

FIG. 4 is a circuit diagram illustrating in detail a second pumping voltage detector among components of a pumping voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention.

For reference, the second pumping voltage detector illustrated in FIG. 4 is a circuit diagram on the assumption that the pumping voltage PUMPING_VOL is the back bias voltage VBB.

Referring to FIG. 4, the second pumping voltage detector 210 includes first and second PMOS transistors P1 and P2 between a core voltage VCORE terminal and a ground voltage VSS terminal, and includes first and second PMOS transistors. The voltage output from the connection node DET of the transistors P1 and P2 is driven to generate an output signal DET_B of the back bias voltage VBB. At this time, a voltage applied to the connection node DET is outputted, and the operation is further provided with a NAND gate NAND and an inverter INV controlled on / off in response to the enable signal ENABLE.

Here, the first PMOS transistor P1 controls the connection of the source-drain-connected core voltage VCORE terminal and the connection node DET in response to the ground voltage VSS input to the gate. The second PMOS transistor P2 controls the connection of the source-drain connection node DET and the ground voltage VSS terminal in response to the back bias voltage VBB input to the gate. The operation of the second pumping voltage detector 210 will be described below based on the above-described configuration.

First, the first and second PMOS transistors P1 and P2 are MOS resistors, respectively, according to the level of the back bias voltage VBB based on the first PMOS transistor P1 whose resistance value is determined according to the ground voltage VSS. The level of the voltage applied to the connection node DET is changed using the second PMOS transistor P2 whose resistance value is changed. At this time, the level of the voltage applied to the connection node DET is set to logic 'high' or logic 'low' based on the logic threshold voltage level of the subsequent NAND gate. It is driven and output as the output signal DET_B of the back bias voltage VBB.

For example, when the level of the back bias voltage VBB is increased in the negative direction lower than the level of the ground voltage VSS, the MOS resistance value of the second PMOS transistor P2 is increased to increase the connection node DET. The level of the voltage applied to) becomes low. At this time, when the level of the voltage applied to the connection node DET is lower than the logic threshold voltage level of the subsequent NAND gate NAND, the output signal DET_B of the back bias voltage VBB driven by the NAND gate NAND Becomes logic 'High'.

That is, the above-described second pumping voltage detector 210 may detect the back bias voltage to be detected by changing the sizes of the first and second PMOS transistors P1 and P2 for adjusting the level of the voltage applied to the connection node DET. VBB) target level can be adjusted.

Therefore, the target level of the back bias voltage VBB to be detected is first determined, and the first and second PMOS transistors (transition) can be transitioned at a timing corresponding to the determined target level. A method of adjusting the size of P1, P2) is used.

The above-described operation detects the level of the back bias voltage VBB to change the voltage level of the connection node DET. However, the result is transmitted to the output signal DET_B of the back bias voltage VBB. This is only possible when the enable signal ENABLE is disabled with logic 'low'. That is, when the enable signal ENABLE is activated with logic 'high', the voltage detection result has no meaning because the output signal DET_B of the back bias voltage VBB is forcibly deactivated.

Although not directly shown in the drawings, the configuration of the circuit for detecting the boosted voltage VPP generated through the charge pumping operation has a form very similar to that of the circuit for detecting the back bias voltage shown in FIG. Since only the circuit configuration form of is changed and the essential operation remains in the same state, it will not be described in more detail here.

FIG. 5 is a circuit diagram illustrating in detail an oscillation signal generation unit among components of a pumping voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention illustrated in FIG. 2.

Referring to FIG. 5, the oscillation signal OSC is delayed by a set first time in response to an output signal DET_A of the first pumping voltage detector 200 or an output signal DET_B of the second pumping voltage detector 210. To the first delay unit 222 for delaying the output signal, the second delay unit 224 for delaying and outputting the output signal of the first delay unit 222 by a set second time, and the enable signal ENALBE. In response, an oscillation signal output unit 226 for outputting one of the output signal of the first delay unit 222 and the output signal of the second delay unit 224 as an oscillation signal OSC.

Here, the first delay unit 222 receives the output signal DET_A of the first pumping voltage detector 200 or the output signal DET_B of the second pumping voltage detector 210 to the first input terminal, and the oscillation signal. NAND gate NAND1 for inputting (OSC) to the second input terminal to perform a negative logic operation and an output signal of NAND gate NAND1, and outputting the logic signal with its logic level as it is A plurality of first inverters INV1 and INV2 are provided to delay by the amount. Here, the time corresponding to the delay amount obtained by adding up the operation delay amount of the NAND gate NAND1 and the first delay amount will be the set delay amount of the first delay unit 222.

Also, the second delay unit 224 receives a plurality of signals output from the plurality of first inverters INV1 and INV2, outputs the logic levels in a state of being maintained as they are, and delays by a set second delay amount. 2 Inverters INV3 and INV4 are provided.

In addition, the oscillation signal output unit 226 may be one of an output signal of the plurality of first inverters INV1 and INV2 and an output signal of the plurality of second inverters INV3 and INV4 in response to the enable signal ENABLE. And first and second pass gates PG1 and PG2 for outputting an output signal of? As an oscillation signal OSC.

Referring to the operation, the oscillation signal is output by outputting the signals output from the plurality of first inverters INV1 and INV2 as oscillation signals OSC in a section in which the enable signal ENABLE is activated as logic 'high'. The period of (OSC) is such that the first delay amount is repeated twice. That is, the oscillation signal OSC having a high frequency is output in response to the enable signal ENABLE being activated with logic 'high'.

On the other hand, during the period in which the enable signal ENABLE is deactivated by logic 'low', the signals output from the plurality of second inverters INV3 and INV4 are output as the oscillation signal OSC, thereby generating the oscillation signal OSC. The period is such that the first delay amount + the second delay amount is repeated twice. That is, in response to the enable signal ENABLE being deactivated to logic 'low', the oscillation signal OSC having a low frequency is output.

As described above, according to the embodiment of the present invention, the frequency of the oscillation signal depends on whether the pumping voltage detection operation is a differential amplification type corresponding to a relatively fast operation speed or a current sensing type corresponding to a relatively slow operation speed. By varying the pumping voltage can be generated with a stable target level.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

100, 200: first pumping voltage detection unit
110, 210: second pumping voltage detection unit
120, 220: oscillation signal generator
140, 240: pumping voltage generator

Claims

A first pumping voltage detector for detecting a level of a pumping voltage based on a target level set in an enable period of the enable signal;
A second pumping voltage detector detecting a level of the pumping voltage based on a target level set in the inactivation section of the enable signal and having a relatively slower operating speed than the first pumping voltage detector;
An oscillation signal generation unit generating an oscillation signal in response to an output signal of the first or second pumping voltage detector, and varying a frequency of the oscillation signal in response to the enable signal; And
A pumping voltage generator configured to generate the pumping voltage by performing a charge pumping operation at a speed corresponding to the frequency of the oscillation signal
A semiconductor device comprising a.

The method of claim 1,
The oscillation signal generator,
Generating the oscillation signal having a relatively high frequency in an activation period of the enable signal,
And generating the oscillation signal having a relatively low frequency in the inactivation section of the enable signal.

The method of claim 2,
The first pumping voltage detector,
A semiconductor device characterized by using a pumping voltage detection method of a differential amplification type.

The method of claim 3,
The second pumping voltage detector,
A semiconductor device comprising a pumping voltage detection method of a current sensing type.

The method of claim 4, wherein
The pumping voltage is a back bias voltage.

The method of claim 4, wherein
The pumping voltage is a semiconductor device, characterized in that the boost voltage.

The method of claim 1,
The oscillation signal generator,
A first delay unit configured to delay and output the oscillation signal by a predetermined first time in response to an output signal of the first or second pumping voltage detector;
A second delay unit for delaying and outputting the output signal of the first delay unit by a predetermined second time; And
And an oscillation signal output unit for outputting one of the output signal of the first delay unit and the output signal of the second delay unit as the oscillation signal in response to the enable signal.