KR20120090397A - Solar cell and method of fabircating the same - Google Patents

Abstract

PURPOSE: A solar battery and a manufacturing method thereof are provided to improving reliability by diverting a current through a diode connected to the corresponding cell in case a defective cell generates. CONSTITUTION: A plurality of solar cells(C1-C6) comprises a window layer, a buffer layer, a light absorption layer, and a back surface electrode layer. A plurality of diode(D1, D2, D3) is formed on a substrate. A plurality of diodes is parallely connected with the plurality of solar cells. The plurality of diodes respectively comprises a first conductive layer and a second conductive layer. A connection electrode electrically interlinks the plurality of solar cells and the plurality of diodes. The connection electrode and a window layer are formed into same material.

Description

SOLAR CELL AND METHOD OF FABIRCATING THE SAME}

An embodiment relates to a solar cell and a manufacturing method thereof.

Recently, as energy demand increases, development of a solar cell converting solar energy into electrical energy is in progress.

In particular, CIGS-based solar cells, which are pn heterojunction devices having a substrate structure including a glass substrate, a metal back electrode layer, a p-type CIGS-based light absorbing layer, a high resistance buffer layer, an n-type window layer, and the like, are widely used.

In such a solar cell, a plurality of cells are formed in one panel, and the cells are connected in series.

If a failure occurs in any one of these cells, the panel is not used and is discarded.

In addition, when a shadow is caused by an external object on the solar cell panel, or when foreign matter such as impurities is attached to the solar cell panel, the shadowed or foreign matter is attached to the cell, which causes a problem that the load becomes large and overheats.

The embodiment provides a solar cell and a method of manufacturing the same, which can be used as a solar cell without deterioration even when a defective cell is generated or a shadow is generated on the solar cell panel, and a process is simplified and integrated by forming a diode on the upper surface of the substrate. .

Solar cell according to the embodiment is a substrate; A window layer on the substrate, a buffer layer on the window layer, and a light absorbing layer on the buffer layer; A plurality of solar cells in which a rear electrode layer is formed on the light absorbing layer; A plurality of diodes formed on the substrate and connected in parallel with the plurality of solar cells; And a connection electrode electrically connecting the plurality of solar cells and the plurality of diodes.

The solar cell according to the embodiment forms a cell unit including a plurality of cells on the substrate and a diode connected in parallel with the plurality of cells, and then connects each cell in series, and forms a diode between the plurality of cells.

Therefore, when one of the cells is shadowed or foreign matter is formed on the cell, the charge is formed to bypass the diode, so that a defective cell or a shadow on the solar cell panel does not cause deterioration of the solar cell. Can be used.

In addition, since a plurality of diodes are formed on one substrate, when a defective cell occurs, current may be bypassed by a diode connected in parallel with the corresponding cell, and other cells may be utilized, thereby improving reliability.

In addition, since diodes may be integrated at the edges of the upper surface of the substrate and diodes may be formed in the process of forming solar cells, the process may be simplified and productivity may be improved.

In contrast to the conventional thin film solar cell structure, since the window layer is formed to be in contact with the substrate, the refractive index difference between the air / glass / window layer is formed to have a gentle structure, thereby reducing the reflection loss of light incident to the solar cell. It is possible to provide a solar cell having improved overall conversion efficiency and preventing the window layer from being oxidized by water (H ₂ O) or the like to deteriorate electrical characteristics.

1 is a plan view illustrating a solar cell according to an embodiment.
FIG. 2 is a cross-sectional view illustrating a cross section taken along AA ′ in FIG. 1.
3 is a cross-sectional view taken along the line BB ′ of FIG. 1.
4 to 12 are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment.

In the description of the embodiments, where each substrate, layer, film, or electrode is described as being formed "on" or "under" of each substrate, layer, film, or electrode, "On" and "under" include both being formed "directly" or "indirectly" through other components. In addition, the upper or lower reference of each component is described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

12 is a plan view illustrating a solar cell according to an embodiment.

As shown in FIG. 12, the solar cell according to the embodiment includes a first cell C1, a second cell C2, a third cell C3, a fourth cell C4, a fifth cell C5, It includes a sixth cell (C6).

The back electrode layer 600 formed on the first cell C1 is electrically connected to the light absorbing layer 500 formed on the second cell C2. Therefore, the first cell C1 and the second cell C2 are electrically connected. The first cell C1, the second cell C2, the third cell C3, the fourth cell C4, the fifth cell C5, and the sixth cell C6 are electrically configured as described above. Can be connected.

The first cell C1 is electrically connected to the first bus bar 810, and the sixth cell C6 is electrically connected to the second bus bar 820.

In addition, the first bus bar 810 and the second bus bar 820 may be parallel to the first cells C1 to sixth cell C6 and formed at both ends of the substrate 100.

First, second and third diodes D1, D2, and D3 are formed on the substrate 100. The first, second, and third diodes D1, D2, and D3 may be formed in a deposition and patterning process of each layer to form the first cells C1 to 6th cell C6.

The first, second, and third diodes D1, D2, and D3 are connected in parallel with the first cells C1 to sixth cell C6. In detail, the first diode D1 is connected in parallel with the first cell C1 and the second cell C2, and the second diode D2 is parallel with the third cell C3 and the fourth cell C4. The third diode D3 may be connected to the fifth cell C5 and the sixth cell C6 in parallel.

In addition, three or more diodes may be formed. That is, the cells may be formed at positions corresponding to the first cells C1 to the sixth cell C6, respectively, and one or more cells may be connected in parallel with one diode.

The first, second, and third diodes D1, D2, and D3 are edges of the substrate 100 on which the cells C1, C2... Are not formed on the substrate 100. It may be formed in the region, but is not limited thereto.

When the first, second, and third diodes D1, D2, and D3 have a shadow on one of the cells C1, C2..., Or a foreign substance is formed on the solar panel. And a current can be diverted to the diode.

As shown, the first, second, and third diodes D1, D2, and D3 are formed on the substrate 100 in the same manner as the plurality of cells C1, C2... It can be formed in the peripheral area of the.

Hereinafter, it will be described in more detail according to the manufacturing process of the solar cell.

1 is a plan view illustrating a solar cell according to an embodiment, FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB ′ of FIG. 1. It is a cross section.

As shown, the first, second, and third diodes D1, D2, and D3 are formed in the same pattern as the plurality of cells C1, C2... The first, second, and third diodes D1, D2, and D3 may be formed under the outer frame.

Since the first cells C1 to 6th cell C6 are formed in the same shape, and the first to third diodes D1, D2, and D3 are formed in the same shape, only a part of the cross-sectional view is presented.

2 and 3, the first through holes TH1 of the region where the first cell C1 to the sixth cell C6 are formed are the first, second, and third diodes D1, It is formed at a relatively narrow interval compared to the first through holes TH1 ′ in the areas where D2 and D3 are formed.

That is, one of the first through holes TH1 in the region where the first cell C1 to the sixth cell C6 is formed is the first, second, and third diodes D1, D2, and D3. It may extend into the first through holes TH1 ′ of the formed region. That is, some of the first through holes TH1 are formed longer than other through holes so that the first through holes in the region where the first, second, and third diodes D1, D2, and D3 are formed. (TH1 ').

The window layer 200 in the region where the first, second, and third diodes D1, D2, and D3 are formed may be etched by the first through hole TH1 ′ to expose the top surface of the substrate 100. In addition, the window layer 200 may be electrically connected to the first bus bar 810 and the second bus bar 820.

In the present exemplary embodiment, the first, second, and third diodes D1, D2, and D3 are disposed to be spaced apart from each other between the first cells C1 to the sixth cell C6, but the same as the plurality of cells. It may be formed in a number and connected to each other. In addition, the number of cells connected in parallel with the diode may be different.

The first, second, and third diodes D1, D2, and D3 and the first cells C1 to 6th cell C6 may be formed of the same material in the same process. That is, the connection electrode layer 210 and the window layer 200 are formed of the same material, and the light absorbing layer 500, the first conductive layer 510, the back electrode layer 600, and the second conductive layer 610 are made of the same material. It can be formed as.

4 to 12 are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment.

4 is a diagram illustrating a substrate 100 and a window layer 200 in a region in which a plurality of cells are formed, and FIG. 5 illustrates a substrate 100 and a connection electrode layer 210 in a region in which a plurality of diodes are formed. One drawing.

4 and 5, the first cell C1, the second cell C2, the third cell C3, the fourth cell C4, the fifth cell C5, and the sixth cell C6. Preparing a substrate 100 for supporting the.

The substrate 100 may be glass, and a ceramic substrate such as alumina, stainless steel, a titanium substrate, or a polymer substrate may also be used.

Soda lime glass may be used as the glass substrate, and polyimide may be used as the polymer substrate.

In addition, the substrate 100 may be rigid or flexible.

The light blocking layer 150 may be formed in a region where the diode is formed on the upper surface of the substrate 100. Since sunlight is blocked by the light blocking layer 150, the first, second, and third diodes D1, D2, and D3 may not generate power by sunlight. The light blocking layer 150 may include a material having a light absorption rate of 50% or more, for example, a metal, or may include an opaque or translucent resin.

Next, the window layer 200 and the connection electrode layer 210 are formed on the substrate 100. The window layer 200, the connection electrode layer 210, and the light blocking layer 150 may be patterned so that the through holes TH1 and TH1 ′ may be formed to expose the top surface of the substrate 100.

The window layer 200 and the back electrode layer 600 are electrically connected to each other by the connection wiring 700.

The window layer 200 is a layer for forming a pn junction with the light absorbing layer 500. Since the window layer 200 functions as a transparent electrode on the front of the solar cell, the window layer 200 may be formed of zinc oxide (ZnO) having high light transmittance and good electrical conductivity. have.

In this case, an electrode having a low resistance value may be formed by doping aluminum to the zinc oxide.

The zinc oxide thin film that is the window layer 200 may be formed by a method of depositing using a ZnO target by RF sputtering, reactive sputtering using a Zn target, and organometallic chemical vapor deposition.

In addition, a double structure in which an indium tin oxide (ITO) thin film having excellent electro-optic properties is deposited on a zinc oxide thin film may be formed.

The connection electrode layer 210 may be formed of the same material as the window layer 200 in the same process.

4 to 6, some of the first through holes TH1 formed in the first cells C1 to 6th cell C6 are formed to be long to form the first, second, and third diodes. It may extend to a region where the D1, D2, and D3 are formed to become the through groove TH1 ′.

That is, in the same process, the first through holes TH1 ′ and the first cells C1 to the first through the regions where the first, second, and third diodes D1, D2, and D3 are formed by different patterning processes. First through holes TH1 formed in the six cells C6 may be formed.

Subsequently, as shown in FIG. 7, the high resistance buffer layer 300, the buffer layer 400, and the light absorbing layer 500 are formed on the window layer 200.

The high resistance buffer layer 300 may include zinc oxide (i-ZnO) that is not doped with impurities. The energy band gap of the high resistance buffer layer 300 is about 3.1 eV to 3.3 eV.

The buffer layer 400 formed on the high resistance buffer layer 300 may be formed of at least one layer, and cadmium sulfide (CdS) may be stacked.

In this case, the buffer layer 400 is an n-type semiconductor layer, and the light absorbing layer 500 is a p-type semiconductor layer. Thus, the light absorbing layer 500 and the buffer layer 400 form a pn junction.

That is, since the light absorption layer 500 and the window layer 200 have a large difference between the lattice constant and the energy band gap, the buffer layer 400 having the band gap in between the two materials may be inserted to form a good junction. Can be.

The light absorbing layer 500 is formed on the buffer layer 400. The light absorbing layer 500 includes an I-III-VI compound. In more detail, the light absorbing layer 500 includes a copper-indium-gallium-selenide-based (Cu (In, Ga) Se ₂ , CIGS-based) compound.

Alternatively, the light absorbing layer 500 may include a copper-indium selenide (CuInSe ₂ , CIS based) compound or a copper-gallium selenide (CuGaSe ₂ , CIS based) compound.

For example, in order to form the light absorbing layer 500, a CIG-based metal precursor film is formed on the window layer 200 by using a copper target, an indium target, and a gallium target.

Thereafter, the metal precursor film is reacted with selenium (Se) by a selenization process to form a CIGS-based light absorbing layer 500.

In addition, the light absorbing layer 500 may form copper, indium, gallium, selenide (Cu, In, Ga, Se) by co-evaporation.

The light absorbing layer 500 receives external light and converts the light into electrical energy. The light absorbing layer 500 generates photo electromotive force by the photoelectric effect.

Subsequently, as shown in FIG. 8, second through holes TH2 penetrating the light absorbing layer 300, the buffer layer 400, and the high resistance buffer layer 500 are formed.

The second through holes TH2 may be formed in a mechanical manner, and a portion of the window layer 200 is exposed.

As illustrated in FIG. 9, a transparent conductive material is stacked on the high resistance buffer layer 500 to form a window layer 600 and a connection wiring 700.

When the back electrode layer 600 is stacked on the light absorbing layer 500, the connection electrode 700 may be inserted into the second through holes TH2 to form the connection wiring 700. That is, the back electrode layer 600 and the connection wiring 700 may be formed of the same material.

The back electrode layer 600 may be formed of a conductor such as metal.

For example, the back electrode layer 600 may be formed by a sputtering process using a molybdenum (Mo) target.

This is because of high electrical conductivity of molybdenum (Mo), ohmic bonding with the light absorbing layer 500, and high temperature stability under Se atmosphere.

In addition, although not shown in the drawing, the back electrode layer 600 may be formed of at least one layer.

When the back electrode layer 600 is formed of a plurality of layers, the layers constituting the back electrode layer 600 may be formed of different materials.

Next, as shown in FIG. 10, third through holes TH3 penetrating the back electrode layer 600, the light absorbing layer 500, the buffer layer 400, and the high resistance buffer layer 300 are formed.

The third through holes TH3 may be formed in a mechanical manner, and part of the window layer 200 is exposed.

Each cell may be separated from each other by the third through holes TH3.

The high resistance buffer layer 300, the buffer layer 400, the light absorbing layer 500, and the back electrode layer 600 may be arranged in a stripe shape or a matrix shape by the third through holes TH3.

The third through holes TH3 are not limited to the above shape, but may be formed in various shapes.

Referring to FIG. 11, the peripheral area of the substrate 100 is patterned to form the first bus bar 810 and the second bus bar 820. In the patterning process, the first, second, and third diodes D1, D2, and D3 are disposed in the circumferential region of the substrate 100 on which the first cells C1 to 6th cell C6 are not formed. The cell C1 is formed to be distinguished from the sixth cell C6.

In the process of forming the window layer 200 to the back electrode layer 600, the first cell C1 to the sixth cell C6 and the first, second and third diodes D1, D2, and D3 are formed. And separated by the patterning process, the first, second, and third diodes D1, D2, and D3 may include the same layer as the first to sixth cells C6 to C6. .

That is, the first, second, and third diodes D1, D2, and D3 are formed by stacking the same layer in the process of forming the first to sixth cells C6, and by the patterning. The first and second cells C1 to C6 are formed separately from each other.

Next, the first bus bar 810 and the second bus bar 820 are formed to be connected to the window layer 200.

A first bus bar 810 is formed in the first cell C1, and a second bus bar 820 is formed in the sixth cell C6. The first bus bar 810 may be connected to the (+) electrode, and the second bus bar 820 may be connected to the (-) electrode.

Next, a portion of the region where the first through holes TH1 are not formed is etched to form first, second, and third diodes D1, D2, and D3. The first, second, and third diodes D1, D2, and D3 may include the same layer as the first to sixth cells C6 to C6. That is, the first, second, and third diodes D1, D2, and D3 are formed by stacking the same layer in the process of forming the first to sixth cells C6, and during the etching process. As a result, the first cell C1 to the sixth cell C6 are formed separately.

The first bus bar 810 and the second bus bar 820 are the light absorbing layer 300, the buffer layer 400, the high resistance buffer layer 500, and the window layer 600 formed at the end of the substrate 100. By removing a portion of the, it may be formed after exposing the window layer 200.

By the above configuration, the current flows through the cells C1, C2, C3 ... in general, but the shadow of any one of the cells C1, C2, C3 ... When foreign matter is formed on the solar cell panel, the corresponding cell in which the failure occurs is operated as a passive device, that is, a resistor, rather than an active device generating power, and thus counter electromotive force is generated in the cell.

Therefore, a conduction voltage is applied to the diode connected to the cell so that current flows through the diode, not the cell. That is, the current is bypassed through the first, second, and third diodes D1, D2, and D3.

For example, if the third cell C3 has a shadow or a failure, the resistance is increased in the shadowed cell or the cell in which the failure occurs.

Therefore, in this case, charge is transferred from the second bus bar 820 through the sixth cell C6, the fifth cell C5, and the second diode D2. The cell moves to one cell C1 and moves through the first bus bar 810.

In addition, when the shadow or the failure occurs in the fourth cell (C4) is operated as described above.

If a shadow or a defect occurs in any one of the third cell C3 and the fourth cell C4, the current flow may be as described above.

Accordingly, the first cell C1, the second cell C2 is the first cell unit, the third cell C3, the fourth cell C4 is the second cell unit, the fifth cell C5, The sixth cell C6 can be thought of as being bundled into a third cell unit.

That is, when the shadow is or a defect occurs in the first cell unit, a current flows through the first diode D1, and when the shadow or a defect occurs in the second cell unit, the second diode D2 is generated. When a current flows through the third cell unit and a shadow occurs or a defect occurs, the current flows through the third diode D3.

The first, second, and third diodes D1, D2, and D3 may be disposed on an upper surface of the substrate 100 and may be formed in an outer corner region.

In the solar cell according to the embodiment described above, when one of the cell units has a shadow or a foreign substance is formed on the cell unit, a defective cell is generated by forming a current to bypass the diode connected to the cell. In addition, even if a shadow occurs on the solar panel can use the solar cell without deterioration.

In addition, since the diode is formed inside the module, not the junction box, that is, the edge of the upper surface of the substrate, integration of the device is possible.

First, second and third diodes D1, D2, and D3 are formed on the substrate 100. Since the first, second, and third diodes D1, D2, and D3 may be formed in a deposition and patterning process of each layer for forming the first to sixth cells C6, the process may be performed. It is simplified.

In addition, since a plurality of diodes are formed in one module, even if an error occurs in any one of the plurality of solar cells in the module, current flows through the diode connected to the corresponding cell, so that other cells normally operating in the same module are available. .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (9)

Board;
A window layer on the substrate, a buffer layer on the window layer, and a light absorbing layer on the buffer layer; A plurality of solar cells in which a rear electrode layer is formed on the light absorbing layer;
A plurality of diodes formed on the substrate and connected in parallel with the plurality of solar cells; And
And a connection electrode electrically connecting the plurality of solar cells and the plurality of diodes. The method of claim 1,
The plurality of diodes are formed in the edge (edge) area of the substrate. The method of claim 1,
The plurality of solar cells include a back electrode layer, a light absorbing layer, a window layer. The method of claim 1,
The connection electrode and the window layer is a solar cell formed of the same material. The method of claim 3,
Each of the plurality of diodes,
A first conductive layer; And
Solar cell comprising a second conductive layer. The method of claim 5,
The first conductive layer is formed of the same material as the light absorbing layer of the plurality of solar cells,
The second conductive layer is a solar cell formed of the same material as the back electrode layer of the plurality of solar cells. The method of claim 1,
Each of the plurality of diodes is a solar cell connected in parallel with one or more of the solar cell. The method of claim 1,
And a first bus bar and a second bus bar electrically connected to the plurality of solar cells and having opposite polarities. The method of claim 8,
The first bus bar and the second bus bar are formed in the peripheral region of the substrate.

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