KR20120089835A - Sputtering target, semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A sputtering target, a semiconductor device, and a semiconductor device manufacturing method are provided to obtain a semiconductor device with superior adhesion and operating characteristics while restricting the diffusion of Cu included in a Cu wiring layer. CONSTITUTION: A sputtering target comprises Cu alloy which includes Mn of 1.5-5.0atomic%, Mg amounting to 0.3-2.1 of (Mg atomic%)/(Mn atomic%), C of 10wtppm or less, and O2 of 2wtppm or less. A semiconductor device manufacturing method comprises the steps of: forming gate electrode layers(21,41) on substrates(20,40), forming gate insulating layers(22,42) on the gate electrode layers, forming a semiconductor layer on the gate insulating layers, forming a Cu alloy layer(27) on the semiconductor layer with a sputtering method using the sputtering target, and forming source electrodes(28,46) and drain electrodes(29,47) on the Cu alloy layer.

Description

SPUTTERING TARGET, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TECHNICAL FIELD This invention relates to a sputtering target, a semiconductor device, and the manufacturing method of a semiconductor device.

As a conventional technique, a sputtering target material containing 0.1 to 5 atomic% of Mg, further 0.1 to 11 atomic% of one or two kinds of Mn and Al, and 0.00 to 0.1 atomic% of P as necessary It is known (for example, refer patent document 1).

This sputtering target material is used for the sputtering method which forms a copper alloy wiring film in the glass substrate surface of a flat panel display, and the copper alloy wiring film formed by this sputtering method reduces the variation of the specific resistance in the position on a glass substrate.

Patent Document 1: Japanese Patent Application Publication No. 2010-53445

However, as for the sputtering target material of patent document 1, evaluation of the copper alloy film described is evaluation of the specific resistance distribution, adhesiveness, and the presence or absence of hillock generation only in the sample in which the copper alloy was formed on the glass substrate. That is, the characteristic evaluation in the state which formed the Si semiconductor layer on the glass substrate is not made, and the possibility of using in the state which formed the source electrode and the drain electrode is unclear.

Therefore, an object of this invention is to provide the semiconductor device excellent in adhesiveness and operating characteristics, its manufacturing method, and the sputtering target used for manufacture of this semiconductor device, suppressing the diffusion to the surroundings of Cu contained in a Cu wiring layer. do.

The present invention, in order to achieve the above object, Mn of 1.5 atomic% or more and 5.0 atomic% or less, Mg of 0.3 or more and 2.1 or less, Mg of 10% or more and 10wtppm represented by (atomic% of Mg) / (atomic% of Mn) A sputtering target formed by using a Cu alloy comprising C or less and ₂ wt% or less of O ₂ is provided.

This invention provides the manufacturing method of the semiconductor device using the said sputtering target in order to achieve the said objective.

In order to achieve the above object, the present invention provides a process for forming a gate electrode film on a substrate, a process of forming a gate insulating film on the gate electrode film, a process of forming a semiconductor film on the gate insulating film, and a sputtering target. Provided are a method of manufacturing a semiconductor device including a step of forming a Cu alloy film on a semiconductor film by a used sputtering method, and a step of forming a source electrode and a drain electrode on the Cu alloy film.

The method for manufacturing the semiconductor device preferably includes a step in which the semiconductor film is an amorphous silicon layer, and the step of forming the semiconductor film includes a step of forming a silicon oxide film on the surface of the amorphous silicon film.

It is preferable that the film thickness of a silicon oxide film is 1 nm or more and 2 nm or less, and the ratio represented by (atomic% of Mg) / (atomic% of Mn) is 0.3 or more and 0.7 or less in the manufacturing method of the said semiconductor device.

It is preferable that the film thickness of a silicon oxide film is more than 2 nm and 3 nm or less, and the ratio represented by (atomic% of Mg) / (atomic% of Mn) is more than 0.7 and 1.5 or less in the manufacturing method of the said semiconductor device.

It is preferable that the film thickness of a silicon oxide film is more than 3 nm and 4 nm or less, and the ratio represented by (atomic% of Mg) / (atomic% of Mn) is more than 1.5 and 2.1 or less in the manufacturing method of the said semiconductor device.

It is preferable that the manufacturing method of the said semiconductor device includes the process of forming a diffusion barrier layer in the boundary of a Cu alloy film and an oxide film by heat-processing.

The present invention, in order to achieve the above object; A gate electrode film formed on the substrate; A gate insulating film formed on the gate electrode film; An amorphous silicon film formed on the gate insulating film; A silicon oxide film formed on the amorphous silicon film; A Cu alloy film formed on the silicon oxide film and including Mn of 1.5 atomic% or more and 5.0 atomic% or less, and the ratio represented by (atomic% of Mg) / (atomic% of Mn) of 0.3 or more and 2.1 or less Mg; ; A semiconductor device having a source electrode and a drain electrode formed on a Cu alloy film is provided.

According to this invention, the semiconductor device excellent in adhesiveness and operation characteristics, the manufacturing method, and the sputtering target used for manufacture of this semiconductor device can be provided, suppressing the diffusion to the surroundings of Cu contained in a Cu wiring layer.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing of the principal part of the sample produced for adhesive evaluation.
In FIG. 2, (a) is sectional drawing of the principal part of the TFT element produced for operation characteristic evaluation, (b) is sectional drawing of the principal part of the TFT element which concerns on the comparative example 7. In FIG.
3 is a schematic view showing a method of measuring operating characteristics of a TFT element.
4 is a graph showing the measured V _G -I _d .

[Summary of Embodiment] The sputtering target according to the embodiment has a ratio of Mn of 1.5 atomic% or more and 5.0 atomic% or less and Mg of 0.3 or more and 2.1 or less, expressed by (atomic% of Mg) / (atomic% of Mn). And a Cu alloy containing 10 wtppm or less of C and 2 wtppm or less of O ₂ .

In addition, the manufacturing method of the semiconductor device which concerns on embodiment advances using the said sputtering target.

Moreover, the semiconductor device which concerns on embodiment is a board | substrate; A gate electrode film formed on the substrate; A gate insulating film formed on the gate electrode film; An amorphous silicon film formed on the gate insulating film; A silicon oxide film formed on the amorphous silicon film; A Cu alloy film formed on the silicon oxide film and including Mn of 1.5 atomic% or more and 5.0 atomic% or less, and the ratio represented by (atomic% of Mg) / (atomic% of Mn) of 0.3 or more and 2.1 or less Mg; ; A source electrode and a drain electrode formed on the Cu alloy film are provided.

(Effect of Embodiment) According to this embodiment, the semiconductor device which is excellent in adhesiveness and operation characteristics, and its manufacturing method, and the sputtering target used for manufacture of this semiconductor device are suppressed the diffusion to the surroundings of Cu contained in a Cu wiring layer. Can be provided.

Hereinafter, the Example of this embodiment is described.

Example 1 (Method for Producing Sputtering Target)
BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing of the principal part of the sample produced for adhesive evaluation. First, the some sputtering target from which a composition differs was produced. The composition of the produced sputtering target is as Table 1 below.

Further, in Examples 1 to 12, the sputtering target has a ratio represented by Mn of 1.5 atomic% or more and 5.0 atomic% or less and (atomic% of Mg) / (atomic% of Mn) of 0.3 or more and 2.1 or less. and Mg, and the condition that is fabricated using a Cu alloy containing C and O ₂ under the following 2wtppm 10wtppm. In Comparative Examples 1 to 6, the sputtering target is produced under conditions different from the above conditions.

In the manufacturing method of a sputtering target, a Cu-Mn-Mg alloy is produced by mix | blending an oxygen-free copper (pure Cu) of purity 99.99 mass% with Mn and Mg so that it may become a predetermined | prescribed compounding (mother alloy preparation) fair). Next, this mother alloy is melted in an alumina crucible in an Ar gas atmosphere to form a molten metal (mold production step). Next, this molten metal is injected into a mold to prepare a base material (ingot) of the sputtering target (casting step). Then, the hot rolling process using a rolling roll is given to this base material (hot rolling process). Then, the cold rolling process using a rolling roll is given to the base material to which the hot rolling process was performed (cold rolling process). Then, heat treatment is performed on the base material subjected to cold rolling (heat treatment step). Next, a cutting process is performed so that the base material to which the heat processing progressed may become a target size (cutting process). By the said manufacturing process, the disk-shaped sputtering target of (phi) 100 mm x 5 mm was produced.

Next, the some sample 1 provided with the Cu alloy film formed using the said sputtering target was produced. Hereinafter, the structure of the sample 1 is demonstrated.

(Configuration summary of sample (1))
As shown in FIG. 1, the sample 1 includes a glass substrate 10, a gate insulating film 11 formed on the glass substrate 10, and amorphous silicon (hereinafter, a −) formed on the gate insulating film 11. hereinafter abbreviated as Si) film 12 and a, a-Si film (formed on a 12), n ⁺ a-Si film 13, and, n ⁺ a-Si film (13, formed on a) Si oxide film 14 and And the Cu alloy film 15 formed on the Si oxide film 14 and the pure Cu film 16 formed on the Cu alloy film 15. The Cu alloy film 15 and the pure Cu film 16 form a Cu wiring layer.

The glass substrate 10 is a glass substrate used for flat panel displays, such as a liquid crystal monitor, a plasma display, an organic electroluminescent (EL) display, an inorganic EL display, for example. The thickness of this glass substrate 10 is 700 micrometers.

The gate insulating film 11 is a SiN (silicon nitride) film formed by CVD (Chemical Vapor Deposition) method. The film thickness of this gate insulating film 11 is 350 nm.

The a-Si film 12 is formed by the CVD method. The film thickness of this a-Si film 12 is 180 nm.

The n ⁺ a-Si film 13 is formed by the plasma CVD method. Specifically, for example, a silane gas (SiH ₄ ), a PH ₃ gas containing a doping element of P, and a balance gas of H ₂ are injected into the chamber to generate plasma by the plasma CVD method to generate a glass substrate 10. The n ⁺ a-Si film 13 is formed by forming P-doped a-Si: H (amorphous silicon hydride) on the Nm).

The Si oxide film 14 is formed by irradiating an n ⁺ a-Si film 13 with oxygen plasma. The irradiation time of the oxygen plasma is 60 seconds. The film thickness of this Si oxide film 14 is 1 nm.

The Cu alloy film 15 is formed by the sputtering method using the sputtering target shown in Table 1. The film thickness of this Cu alloy film 15 is 50 nm.

Specifically, the sputtering method was advanced under the following conditions.
DC power: 600 W
Discharge Gas Type: Ar
Gas pressure: 0.5 Pa
Heating temperature of glass substrate: room temperature (no heating)

Pure Cu film | membrane 16 is formed by the sputtering method using the sputtering target made from pure Cu of 99.99 mass% of purity. The film thickness of this pure Cu film 16 is 300 nm. In addition, a sputtering method shall advance so that each Cu alloy film shown below may become a composition similar to the sputtering target used for the sputtering method.

Specifically, the sputtering method was advanced under the following conditions.
DC power: 600 W
Discharge Gas Type: Ar
Gas pressure: 0.5 Pa
Heating temperature of glass substrate: room temperature (no heating)

[Evaluation of Adhesiveness of Sample 1]
The adhesive evaluation of the some sample 1 produced using the said sputtering target was performed. The results of the adhesion evaluation are shown in Table 2 below. In addition, the adhesive evaluation of the sample 1 advanced for each sample 1 provided with the Si oxide film 14 from which the film thickness differs formed by changing the irradiation time of oxygen plasma. The film thickness of this Si oxide film 14 is 1 nm (irradiation time 60 seconds), 1.5 nm (irradiation time 90 seconds), 2 nm (irradiation time 120 seconds), 2.5 nm (irradiation time 200 seconds), 3 nm (irradiation). 7 types of time 300 second), 3.5 nm (irradiation time 500 second), and 4 nm (irradiation time 900 second). In addition, the film thickness measurement of the Si oxide film 14 shown below and the Si oxide film 25 mentioned later was advanced using the spectroscopic ellipsometry.

The adhesive evaluation method was advanced based on JIS-K5600. First, 25 2 mm <2> squares (cells) are drawn to the pure Cu film | membrane 16 of the sample 1 by 5 * 5. Next, the adhesive tape (# 3305, manufactured by 3M Company) was attached to the pure Cu film 16 and peeled off, and the adhesion between the Cu wiring layer and the a-Si film 23 was evaluated. That is, since the Cu wiring layer is comprised from the pure Cu film | membrane 16 and the Cu alloy film | membrane 15, and the Si oxide film | membrane 14 is formed by a part of a-Si film | membrane 12, Cu wiring layer as an adhesive evaluation is shown. The evaluation of adhesion to the a-Si film 23 and the results are the same.

As for the criterion of adhesive evaluation, (circle) and the case of peeling of less than 1 space were (circle) and the case of peeling of 1 or more spaces and less than 5 spaces (triangle | delta) and the case of peeling of 5 spaces or more were made into x for the case where it was not peeled at all. Next, the TFT (Thin Film Transistor) element as a semiconductor element is formed using the sputtering target which has a composition of Table 1, and the operation characteristic evaluation of this TFT element is demonstrated.

(Configuration overview of the TFT element)
Fig. 2A is a sectional view of a main part of a TFT device fabricated for evaluating operating characteristics, and Fig. 2B is a sectional view of a main part of a TFT device according to Comparative Example 7. Figs. First, the structure of the TFT element 2 produced for evaluating operating characteristics will be described. Below, the part mainly different from the sample 1 is demonstrated.

As shown in Fig. 2A, the TFT element 2 includes a glass substrate 20, a gate electrode film 21, a gate insulating film 22, an a-Si film 23 as a semiconductor film, , n ⁺ a-Si film 24, Si oxide film 25, diffusion barrier layer 26, Cu alloy film 27, source electrode film 28, drain electrode film 29, And the protective film 30 is comprised. The TFT elements 2 of Examples 1 to 12 and Comparative Examples 1 to 6 shown in Table 2 were changed by changing the composition of the sputtering target used to form the Cu alloy film 27 of the TFT element 2. Produced.

As shown in FIG. 2B, the TFT element 4 according to Comparative Example 7 has a glass substrate 40, a gate electrode film 41, a gate insulating film 42, and an a-Si film 43. ), An n ⁺ a-Si film 44, a Mo barrier film 45, a source electrode film 46, a drain electrode film 47, and a protective film 48. The TFT element 4 includes a Mo barrier film 45 instead of the Si oxide film 25, the diffusion barrier layer 26, and the Cu alloy film 27. Hereinafter, the manufacturing method of the TFT element 2 and the TFT element 4 is demonstrated.

(Manufacturing method of TFT element 2)
First, the gate electrode film 21 is formed on the glass substrate 20 by sputtering. This glass substrate 20 is the same glass substrate as the glass substrate 10 of the sample 1. The gate electrode film 21 is a chromium (Cr) film. The film thickness of the gate electrode film 21 is 300 nm. In addition, in order to simplify the manufacture of TFT elements according to the Examples and Comparative Examples, patterning of the gate electrode film, the gate insulating film, the a-Si film and the n ⁺ a-Si film is omitted. In addition, as shown in Table 2, the TFT element 2 is manufactured with a plurality of TFT elements 2 depending on the composition of the sputtering target and the kind of the film thickness of the Si oxide film.

Next, the gate insulating film 22 is formed on the gate electrode film 21 by the CVD method. The gate insulating film 22 is formed to have the same composition and film thickness as the gate insulating film 11 of the sample 1.

Next, an a-Si film 23 is formed on the gate insulating film 22 by the CVD method. This a-Si film 23 is formed to have the same composition and film thickness as the a-Si film 12 of the sample 1.

The n ⁺ a-Si film 24 is formed by the plasma CVD method under the same conditions as the formation of the n ⁺ a-Si film 13 in the sample 1. This n ⁺ a-Si film 24 is formed so as to have the same composition and film thickness as the n ⁺ a-Si film 13 of the sample 1.

Next, an oxygen plasma is irradiated on the surface of the n ⁺ a-Si film 24 to form an Si oxide film 25. The Si oxide film 25 is formed to have seven kinds of film thicknesses shown in Table 2 according to the irradiation time of the oxygen plasma.

Next, the Cu alloy film 27 is formed by the sputtering method using the sputtering target provided with the composition shown in Table 1. As shown in FIG. The Cu alloy film 27 is formed to have the same film thickness as the Cu alloy film 15 of the sample 1.

Specifically, the sputtering method was advanced under the following conditions.
DC power: 600 W
Discharge Gas Type: Ar
Gas pressure: 0.5 Pa
Heating temperature of glass substrate: room temperature (no heating)

Next, a pure Cu film is formed on the Cu alloy film 27 by the sputtering method using the sputtering target made of pure Cu. The pure Cu film is formed to have the same composition and film thickness as the pure Cu film 16 of the sample 1.

Specifically, the sputtering method was advanced under the following conditions.
DC power: 600 W
Discharge Gas Type: Ar
Gas pressure: 0.5 Pa
Heating temperature of glass substrate: room temperature (no heating)

Next, a resist pattern for forming the source electrode film and the drain electrode film by a photolithography method is formed on the pure Cu film, and by the wet etching method, the pure Cu film and the Cu alloy film (using the resist pattern as a mask). 27). Subsequently, a part of the Si oxide film 25, the n ⁺ a-Si film 24, and the a-Si film 23 is patterned by dry etching.

In the patterned pure Cu film, one side becomes the source electrode film 28 and the other side becomes the drain electrode film 29.

Next, the protective film 30 is formed on the a-Si film 23, the source electrode film 28, and the drain electrode film 29 by CVD, and then heat treatment at 300 ° C. for 30 minutes in vacuum. Proceed. By this heat treatment, the diffusion barrier layer 26 is formed at the boundary between the Cu alloy film 27 and the Si oxide film 25 to obtain the TFT element 2. This protective film 30 is a Si oxide film. In addition, the film thickness of the protective film 30 is 500 nm.

In addition, the diffusion barrier layer 26 is formed by heat treatment in which Mn is integrated at the boundary between the Cu alloy film 27 and the Si oxide film 25. By accumulation of this Mn, diffusion of Mg contained in the Cu alloy film 27 into the Si oxide film 25 is suppressed. Therefore, since the diffusion barrier layer 26 suppresses the diffusion of Mg into the Si oxide film 25, the diffusion barrier layer 26 suppresses the loss of the Si oxide film 25 while suppressing the diffusion of Cu.

In addition, the channel region 31 of the TFT element 2 is formed in the a-Si film 23 between the source electrode film 28 and the drain electrode film 29, as shown in Fig. 2A. . The channel region 31 has a channel length L of 10 mu m and a channel width substantially perpendicular to the channel length of 100 mu m.

(Manufacturing method of TFT element 4 of Comparative Example 7)
First, the gate electrode film 41 is formed on the glass substrate 40 by sputtering. This glass substrate 40 is the same glass substrate as the glass substrate 20 of the TFT element 2. The gate electrode film 41 is formed to have the same composition and film thickness as the gate electrode film 21 of the embodiment.

Next, the gate insulating film 42 is formed on the gate electrode film 41 by the CVD method. This gate insulating film 42 is formed to have the same composition and film thickness as the gate insulating film 22 of the TFT element 2.

Next, an a-Si film 43 is formed on the gate insulating film 42 by the CVD method. This a-Si film 43 is formed to have the same composition and film thickness as the a-Si film 23 of the TFT element 2.

The n ⁺ a-Si film 44 is formed by the plasma CVD method under the same conditions as in the formation of the n ⁺ a-Si film 24 of the TFT element 2. This n ⁺ a-Si film 44 is formed so as to have the same composition and film thickness as the n ⁺ a-Si film 24 of the TFT element 2.

Next, Mo (molybdenum) is deposited on the n ⁺ a-Si film 44 by the sputtering method to form the Mo barrier film 45. The Mo barrier film 45 has a film thickness of 30 nm.

Specifically, the sputtering method was advanced under the following conditions.
DC power: 600 W
Discharge Gas Type: Ar
Gas pressure: 0.5 Pa
Heating temperature of glass substrate: room temperature (no heating)

Next, a pure Cu film is formed on the Mo barrier film 45 by the sputtering method using the sputtering target made from pure Cu. This pure Cu film is formed so as to have the same composition and film thickness as the pure Cu film (the source electrode film 28 and the drain electrode film 29) of the TFT element 2.

Next, a resist pattern for forming the source electrode film and the drain electrode film is formed on the pure Cu film by the photolithography method, and the pure Cu film is patterned by using the resist pattern as a mask by the wet etching method. Subsequently, a part of the n ⁺ a-Si film 44 and the a-Si film 43 is patterned by dry etching.

The patterned net Cu film has a source electrode film 46 on one side and a drain electrode film 47 on the other side.

Next, the protective film 48 is formed on the a-Si film 43, the source electrode film 46, and the drain electrode film 47 by CVD, and then heat treated at 300 ° C. for 30 minutes in a vacuum. The TFT element 4 of the comparative example 7 is obtained. This protective film 48 is formed so as to have a composition and a film thickness of the protective film 30 of the TFT element 2.

In addition, the channel region 49 of the TFT element 4 is formed in the a-Si film 43 between the source electrode film 46 and the drain electrode film 47, as shown in Fig. 2B. . In this channel region 49, the channel length L is 10 mu m, and the channel width substantially orthogonal to the channel length is 100 mu m.

Moreover, the electrode pad (not shown) which makes the measurement probe contact the gate electrode film, the source electrode film, and the drain electrode film of the TFT element 2 and the TFT element 4 is provided.

[Operation Characteristic Evaluation]
3 is a schematic view showing a method of measuring operating characteristics of a TFT element. Below, the mobility of the carrier mentioned later as an operation characteristic is measured. In order to measure the operating characteristics of the TFT element 2, as shown in FIG. 3, an ammeter 51, an ammeter 53, an ammeter 54, a power source 52, and a power source 55 are connected.

Specifically, the source electrode film 28 of the TFT element 2 is grounded. In addition, an ammeter 51 for measuring a current input to the source electrode film 28 is connected to the source electrode film 28. The drain electrode film 29 is connected to a power supply 55 for supplying a voltage V _DS . In this power supply 55, an ammeter 54 connected to the drain electrode film 29 is connected to a terminal on the drain electrode film 29 side, and the terminal on the opposite side to the drain electrode film 29 side is grounded. In addition, an ammeter 53 is connected to the gate electrode film 21, one side of which is connected to a power supply 52 that supplies the gate voltage V _G , and the other side of which is connected to the gate electrode film 21.

In the operation characteristic measurement method, first, a constant voltage V _DS is supplied from the power supply 55 between the source electrode film 28 and the drain electrode film 29, and further, from the power supply 52, the gate electrode film ( The gate voltage V _G is supplied to 21. When the gate voltage V _G is supplied, the channel region 31 is formed in the a-Si film 23 when the voltage becomes equal to or higher than the threshold voltage V _th determined from the structure of the TFT element 2. The current 50 (I _d ) flows from the source electrode film 28 to the drain electrode film 29.

In this operation characteristic measurement, although the patterning of the gate electrode film 21 is abbreviate | omitted, the electric current 50 between the source electrode film 28 and the drain electrode film 29 passes through the some gate insulating film 22. Since the gate electrode film 21 flowed as a leakage current, a large voltage V _DS was supplied so that this leakage current was negligibly small and measured in a region where the error of leakage current was small.

In the saturation region in the case where this voltage V _DS was supplied, equation (1) shown below was established, and saturation mobility (μ) was obtained by equation (2) derived therefrom.

Here, the saturation mobility (mobility: μΩ㎝), the equation (2) again plot a plot of V _G -I _d obtained from the V _G -√I as _d, and the linear portion of the V _G -√I _d We saved from slope.

This saturation mobility μ represents the conductivity of the current from the source electrode to the drain electrode, and is related to the charge / discharge rate to the transparent electrode for driving the liquid crystal.

4 is a graph showing the measured V _G -I _d . 4, the vertical axis represents current I _d (A), and the horizontal axis represents gate voltage V _G (V). As shown in FIG. 4, also in the TFT element 2 of both an Example and a comparative example, the operation characteristic of a typical TFT element was obtained.

Table 2 shows the results of this operation characteristic evaluation. The evaluation criteria are 0.63 μΩ, which is 90% or more and less than 100% when the mobility characteristic of the TFT element 4 of Comparative Example 7 shown in FIG. 2B is less than 0.63 μΩcm that is less than 90%. In the case of cm or more and less than 0.7 μΩcm,?, In the case of 0.7 μΩcm or more and less than 0.77 μΩcm that is 100% or more and less than 110%, ○, in the case of 0.77 μΩcm or more that is 110% or more, ◎.

From Table 2, the composition of the Cu alloy film 27 whose evaluation of both adhesion and mobility is good (evaluation of whether ◎ or ○) is divided by the film thickness of the Si oxide film 25, the film of the Si oxide film 25. When the thickness is 1 nm or more and 2 nm or less, in Examples 1, 2, 5, 6, 9, and 10, the ratio (Mg atomic% / Mn atomic%) is 0.3 or more and 0.7 or less.

In addition, when the film thickness of the Si oxide film 25 is more than 2 nm and 3 nm or less, in Example 3, 7, 11, the ratio (Mg atomic% / Mn atomic%) becomes more than 0.7 and 1.5 or less.

In addition, when the film thickness of the Si oxide film 25 is more than 3 nm and 4 nm or less, in Example 4, 8, 12, the ratio (Mg atomic% / Mn atomic%) is more than 1.5 and 2.1 or less.

On the other hand, in Comparative Examples 1, 3, and 5 in which the ratio (Mg atomic% / Mn atomic%) is lower than 0.3, since the amount of Mg is smaller than that of Mn and the amount of residual Si oxide film 25 is large, the adhesion is good. Since the parasitic resistance component of the Si oxide film 25 is high, it is thought that mobility became a value lower than 0.7 micrometer cm which is evaluation criteria.

In Comparative Examples 2, 4, and 6, in which the ratio (Mg atomic% / Mn atomic%) is higher than 0.3, the amount of Mg is higher than that of Mn, and Mg loses the Si oxide film 25, whereby adhesion is achieved. It becomes poor, and it becomes difficult to suppress diffusion of Cu, and it is thought that it became the value with low mobility.

[Verification of Number of Abnormal Discharges]
Table 3 shown below shows the result of having measured the number of abnormal discharges which generate | occur | produced by sputtering using the sputtering target which concerns on Example 13 and Example 14, and the sputtering target which concerns on Comparative Example 7 and Comparative Example 8. Moreover, the produced sputtering target has a disk shape of (phi) 100 mm x 5 mm.

Exemplary sputtering target according to Example 13, Example 1 of the following composition: and the (Mn 1.5 at.%, Mg 0.5% by atom) as a base, and is constructed to include a 1.2wtppm 3.0wtppm, the O ₂ C. The ratio (Mg atomic% / Mn atomic%) in Example 13 is 0.33.

Exemplary sputtering target according to Example 14 is carried out the composition of Example 12: a (5 at.% Mn, Mg 10 atomic%) with a base, and is constructed to include a 1.8wtppm 9.5wtppm, the O ₂ C. The ratio (Mg atomic% / Mn atomic%) in Example 14 is 2.00.

The sputtering target according to Comparative Example 7, the composition of the embodiment example 12: the (5 at.% Mn, Mg 10 atomic%) with a base, and is constructed to include a 2.5wtppm 11wtppm, the O ₂ C. The ratio (Mg atomic% / Mn atomic%) in the comparative example 7 is 2.00.

The sputtering target which concerns on the comparative example 8 is produced based on the composition (Mn: 5 atomic%, Mg 10 atomic%) of Example 12, and contains ₂₀ wtppm of C and 4 wtppm of O2. The ratio (Mg atomic% / Mn atomic%) in the comparative example 8 is 2.00.

In Comparative Example 7 and Comparative Example 8, when producing the master alloy of the sputtering target, the Mn raw material (Mn flake) which had not been deoxidized was placed in a carbon crucible together with other raw materials, It melt | dissolved in and made into molten metal. As for the master alloy produced by this manufacturing process, compared with the mother alloy produced by the manufacturing process of an Example, carbon concentration and oxygen concentration increase.

Electron microscopy and EDX (Energy Dispersive X-ray microanalyzer) analysis of sputtering targets containing C and O _{2 show} that C is a compound phase with Mn in the sputtering target. ) And O ₂ is bonded to Mg in the sputtering target to form a foreign substance phase of MgO.

Here, in the normal discharge in sputtering, a glow discharge state in which the current and the voltage become a steady state occurs. Moreover, when a sputtering target contains a foreign material phase, an arc generate | occur | produces by abnormal discharge during sputtering, and a current and a voltage change. This generated arc causes a discharge foreign matter such as particles to be generated on the substrate forming the film. Here, the abnormal discharge times of Example 13, Example 14, Comparative Example 7 and Comparative Example 8 were measured by the detection apparatus system (arc monitor) of a sputtering apparatus.

The measuring method was a method of measuring the current and voltage applied between the substrate electrode and the cathode electrode (sputtering target side) during sputtering, and determining the occurrence of an arc and counting it. In addition, measurement conditions are as follows.
DC power: 600 W
Discharge Gas Type: Ar
Gas pressure: 0.5 Pa
Heating temperature of substrate: room temperature (no heating)
Time: 2h

As shown in Table 3, in Example 13 and Example 14, the abnormal discharge count was 0 times, twice in Comparative Example 7, and seven times in Comparative Example 8. The diameter of the sputtering target used for this measurement is 100 mm, and it is anticipated that it will increase from the said number in the sputtering target of several meters order actually used for the sputtering method. Therefore, the sputtering target is preferably containing as the following 10wtppm C, O ₂ or less 2wtppm.

(Effect of Example)
As a result, according to the present Example, the ratio represented by Mn of 1.5 atomic% or more and 5.0 atomic% or less, and the ratio represented by (atomic% of Mg) / (atomic% of Mn) is 0.3 or more and 2.1 or less Mg, and 10 wtppm or less A composition of the Cu alloy film 27 formed by using a sputtering target formed by using C and a Cu alloy containing ₂ wtppm or less of O ₂ ; By selecting the film thickness of the Si oxide film 25, the semiconductor device provided with the wiring layer which made adhesiveness and mobility characteristics compatible can be formed.

Further, according to the TFT element 2 according to the present embodiment, instead of the formation of the barrier layer using Mo or Ti used in the conventional liquid crystal panel TFT element, the a-Si film 23 is subjected to surface oxidation treatment. Since the formation of the Si oxide film 25 and the formation of the diffusion barrier layer 26 by heat treatment are performed, a significant reduction in the manufacturing cost of the liquid crystal panel can be achieved.

In addition, according to the present embodiment, since the Cu wiring layer having a lower resistance than that of the Al wiring layer used in the conventional liquid crystal panel TFT element is formed, it is possible to reduce the design cost for larger size and higher image quality of the liquid crystal panel.

In addition, according to this embodiment, in the patterning process of the source electrode film 28 and the drain electrode film 29, etching of the same type metal laminated film, such as the pure Cu film and the Cu alloy film 27, is performed, Etching by etching liquid is possible, and compared with the case of the comparative example 7 which etches a pure Cu film | membrane and Mo film | membrane, etching cost can be reduced.

In addition, according to the sputtering target according to the present embodiment, since it contains 10 wtppm or less of C and 2 wtppm or less of O ₂ , the occurrence of arc is suppressed as compared with the case of containing more than 10 wtppm of C and more than ₂ wtppm of O ₂ . It is possible to suppress generation of discharge foreign matters such as particles caused by the arc. Therefore, the yield of a semiconductor device can be improved by using the sputtering target of a present Example.

In addition, the sputtering target may contain a small amount of P. This P does not impair the mobility characteristics of the TFT element, the adhesion of the wiring film and the specific resistance, and does not cause the occurrence of film defects such as Hilllock, voids, etc., and facilitates the processing of the base material of the sputtering target. In addition, it is preferable that P is 0.1 atomic% or more and 1 atomic% or less, for example.

In addition, although the formation of the said Si oxide film used oxygen plasma, it is not limited to this, The method, such as heat processing in atmosphere containing oxygen, such as ozone and water, may be sufficient.

As mentioned above, although embodiment of this invention and its Example were described, embodiment and Example which were mentioned above do not limit invention of a claim. In addition, it should be noted that not all combinations of the features described in the embodiments and the examples are essential to the means for solving the problems of the invention.

1: sample
2: TFT element
4: TFT element
10: glass substrate
11: gate insulating film
12: a-Si film
13: n ⁺ a-Si film
14: Si oxide film
15: Cu alloy film
16: pure Cu film
20: glass substrate
21: gate electrode film
22: gate insulating film
23: a-Si film
24: n ⁺ a-Si film
25: Si oxide film
26: diffusion barrier layer
27: Cu alloy film
28: source electrode film
29: drain electrode film
30: Shield
31: channel area
40: glass substrate
41: gate electrode film
42: gate insulating film
43: a-Si film
44: n ⁺ a-Si film
45: Mo barrier film
46: source electrode film
47: drain electrode film
48: Shield
49: channel area
50: current
51: ammeter
52: power
53: ammeter
54: ammeter
55: power

Claims (9)

Mn of 1.5 atomic% or more and 5.0 atomic% or less, the ratio represented by (atomic% of Mg) / (atomic% of Mn) is 0.3 or more and Mg of not more than 2.1, C of 10 wtppm or less, and O ₂ of ₂ wtppm or less Sputtering target formed using Cu alloy containing. The manufacturing method of the semiconductor device using the sputtering target of Claim 1. The method of claim 2,
Forming a gate electrode film on the substrate;
Forming a gate insulating film on the gate electrode film;
Forming a semiconductor film on the gate insulating film;
Forming a Cu alloy film on the semiconductor film by a sputtering method using the sputtering target,
A method of manufacturing a semiconductor device comprising the step of forming a source electrode and a drain electrode on the Cu alloy film. The method of claim 3, wherein
The semiconductor film is an amorphous silicon film,
And the step of forming the semiconductor film includes a step of forming a silicon oxide film on the surface of the amorphous silicon film. The method of claim 4, wherein
The film thickness of the said silicon oxide film is 1 nm or more and 2 nm or less,
The manufacturing method of the semiconductor device whose ratio represented by said (atomic% of Mg) / (atomic% of Mn) is 0.3 or more and 0.7 or less. The method of claim 4, wherein
The film thickness of the said silicon oxide film is more than 2 nm and 3 nm or less,
The manufacturing method of the semiconductor device whose ratio represented by said (atomic% of Mg) / (atomic% of Mn) is more than 0.7 and 1.5 or less. The method of claim 4, wherein
The film thickness of the said silicon oxide film is more than 3 nm and 4 nm or less,
The manufacturing method of the semiconductor device whose ratio represented by said (atomic% of Mg) / (atomic% of Mn) is more than 1.5 and 2.1 or less. The method according to any one of claims 5 to 7,
A method of manufacturing a semiconductor device, comprising the step of forming a diffusion barrier layer at a boundary between the Cu alloy film and the oxide film by performing a heat treatment. A substrate;
A gate electrode film formed on the substrate;
A gate insulating film formed on the gate electrode film;
An amorphous silicon film formed on the gate insulating film;
A silicon oxide film formed on the amorphous silicon film;
A Cu alloy film formed on the silicon oxide film and including Mn of 1.5 atomic% or more and 5.0 atomic% or less and Mg of 0.3 or more and 2.1 or less in Mg. and;
A semiconductor device comprising a source electrode and a drain electrode formed on the Cu alloy film.

Images