KR20120076435A

KR20120076435A - Temperature sensor

Info

Publication number: KR20120076435A
Application number: KR1020100137923A
Authority: KR
Inventors: 이세원
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2010-12-29
Filing date: 2010-12-29
Publication date: 2012-07-09

Abstract

The temperature sensor selects and outputs the first to fourth reference voltages among a plurality of reference voltages in which the power voltage is divided in voltage in response to the first and second fuse signals generated according to whether the fuse is cut or not, and an external voltage. And a sensing voltage generator configured to sense a temperature of a semiconductor integrated circuit in response to the reference voltage to generate a sensing voltage insensitive to a change in PVT characteristics, and compare the sensing voltage with the first to fourth reference voltages. And a decoder configured to generate a four flag signal and a decoder to decode the first to fourth flag signals to generate a temperature code.

Description

TEMPERATURE SENSOR {TEMPERATURE SENSOR}

The present invention relates to a semiconductor integrated circuit, and more particularly to a temperature sensor.

In general, in order to meet the high performance of electronic systems such as personal computers, electronic communication devices, and the like, volatile semiconductor memory devices such as DRAMs that are mounted as memories have become increasingly high in speed and high density. In the case of a semiconductor integrated circuit mounted in a battery-operated system such as a mobile phone or a notebook computer, especially low power consumption characteristics are desperately required, efforts and researches for reducing the operating (operating) current and standby current have been actively conducted.

The data retention characteristics of DRAM memory cells, which consist of one transistor and one storage capacitor, are very sensitive to temperature. Therefore, it may be necessary to adjust the operating conditions of the circuit blocks in the semiconductor integrated circuit according to the change in the internal temperature of the semiconductor integrated circuit. For example, in the case of dynamic random access memory (DRAM) used in mobile products, a refresh period is controlled according to a change in the internal temperature of a semiconductor integrated circuit. In order to adjust the operating conditions according to the internal temperature change of the semiconductor integrated circuit, temperature sensors such as a digital temperature sensor regulator (DTSR), an analog temp sensor regulator (ATSR), and a digital temperature compensated self refresh (DTCSR) are used.

1 is a block diagram showing the configuration of a temperature sensor according to the prior art.

As shown in FIG. 1, the temperature sensor according to the related art detects an internal temperature of a semiconductor integrated circuit, and generates a sensing voltage generation unit 10 generating a sensing voltage VSENSE, a sensing voltage VSENSE, and reference voltages. And a temperature code generator 11 for generating a temperature code TCODE <1: 4> by comparing VREF <1: 4>. The temperature sensor having such a configuration compares the levels of the sensing voltage VSENSE and the reference voltages VREF <1: 4> to determine whether the internal temperature of the semiconductor integrated circuit is higher than the temperature corresponding to the level of the reference voltage VREF. Generate a temperature code (TCODE <1: 4>) containing information about. Here, the temperature codes TCODE <1: 4> adjust the refresh cycle of the semiconductor integrated circuit.

However, the temperature sensor having such a configuration causes a problem in that the voltage change amount of the sensing voltage VSENSE is generated non-linearly according to the change in the process voltage temperature (PVT) characteristic. This will prevent the temperature code (TCODE <1: 4>) from being set correctly, which can lead to incorrect adjustment of the refresh period.

Accordingly, the present invention discloses a temperature sensor which is insensitive to changes in PVT characteristics and generates a sensing voltage that changes linearly with temperature, so that the temperature code can be correctly set and the refresh cycle can be stably set.

To this end, the present invention is a reference voltage selector for selecting and outputting the first to fourth reference voltage of a plurality of reference voltage voltage distribution voltage distribution in response to the first and second fuse signal generated according to the fuse cutting A sensing voltage generation unit configured to sense a temperature of a semiconductor integrated circuit in response to an external voltage and the reference voltage to generate a sensing voltage insensitive to a change in PVT characteristics, and compare the sensing voltage with the first to fourth reference voltages. It provides a temperature sensor including a comparator for generating a first to fourth flag signal and a decoder for decoding the first to fourth flag signal to generate a temperature code.

1 is a block diagram showing the configuration of a temperature sensor according to the prior art.
2 is a block diagram showing the configuration of a temperature sensor according to an embodiment of the present invention.
3 is a circuit diagram of a sensing voltage generator included in the temperature sensor shown in FIG. 2.
Figure 4a is a graph showing a sense voltage slope of the prior art according to the temperature change.
4b is a graph showing a sensed voltage slope of the present invention according to temperature change.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a block diagram showing the configuration of a temperature sensor according to an embodiment of the present invention.

As illustrated in FIG. 2, the temperature sensor includes a fuse signal generator 1, a reference voltage selector 2, a sense voltage generator 3, a comparator 4, and a decoder 5.

The fuse signal generator 1 generates the first and second fuse signals FUSE <1: 2> according to whether the first and second fuses (not shown) are cut in response to the test mode signal TM_EN. .

The reference voltage selector 2 includes first to fourth reference values according to the first and second fuse signals FUSE <1: 2> among the plurality of reference voltages in which the power supply voltage VDD is divided by a plurality of resistors. The voltages VREF <1: 4> are selected and output. Here, the first to fourth reference voltages VREF <1: 4> selected according to the first and second fuse signals FUSE <1: 2> may be variously set according to embodiments.

As illustrated in FIG. 3, the sensed voltage generator 3 includes a driving voltage generator 30, a driver 31, and a sensed voltage output unit 32.

The driving voltage generator 30 includes a first driving voltage generator 300 and a second driving voltage generator 301.

The first driving voltage generator 300 is positioned between the power supply voltage VDD and the first node nd30, and pulls-up the first node nd30 in response to the ground voltage VSS to drive the first driving voltage DRV1. The first voltage regulating element P30 and the first node nd30 and the ground voltage VSS are disposed to adjust the level, and pull down driving the first node nd30 in response to the second reference voltage VREF2. The second voltage adjusting element P31 for adjusting the level of the first driving voltage DRV1 is included. Here, the second reference voltage VREF2 is preferably set at a level higher than the threshold voltage of the second voltage adjusting element P31.

The second driving voltage generator 301 is positioned between the power supply voltage VDD and the second node nd31, and adjusts the level of the second driving voltage DRV2 by reducing the power supply voltage VDD. Located between the resistor R30 and the second node nd31 and the ground voltage VSS, the second node nd31 is pulled down in response to the power supply voltage VDD to adjust the level of the second driving voltage DRV2. And a third voltage regulating element N30.

The driver 31 is positioned between the power supply voltage VDD and the third node nd32, and pulls up the third node nd32 in response to the first driving voltage DRV1 to adjust the level of the feedback voltage VFEED. Located between the first driving device N31, the third node nd32, and the fourth node nd33, the pullback driving of the third node nd32 in response to the second driving voltage DRV2 causes the feedback voltage VFEED. Is positioned between the second driving element N32 and the fourth node nd33 and the ground voltage VSS to adjust the level of the control element, and adjusts the driving force of the second driving element N32 to adjust the level of the feedback voltage VFEED. And a second voltage regulating resistor R31 for adjusting.

The sensing voltage output unit 32 responds to the third driving element P32 and the feedback voltage VFEED which adjust the level of the sensing voltage VSENSE by pulling up the sensing voltage VSENSE in response to the ground voltage VSS. And a fourth driving element P33 for controlling the level of the sensing voltage VSENSE by pulling down the sensing voltage VSENSE.

The operation of the temperature sensor according to the present invention will be described with reference to a case in which the power supply voltage VDD is lowered due to a change in PVT characteristics and a threshold voltage of the NMOS transistor is lowered as an example.

The reference voltage selector 2 includes first to fourth reference values according to the first and second fuse signals FUSE <1: 2> among the plurality of reference voltages in which the power supply voltage VDD is divided by a plurality of resistors. The voltages VREF <1: 4> are selected and output.

First, when the power supply voltage VDD is changed due to a change in the process voltage temperature (PVT) characteristic, the level of the first driving voltage DRV1 becomes lower than the first voltage of the first driving voltage generator 300 at the lower power supply voltage VDD. As low as the threshold voltage of the voltage adjusting element (P30). In addition, since the second reference voltage VREF2 generated by lowering the power supply voltage VDD is changed less than the voltage change amount of the power supply voltage VDD, the amount of current flowing through the second voltage regulating element P31 is changed little. The amount of decrease in voltage level of the first driving voltage DRV1 is reduced. This is because the amount of decrease in the voltage level of the second reference voltage VREF2 is smaller than that in the case where the power supply voltage VDD is not lowered, so that the amount of change in the first driving voltage DRV1 becomes smaller. This reduces the amount of change in the amount of current flowing through the first driving element N31 to reduce the level change in the feedback voltage VFEED.

Next, when the threshold voltage of the NMOS transistor is lowered due to a change in the process voltage temperature (PVT) characteristic, the threshold voltage of the third voltage regulating element N30 of the second driving voltage generator 301 which is the NMOS transistor is lowered. In this case, the amount of current flowing through the third voltage regulating element N30 is increased to lower the voltage level of the second driving voltage DRV2. In addition, since the second driving device N32 of the driving unit 31 is also an NMOS transistor, the threshold voltage is lowered to increase the amount of current flowing through the second driving device N32. In addition, the voltage level of the fourth node nd33 is increased by the increased amount of current and the second voltage regulating resistor R31, thereby reducing the gate source voltage VGS of the second driving device N32, thereby reducing the second driving device N32. Reduction of the amount of current flowing in the circuit) reduces the amount of level change in the feedback voltage (VFEED).

The comparator 4 includes a first comparator 40, a second comparator 41, a third comparator 42, and a fourth comparator 43. The first comparator 40 compares the level of the sensing voltage VSENSE with the level of the first reference voltage VREF <1> so that the sensing voltage VSENSE is lower than the first reference voltage VREF <1>. A first flag signal TFLAG <1> that is enabled at a logic high level is generated. The second comparator 41 generates a second flag signal TFLAG <2> that is enabled at a logic high level when the sensing voltage VSENSE is lower than the second reference voltage VREF <2>. The third comparator 42 generates a third flag signal TFLAG <3> that is enabled at a logic high level when the sensing voltage VSENSE is lower than the third reference voltage VREF <3>. The fourth comparator 43 generates a fourth flag signal TFLAG <4> which is enabled at a logic high level when the sensing voltage VSENSE is lower than the fourth reference voltage VREF <4>. The comparator 4 having such a configuration compares the sensing voltage VSENSE with the levels of the first to fourth reference voltages VREF <1: 4>, and compares the first to fourth flag signals TFLAG <1: 4>. ) For example, when the internal temperature of the semiconductor integrated circuit is higher than the internal temperature corresponding to the second reference voltage VREF <2> and lower than the internal temperature corresponding to the third reference voltage VREF <3>, the sensing voltage ( VSENSE) is generated at a level lower than the first and second reference voltages VREF <1: 2> and higher than the third and fourth reference voltages VREF <3: 4>. Accordingly, the first flag signal TFLAG <1> and the second flag signal TFLAG <2> are enabled at a logic high level, and the third flag signal TFLAG <3> and the fourth flag signal TFLAG < 4>) is disabled to a logic low level.

The decoder 7 generates the temperature codes TCODE <1: 4> by decoding the first to fourth flag signals TFLAG <1: 4>. Here, the temperature code TCODE <1: 4> may be implemented as a signal having a plurality of bits according to an embodiment.

4A and 4B are graphs showing a sense voltage of the prior art and a sense voltage gradient of the present invention according to temperature change.

As shown in FIG. 4A, the temperature sensor according to the related art has a change in sensing voltage VSENSE of 167 mV according to a process voltage temperature (PVT) characteristic change when a semiconductor integrated circuit operates at 150 ° C., and is illustrated in FIG. 4B. As described above, when the semiconductor integrated circuit operates at 150 ° C., the temperature sensor of the present invention can recognize that the amount of change of the sensing voltage VSENSE is 34mV according to the change of PVT characteristics. That is, it can be seen that the temperature sensor of the present invention changes linearly in the amount of change of the sensing voltage VSENSE according to the temperature change than the temperature sensor of the prior art.

As described above, the temperature sensor of this embodiment sets the temperature code TCODE <1: 4> correctly by linearly changing the voltage change amount of the sensing voltage VSENSE according to the temperature change even when the PVT characteristic changes. It is possible to set a stable refresh period.

1. Fuse signal generator 2. Reference voltage selector
3. Detection voltage generator 4. Comparator
5. Decoder 30. Driving voltage generator
31.Driver 32. Sense Voltage Output
40. First Comparator 41. Second Comparator
42. Third Comparator 43. Fourth Comparator
300. The first driving voltage generator 301. The second driving voltage generator

Claims

A reference voltage selector configured to select and output first to fourth reference voltages among a plurality of reference voltages whose power voltages are divided by voltages in response to the first and second fuse signals generated according to whether the fuse is cut or not;
A sensing voltage generator configured to sense a temperature of a semiconductor integrated circuit in response to an external voltage and the reference voltage to generate a sensing voltage insensitive to a change in PVT characteristics;
A comparator configured to generate first to fourth flag signals by comparing the sensed voltage to the first to fourth reference voltages; And
And a decoder configured to decode the first to fourth flag signals to generate a temperature code.

The method of claim 1, wherein the detection voltage generation unit
A driving voltage generator configured to generate a driving voltage for compensating for the PVT characteristic change in response to the external voltage;
A driving unit generating a feedback voltage insensitive to the PVT characteristic change in response to the driving voltage; And
And a sensing voltage output unit configured to generate the sensing voltage corresponding to a temperature change of the semiconductor integrated circuit in response to the feedback voltage and the ground voltage.

The method of claim 2, wherein the driving voltage generation unit
A first driving voltage generator configured to drive and output a first driving voltage in response to the ground voltage and the reference voltage; And
And a second driving voltage generator configured to drive and output the second driving voltage in response to the power supply voltage.

The method of claim 3, wherein the first driving voltage generator
A first voltage regulating element positioned between the power supply voltage and the first node and configured to adjust the level of the first driving voltage by pulling up the first node in response to the ground voltage; And
And a second voltage adjusting element positioned between the first node and the ground voltage and configured to adjust the first driving voltage level by pulling down the first node in response to the reference voltage.

The method of claim 3, wherein the second driving voltage generator
A first voltage regulating resistor positioned between the power supply voltage and a second node and configured to adjust the level of the second driving voltage by reducing the power supply voltage; And
And a third voltage adjusting element positioned between the second node and the ground voltage and configured to adjust the level of the second driving voltage by pulling down the second node in response to the power supply voltage.

The method of claim 2, wherein the driving unit
A first driving device positioned between the power supply voltage and a third node, the first driving device configured to adjust a level of a feedback voltage by driving the third node up in response to the first driving voltage;
A second driving device positioned between the third node and a fourth node and configured to adjust the level of the feedback voltage by pulling down the third node in response to the second driving voltage; And
And a second voltage regulating resistor disposed between the fourth node and the ground voltage to adjust the feedback voltage level by adjusting a driving force of the second driving element.

The method of claim 2, wherein the sensing voltage output unit
A third driving device configured to adjust the level of the sensed voltage by driving the sensed voltage in response to the ground voltage; And
And a fourth driving device configured to adjust the level of the sensed voltage by driving the sensed voltage down in response to the feedback voltage.

The method of claim 1, wherein the comparison unit
A first comparator comparing the sensed voltage with the first reference voltage and generating the first flag signal enabled when the sensed voltage is lower than the first reference voltage;
A second comparator comparing the sensed voltage with the second reference voltage and generating the second flag signal enabled when the sensed voltage is lower than the second reference voltage;
A third comparator comparing the sensed voltage with the third reference voltage and generating the third flag signal enabled when the sensed voltage is lower than the third reference voltage; And
And a fourth comparator for comparing the sensed voltage with the fourth reference voltage and generating the fourth flag signal enabled when the sensed voltage is lower than the fourth reference voltage.

The method of claim 1,
And a fuse signal generator configured to generate the first and second fuse signals according to whether the fuse is cut in response to a test mode signal.