KR20140081350A

KR20140081350A - Device for driving a power

Info

Publication number: KR20140081350A
Application number: KR1020120151001A
Authority: KR
Inventors: 최영경
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2012-12-21
Filing date: 2012-12-21
Publication date: 2014-07-01

Abstract

The present invention relates to a power driving device. The present invention relates to technology capable of maintaining the stability of internal power by reducing an operation current of a driver to constantly control the internal power in a semiconductor memory device. The present invention includes a voltage generating unit which generates a detection signal by comparing a reference voltage with an internal voltage, a driving unit which outputs a plurality of driving signals whose voltage levels are changed by corresponding to the detection signal, and an internal voltage driving unit which includes a plurality of internal voltage drivers to control the level of the internal voltage and controls the operation numbers of the internal voltage drivers according to the driving signals.

Description

Device for driving a power}

[0001] The present invention relates to a power supply driving apparatus, and more particularly, to a technique for reducing the operating current of a driver that constantly controls an internal power supply in a semiconductor memory device to maintain stability of an internal power supply.

Gate length and oxide thickness of a transistor (for example, a MOSFET, a metal oxide semiconductor field effect transistor) decrease as the degree of integration of a dynamic random access memory (DRAM) have. However, since the external power supply voltage continues to use a high voltage (for example, 5V), the channel electric field becomes large and reaches the breakdown voltage of the oxide film. As a result, the reliability of the transistor is deteriorated.

To solve this problem, a voltage conversion circuit (for example, 16M DRAM) for lowering the power supply voltage inside a chip is being used in earnest. Here, in a semiconductor memory device using a voltage conversion circuit, the power consumption of a CMOS (Complementary Metal-Oxide-Semiconductor) circuit is proportional to the square of the voltage. Therefore, the conventional semiconductor memory device has an advantage that power consumption can be reduced by using a low power supply voltage. In particular, if the internal voltage source is set to a constant voltage, stable power supply voltage can be ensured even if the external supply voltage fluctuates, so that the operation of the chip is stabilized.

However, it is difficult to design a circuit that exhibits stable operation in the DRAM because peripheral circuits or memory arrays supplied with an internal voltage (VINT;

The core of the DRAM includes a cell, a sub-word line driver, a sense amplifier, an X-decorder, and a Y-decoder. . Here, the internal voltage VINT used on the core side includes a core voltage (VCORE) and a high voltage (VPP) which are positive potential voltages.

For example, the core voltage VCORE is lower than the external power supply voltage VDD, and the high voltage VPP is higher than the external power supply voltage VDD. And, in the active operation of the DRAM, the core voltage VCORE is used, and accordingly, a lot of current is consumed. Therefore, the core voltage VCORE is generated by an internal driver for generating an internal voltage using an operational amplifier.

1 is a circuit diagram of a full driver used as a conventional active driver for internal voltage generation.

Conventionally, an active driver for internal voltage generation receives a reference voltage VREFC and outputs a core voltage VCORE having the same voltage. The active driver for generating the internal voltage includes an operational amplifier 16, an output driver 14 and an N-channel MOSFET 18 (hereinafter referred to as 'NMOS transistor') and a P-channel MOSFET 12 Quot;).

Here, the operational amplifier 16 receives the reference voltage VREFC through a non-inverted input terminal (+). The operational amplifier 16 receives the output voltage VCORE through an inverted input terminal (negative input). The operational amplifier 16 then provides an output signal to the gate electrode of the output driver 14.

Further, the output driver 14 is connected between the external power supply voltage VDD input terminal and the output terminal 20, and the gate terminal is connected to the node 19. The NMOS transistor 18 is connected between the output terminal 20 and an end of the ground voltage VSS, and the control voltage VCON is applied through the gate terminal. As a result, the coil voltage VCORE whose voltage has dropped from the external power supply voltage VDD is output.

The conventional active driver for internal voltage generation allows an active signal ACT to be input to the gate terminal of the PMOS transistor 12 to be operated only during an active operation. The PMOS transistor 12 is connected between the node to which the external supply voltage VDD is applied and the node 19, and the active signal ACT is applied through the gate terminal.

Here, the active signal ACT is activated to the high level in the active operation. If the active signal ACT is input in the 'LOW' state, the PMOS transistor 12 is turned on. Then, the drive node 19 becomes logic 'high' due to the external power supply voltage VDD. As a result, the output driver 14 is turned off. On the other hand, when the active signal ACT transits from the low state to the high state, that is, when the DRAM actually performs the active operation, the output driver 14 is turned on.

Here, the size (size) of the output driver 14 is highly related to the deviation of the core voltage VCORE output to the output stage 20. [ That is, a level deviation of the core voltage VCORE occurs depending on the speed of the current flowing to the output driver 14. For this reason, the size of the output driver 14 is set by accurately estimating the consumed current and loading capacitance of the core voltage VCORE obtained through simulation.

In general, the size of the PMOS transistor of the output driver 14 is set to be larger (for example, about 2 to 3 times) than the simulation result. However, increasing the size of the PMOS transistor of the output driver 14 has its limitations for various reasons.

As described above, there is a limitation in increasing the size of the output driver 14. For example, the level of the core voltage VCORE is dropped by the current consumed in the active operation. Then, the PMOS transistor of the output driver 14 is operated after a certain time delay due to the response speed of the internal voltage generating active driver due to the current consumed in the active operation.

Thereafter, the level of the core voltage VCORE lowered by the operation of the PMOS transistor of the output driver 14 is forcibly raised. In this case, when the size of the PMOS transistor of the output driver is large, it takes a long time to overdamp to the core voltage (VCORE) level and stabilize to the original core voltage (VCORE) level. In addition, when the size of the PMOS transistor of the output driver 14 increases, the layout area of the circuit also increases.

2 is a simulation diagram for explaining an AC noise of an internal voltage according to a driving current of a driving node in a driver for generating an internal voltage in the related art.

FIG. 2 shows how the AC noise of the internal power source changes when the amount of current flowing to the driving node is varied. When the driving current is small, a current flows to the driving node as shown in (G). When the driving current is large, a current flows as shown in (H) to the driving node. That is, it can be seen that the AC noise of the internal power source is smaller than that in the case where the drive current is large.

As the level of the internal voltage increases or decreases, the probability of failure increases, and the internal voltage must be restored to a desired value within a short period of time. To this end, the response speed of the active driver for internal voltage generation must be designed very quickly. If the internal voltage deviates from the desired voltage level range, the driver must react quickly and return the internal voltage to a stable value. However, when the reaction speed of the driver is increased, the operating current of the driver becomes larger. When the operating current is reduced, the response speed of the driver is slowed, and the amount of current that can be driven is reduced.

The present invention is characterized in that the operating current of a driver that constantly controls the internal power supply in the semiconductor memory device is reduced to maintain the stability of the internal power supply.

A power supply driving apparatus according to an embodiment of the present invention includes a voltage generator for comparing a reference voltage with an internal voltage to generate a detection signal; A driving unit for outputting a plurality of driving signals whose voltage levels are changed corresponding to detection signals; And a plurality of internal voltage drivers for controlling the level of the internal voltage, and an internal voltage driver for adjusting the number of operations of the plurality of internal voltage drivers according to the plurality of driving signals.

According to another aspect of the present invention, there is provided a power supply driving apparatus comprising: a comparator for comparing a reference voltage with a first voltage to output a detection signal; A bias unit for supplying a bias current corresponding to an output of the comparison unit; A voltage divider for dividing an internal voltage and outputting a first voltage; A first driving driver pair which selectively operates by a detection signal and a bias current to output a first driving signal; A second drive driver pair that selectively operates by a detection signal and the bias current to output a second drive signal; A first internal voltage driver that selectively operates according to the first driving signal to control the level of the internal voltage; And a second internal voltage driver for selectively controlling the level of the internal voltage according to the second driving signal.

The present invention provides an effect of reducing the operating current of the DRAM without degrading the characteristics of the driver by using an internal power source driver that reduces the operating current.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a circuit diagram of a conventional active driver for internal voltage generation;
2 is a simulation view for explaining noise of an internal voltage according to a drive current in a driver for generating an internal voltage in the related art.
3 is a circuit diagram related to a power supply driving apparatus according to an embodiment of the present invention;
4 is a circuit diagram related to a power supply driving device according to another embodiment of the present invention.
5 is an operation timing diagram of the power source driving apparatus of FIG.
6 is a circuit diagram related to a power supply driving device according to another embodiment of the present invention;
7 is a circuit diagram related to a power supply driving device according to another embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The power source of the semiconductor memory device is divided into an external power source supplied from the outside and an internal power source generated internally. Here, since the internal power source is mainly used for the operation of the cell, if the voltage of the internal power source is unstable, a failure occurs while reading data of the cell or writing data to the cell. Accordingly, when the fluctuation range of the voltage of the internal power supply is large, the operation of the semiconductor memory device becomes unstable, so it is very important to keep the voltage of the internal power supply constant.

There are two types of drivers that drive internal power. A power supply driving apparatus that supplies current from the external power supply VDD when the internal voltage is lowered is referred to as a " voltage down converter ". A power driver driving a current from an internal power supply to a ground (VSS) power supply to lower an internal voltage when the internal voltage becomes high is called a "release driver ". The drive voltage must be lowered to the core voltage level by the release driver after overdriving the semiconductor memory device so that the semiconductor memory device can perform stable operation.

3 is a circuit diagram of a power supply driving apparatus according to an embodiment of the present invention. In the embodiment of FIG. 3, the case where the power supply driving apparatus is composed of the voltage down converter will be described as an example.

A power supply driving apparatus according to an embodiment of the present invention includes a voltage generating unit 100, a driving unit 110, an internal voltage driving unit 120, and a driving control unit 140. Here, the voltage generating unit 100 includes a comparator 101, biasing units 102 and 103, and a voltage distributor 104. The internal voltage driver 120 includes the activation unit 130.

The voltage generator 100 compares the reference voltage VREF with the internal voltage INV and outputs a detection signal according to the comparison result. The comparator 101 includes a differential amplifier for comparing the reference voltage VREF with the voltage VF and outputting a detection signal corresponding to the voltage difference. That is, the comparator 101 amplifies the differential value between the reference voltage VREF and the voltage VF. Here, the voltage VF may be set to a half level of the internal voltage INV, and the voltage VF may vary as much as the level of the reference voltage VREF.

The comparator 101 includes PMOS transistors P1 and P2 and a plurality of NMOS transistors N1 to N3. Here, the PMOS transistors P1 and P2 are connected between the power supply voltage VDD stage and the nodes A and B, respectively. The gate terminal of the PMOS transistor P1 is commonly connected to the PMOS transistor P3. The gate terminal of the PMOS transistor P2 is connected to the node B. The NMOS transistors N1 and N2 are connected between the nodes A and B and the NMOS transistor N3, and the reference voltage VREF and the voltage VF are applied through the gate terminal, respectively. The NMOS transistor N3 is connected between the NMOS transistors N1 and N2 and the ground voltage VSS, and the active signal ACTB is applied through the gate terminal.

The bias portions 102 and 103 control the bias current corresponding to the comparison result signal of the comparison portion 101. [ The biasing unit 102 includes a PMOS transistor P3 and an NMOS transistor N4 connected in series between a power supply voltage VDD stage and a ground voltage VSS stage. Here, the gate terminal of the PMOS transistor P3 is commonly connected to the PMOS transistor P1, and the drain terminal and the gate terminal of the NMOS transistor N4 are connected in common. The biasing unit 103 includes a PMOS transistor P4 and an NMOS transistor N5 connected in series between a power supply voltage VDD stage and a ground voltage VSS stage. Here, the gate terminal of the PMOS transistor P4 is connected to the node A, and the drain terminal and the gate terminal of the NMOS transistor N5 are connected in common.

The voltage divider 104 divides the internal voltage INV to generate a voltage VF having a half level of the internal voltage INV. The voltage divider 104 includes PMOS transistors P5 and P6 connected in series between the output terminal of the internal voltage INV and the ground voltage VSS terminal. Here, the gate terminal and the source terminal of the PMOS transistor P5 are connected in common. The gate terminal and the source terminal of the PMOS transistor P6 are connected in common.

The driving unit 110 selectively controls the driving state of the internal voltage driving unit 120 according to the output of the voltage generating unit 100. The driving unit 110 includes a plurality of PMOS transistors P31 to P3N and a plurality of NMOS transistors N31 to N3N. The plurality of PMOS transistors P31 to P3N provide the NMOS transistors N31 to N3N and the internal voltage driver 120 with a current corresponding to the amount of current provided at the node B, respectively. Each of the PMOS transistors P31 to P3N and each of the NMOS transistors N31 to N3N in the driving unit 110 can be referred to as a "driving driver" for controlling driving of the internal voltage driving unit 120. [

Here, the PMOS transistor P31 and the NMOS transistor N31 are connected in series between the power supply voltage VDD stage and the drive control section 140. [ The gate terminal of the PMOS transistor P31 is connected to the node B. The gate terminal of the NMOS transistor N31 is commonly connected to the gate terminal of the NMOS transistor N4. The PMOS transistor P31 and the NMOS transistor N31 output the driving signal DRV1 through the common drain terminal.

The PMOS transistor P32 and the NMOS transistor N32 are connected in series between the power supply voltage VDD stage and the drive control section 140. [ The gate terminal of the PMOS transistor P32 is connected to the node B in common. The gate terminal of the NMOS transistor N32 is commonly connected to the gate terminal of the NMOS transistor N4. The PMOS transistor P3N and the NMOS transistor N3N output the driving signal DRVN through the common drain terminal.

The activation unit 130 selectively supplies the power supply voltage VDD according to the enable signals EN2B to ENNB to control the activation state of the internal voltage driver 120. [ The activation unit 130 includes a plurality of PMOS transistors P21 to P2N. Here, the PMOS transistor P21 is connected between the power supply voltage VDD stage and the output terminal of the drive signal DRV2, and the enable signal EN2B is applied through the gate terminal. The PMOS transistor P2N is connected between the power supply voltage VDD stage and the output terminal of the drive signal DRVN, and the enable signal ENNB is applied through the gate terminal.

In addition, the internal voltage driver 120 selectively controls the voltage level of the internal voltage INV by adjusting the number of drivers operating according to the driving signals DRV1 to DRVN applied from the driving unit 110. [ That is, the internal voltage driving unit 120 adjusts the voltage level of the internal voltage INV corresponding to the amount of current supplied from the driving unit 110.

The internal voltage driving unit 120 includes a plurality of PMOS transistors P11 to P1N connected in parallel to an output terminal of the internal voltage INV. Each of the PMOS transistors P11 to P1N in the internal voltage driving unit 120 may be referred to as an " internal voltage driver "for controlling driving of the internal voltage INV.

Here, the PMOS transistor P11 is connected between the power supply voltage VDD stage and the output terminal of the internal voltage INV, and the driving signal DRV1 is applied through the gate terminal. The PMOS transistor P12 is connected between the power supply voltage VDD and the output terminal of the internal voltage INV, and the driving signal DRV2 is applied through the gate terminal. The PMOS transistor P1N is connected between the power supply voltage VDD stage and the output terminal of the internal voltage INV, and the driving signal DRVN is applied through the gate terminal.

The driving control unit 140 selectively supplies the ground voltage VSS to the driving unit 110 according to the driving enable signals EN1 to ENN to control the activation state of the driving unit 110. [ The driving control unit 140 includes a plurality of resistors R1 to RN, a plurality of NMOS transistors N21 to N2N, NRT1, and a plurality of delay units DRY1 to DRYN.

Here, the resistors R1 to RN are connected in series between the input terminal of the drive enable signal EN1 and the drain terminal of the NMOS transistor NRT1. The plurality of NMOS transistors N21 to N2N are connected in a one-to-one correspondence with the plurality of NMOS transistors N31 to N3N.

The NMOS transistor N21 is connected between the NMOS transistor N31 and the ground voltage VSS stage, and the drive enable signal EN1 is input through the gate terminal. The delay section DRY1 includes an odd number of inverters IV1 to IV3 for inverting and delaying the drive enable signal EN2.

The NMOS transistor N22 is connected between the NMOS transistor N32 and the ground voltage VSS, and the output of the delay unit DRY1 is applied through the gate terminal. In addition, the delay unit DRYN includes an odd number of inverters IV4 to IV6 to invert the drive enable signal ENN.

The NMOS transistor N2N is connected between the NMOS transistor N3N and the ground voltage VSS, and the output of the delay unit DRYN is applied through the gate terminal. In addition, the NMOS transistor NRT1 is connected between the resistor RN and the ground voltage VSS stage, and the power supply voltage VDD is applied through the gate terminal. Here, the power supply voltage VDD is applied to the NMOS transistor NRT1 through the gate terminal, and the NMOS transistor NRT1 is always kept in the turned-on state.

The operation of the power supply apparatus according to the embodiment of the present invention having such a configuration will be described below.

First, the voltage generating unit 100 compares the reference voltage VREF with the voltage VF and outputs the result to the node B. If the level of the internal voltage INV is low, the voltage VF provided by the voltage divider 104 is lowered. Then, the number of PMOS transistors P11 to P1N of the internal voltage driver 120 is turned on in accordance with the driving signals DRV1 to DRVN, thereby raising the level of the internal voltage INV. On the other hand, when the level of the internal voltage INV is high, the number of turn-on of the PMOS transistors P11 to P1N of the internal voltage driver 120 is reduced according to the driving signals DRV1 to DRVN to reduce the level of the internal voltage INV.

At this time, in order to speed up the reaction speed of the internal voltage driver 120, the gate nodes of the PMOS transistors P11 to P1N must be driven quickly. The gate nodes of the PMOS transistors P11 to P1N must quickly fall to a low voltage in order to rapidly supply current from the external power supply voltage VDD stage to the output terminal of the internal voltage INV. To this end, a large amount of current must flow through each transistor of the driver 110 for controlling the driving signals DRV1 to DRVN.

Here, the amount of current flowing through each transistor of the driving unit 110 increases in proportion to the transistor size of the internal voltage driver 120. At this time, as the transistor size of the internal voltage driver 120 increases, the amount of capacitance of the drive signals DRV1 to DRVN increases, and the driving operation of the drive signals DRV1 to DRVN is slowed down. That is, the smaller the transistor size of the internal voltage driving unit 120, the faster the response speed of the internal voltage driving unit 120 is.

However, if the transistor size of the internal voltage driving unit 120 is reduced, the internal voltage driving unit 120 may not have enough current to transmit the internal voltage INV, so that the internal power supply may be continuously increased or decreased. Accordingly, there is a limit in reducing the size of the transistor of the internal voltage driver 120 and reducing the operating current. Therefore, the embodiment of the present invention controls the level of the internal voltage INV by selectively adjusting the number of turn-on of the PMOS transistors P11 to P1N included in the internal voltage driver 120 according to the driving signals DRV1 to DRVN.

In the embodiment of the present invention, since the number of driving drivers is divided into several, the size of one driver becomes smaller than that of the prior art. Accordingly, in the embodiment of the present invention, assuming that only one driver operates, the internal voltage INV can be driven at a high operation speed even with a small driving current. In addition, in the embodiment of the present invention, the number of drivers to be driven increases corresponding to the level of the internal voltage INV. Accordingly, the internal power supply does not continuously rise or fall due to the insufficient amount of current supplied to the internal voltage INV.

Further, in the embodiment of the present invention, the number of turn-on of each of the PMOS transistors P11 to P1N is adjusted according to the drive signals DRV1 to DRVN generated by the driver 110. [ The number of PMOS transistors P11 to P1N of the driving unit 110 corresponds to the number of pairs of the PMOS transistors P31 to P3N and the NMOS transistors N31 to N3N. That is, when the number of the PMOS transistors P11 to P1N is N, the PMOS transistors P31 to P3N for controlling the NMOS transistors P11 to P1N are provided and N NMOS transistors N31 to N3N are provided. Thus, one pair of transistors drives one driver. For example, one PMOS transistor P11 is driven in accordance with the drive signal DRV1 generated by the PMOS transistor P31 and the NMOS transistor N31.

In order to drive the internal voltage driver 120, a plurality of drivers of the driver 110 may be provided. For example, it is assumed that the size of one output driver 14 of FIG. 1 and the sum of the sizes of the PMOS transistors P11 to P1N of the internal voltage driver 120 are the same. It is assumed that the sum of the current flowing through the node 19 and the current flowing through the driving unit 110 in FIG. 1 is equal. Then, the current flowing in the pair of the PMOS transistor P31 and the NMOS transistor N31 becomes smaller than the current flowing in the node 19. If all of the N PMOS transistors P11 to P1N are driven, the same current is consumed as in the case where one driver operates in Fig.

The driving control unit 140 adjusts the number of driving transistors operating in the driving unit 110 in accordance with the voltage level of the internal voltage INV. The drive control unit 140 controls the number of turn-on of the NMOS transistors N21 to N2N according to the voltages of the drive enable signals EN1 to ENN. The operation state of the driving unit 110 connected to the NMOS transistors N21 to N2N is determined according to the number of turn-ons of the NMOS transistors N21 to N2N.

For example, the voltage of the drive enable signal EN1 is equal to or higher than the threshold voltage (Vth) of the NMOS transistor N21. Therefore, according to the drive enable signal EN1, the NMOS transistor N21 is turned on and the current flows to the NMOS transistor N21. However, since the resistors R1 to RN are connected in series, the drive enable signals EN2 to ENN passing through the resistors R1 and R2 gradually become lower in voltage level.

Thus, it is assumed that the voltages of the drive enable signals EN2 to ENN are lowered to turn off the NMOS transistors N22 to N2N, and no current flows to the NMOS transistors N22 to N2N. The enable signals EN2B to ENNB are inverted signals of the drive enable signals EN2 to ENN. Accordingly, when the drive enable signals EN2 to ENN are at the high level, the enable signals EN2B to ENNB are at the low level.

Then, when the enable signals EN2B to ENNB are at the low level, the PMOS transistors P21 to P2N of the activation unit 130 are turned on. Therefore, the driving signals DRV2 and DRVN are brought into the high level state, and the PMOS transistors P12 to P1N are not operated.

That is, when the voltage levels of the drive enable signals EN1 to ENN are equal to or higher than the threshold voltages Vth of the NMOS transistors N21 to N2N, the corresponding driver of the internal voltage driver 120 operates while the current flows through the NMOS transistors N21 to N2N . In this way, the number of drivers operating in the internal voltage driver 120 varies depending on the number of transistors turned on in the drive controller 140.

At this time, the voltage level of the drive enable signals EN1 to ENN is determined by the biasing voltage flowing through the PMOS transistor P4 and the NMOS transistor N5. The PMOS transistor P4 provides a current corresponding to the amount of current of the node A to the NMOS transistor N5.

That is, as the level of the internal voltage INV decreases, the voltage flowing to the biasing part 103 becomes higher, and the voltages of the drive enable signals EN1 to ENN rise. As a result, current flows through the NMOS transistors N21 to N2N, and the voltage of the drive signals DRV1 to DRVN is lowered to a specific voltage.

The PMOS transistors P21 to P2N of the activation unit 130 are turned on by the enable signals EN2B to ENNB, and current flows to the PMOS transistors P21 to P2N. Then, the internal voltage INV is driven by the external power supply voltage VDD. That is, when the internal voltage INV is lowered, the number of operating drivers increases, and the internal voltage INV can be quickly raised to a desired voltage level.

As described above, the embodiment of the present invention divides the driver into N and controls the size of the driver operating according to the internal voltage INV, thereby reducing the operating current of the driver. That is, N drivers are sequentially turned on according to the internal voltage INV. Accordingly, in a general state in which the internal voltage INV is close to a desired level, a current flows only to one NMOS transistor N21 of the transistors of the driving control unit 140, so that the operating current becomes smaller than that of the conventional voltage down converter. Then, only when the internal voltage INV is greatly lowered, current flows to all the transistors of the drive control section 140. [ Therefore, all of the drivers of the internal voltage driver 120 are operated and the current increases.

4 is a circuit diagram of a power supply driving apparatus according to another embodiment of the present invention. In the embodiment of FIG. 4, a case where the power supply driving apparatus is a release driver will be described as an example.

The power supply driving apparatus according to another embodiment of the present invention includes a voltage generating unit 200, a driving unit 210, an internal voltage driving unit 220, and a driving control unit 240. Here, the voltage generating unit 200 includes a comparator 201, a biasing unit 202, and voltage dividers 203 and 204. The internal voltage driver 220 includes an activator 230.

The voltage generator 200 compares the reference voltage VREF with the internal voltage INV and outputs a detection signal according to the comparison result. The comparator 201 includes a differential amplifier for comparing the reference voltage VREF with the voltage VF and outputting a detection signal corresponding to the voltage difference. That is, the comparator 201 amplifies the differential value between the reference voltage VREF and the voltage VF. Here, the voltage VF may be set to a half level of the internal voltage INV, and the voltage VF may vary as much as the level of the reference voltage VREF.

The comparator 201 includes a differential amplifier for comparing the reference voltage VREF with the voltage VF and outputting a comparison result signal corresponding to the voltage difference. That is, the comparator 201 amplifies the differential value between the reference voltage VREF and the voltage VF.

The comparator 201 includes PMOS transistors P7 and P8 and a plurality of NMOS transistors N6 to N8. Here, the PMOS transistors P7 and P8 are connected between the power supply voltage VDD stage and the nodes (I) and (J). The gate terminal of the PMOS transistor P7 is commonly connected to the PMOS transistor P9. The gate terminal of the PMOS transistor P8 is connected to the node J. The NMOS transistors N6 and N7 are connected between the nodes I and J and the NMOS transistor N8, respectively, and the reference voltage VREF and the voltage VF are applied through the gate terminal, respectively. The NMOS transistor N8 is connected between the NMOS transistors N6 and N7 and the ground voltage VSS stage, and the active signal ACTB is applied through the gate terminal.

The bias unit 202 controls the bias current corresponding to the comparison result signal of the comparison unit 201. [ The biasing unit 202 includes a PMOS transistor P9 and an NMOS transistor N9 connected in series between a power supply voltage VDD stage and a ground voltage VSS stage. Here, the gate terminal of the PMOS transistor P9 is commonly connected to the PMOS transistor P7, and the drain terminal and the gate terminal of the NMOS transistor N9 are connected in common.

The voltage divider 203 divides the internal voltage INV to generate a voltage having a level 3/4 of the internal voltage INV. In the embodiment of FIG. 4, the internal voltage INV is divided by the voltage of 3/4 level. However, the embodiment of the present invention is not limited to this, but the ratio can be sufficiently changed according to the level of the internal voltage INV .

The voltage divider 203 includes a plurality of PMOS transistors P10 to P13 serially connected between the output terminal of the internal voltage INV and the ground voltage VSS. Here, the gate terminal and the source terminal of the plurality of PMOS transistors P10 to P13 are connected in common.

The voltage divider 204 divides the internal voltage INV to generate a voltage VF having a half level of the internal voltage INV. The voltage divider 204 includes PMOS transistors P14 and P15 connected in series between the output terminal of the internal voltage INV and the ground voltage VSS terminal. Here, the PMOS transistors P14 and P15 are commonly connected to the gate terminal and the source terminal, respectively.

The driving unit 210 selectively controls the driving state of the internal voltage driving unit 220 according to the output of the voltage generating unit 200. The driving unit 210 includes a plurality of PMOS transistors P41 to P4N and a plurality of NMOS transistors N41 to N4N. The plurality of PMOS transistors P41 to P4N provide a current corresponding to the amount of current provided at the node J to the NMOS transistors N41 to N4N and the internal voltage driver 220, respectively. Each of the PMOS transistors P41 to P4N and each of the NMOS transistors N41 to N4N in the driving unit 210 may be referred to as a "driving driver" for controlling the driving of the internal voltage driving unit 220. [

Here, the PMOS transistor P41 and the NMOS transistor N41 are connected in series between the power supply voltage VDD stage and the drive control section 240. [ The gate terminal of the PMOS transistor P41 is connected to the node J. The gate terminal of the NMOS transistor N41 is commonly connected to the gate terminal of the NMOS transistor N9. The PMOS transistor P41 and the NMOS transistor N41 output the driving signal DRV1 through the common drain terminal.

The PMOS transistor P42 and the NMOS transistor N42 are connected in series between the power supply voltage VDD stage and the drive control section 240. [ The gate terminal of the PMOS transistor P42 is connected to the node J in common. The gate terminal of the NMOS transistor N42 is commonly connected to the gate terminal of the NMOS transistor N9. The PMOS transistor P4N and the NMOS transistor N4N output the driving signal DRVN through the common drain terminal.

The internal voltage driver 220 selectively controls the voltage level of the internal voltage INV by adjusting the number of drivers that operate according to the driving signals DRV1 to DRVN applied from the driver 210. [ That is, the internal voltage driving unit 220 adjusts the voltage level of the internal voltage INV corresponding to the amount of current supplied from the driving unit 210.

The internal voltage driving unit 220 includes a plurality of NMOS transistors N61 to N6N connected in parallel to an output terminal of the internal voltage INV. Each of the NMOS transistors N61 to N6N in the internal voltage driving unit 220 may be referred to as an "internal voltage driver" for controlling driving of the internal voltage INV.

Here, the NMOS transistor N61 is connected between the output terminal of the internal voltage INV and the ground voltage VSS, and the driving signal DRV1 is applied through the gate terminal. The NMOS transistor N62 is connected between the output terminal of the internal voltage INV and the ground voltage VSS, and the driving signal DRV2 is applied through the gate terminal. The PMOS transistor N6N is connected between the output terminal of the internal voltage INV and the ground voltage VSS terminal, and the driving signal DRVN is applied through the gate terminal.

The activation unit 230 selectively supplies the ground voltage VSS according to the enable signals EN2B to ENNB to control the activation state of the internal voltage driver 220. [ The activation unit 230 includes a plurality of NMOS transistors N71 to N7N. Here, the NMOS transistor N71 is connected between the ground voltage VSS stage and the output terminal of the driving signal DRV2, and the enable signal EN2B is applied through the gate terminal. The NMOS transistor P7N is connected between the ground voltage VSS stage and the output terminal of the drive signal DRVN, and the enable signal ENNB is applied through the gate terminal.

The driving control unit 240 selectively supplies the ground voltage VSS to the driving unit 210 according to the driving enable signals EN1 to ENN to control the activation state of the driving unit 210. [ The driving control unit 240 includes a plurality of resistors R11 to R1N, a plurality of NMOS transistors N51 to N5N, NRT2, and a plurality of delay units DY1 to DYN.

Here, the plurality of resistors R11 to R1N are connected in series between the input terminal of the drive enable signal EN1 and the drain terminal of the NMOS transistor NRT2. The plurality of NMOS transistors N51 to N5N are connected in a one-to-one correspondence with the plurality of NMOS transistors N41 to N4N.

The NMOS transistor N51 is connected between the NMOS transistor N41 and the ground voltage VSS stage, and the drive enable signal EN1 is input through the gate terminal. The delay section DY1 includes an even number of inverters IV7 and IV8 to non-inverted delay the drive enable signal EN2.

The NMOS transistor N52 is connected between the NMOS transistor N42 and the ground voltage VSS stage, and the delay signal EN2D is applied through the gate terminal. In addition, the delay section DYN includes an even number of inverters IV9 and IV10 for non-inverting delay of the drive enable signal ENN.

The NMOS transistor N5N is connected between the NMOS transistor N4N and the ground voltage VSS stage, and the delay signal ENND is applied through the gate terminal. In addition, the NMOS transistor NRT2 is connected between the resistor R1N and the ground voltage VSS stage, and the power supply voltage VDD is applied through the gate terminal. Here, the power supply voltage VDD is applied to the NMOS transistor NRT2 through the gate terminal, and the NMOS transistor NRT2 is always kept in the turn-on state.

The operation of the power source driving apparatus according to another embodiment of the present invention having such a configuration will be described with reference to the operation timing diagram of FIG.

First, the voltage generator 200 compares the reference voltage VREF with the voltage VF and outputs the result to the node J. If the level of the internal voltage INV is low, the voltage VF provided by the voltage divider 204 is lowered. Then, the number of turn-on of the NMOS transistors N61 to N6N of the internal voltage driver 220 is reduced according to the driving signals DRV1 to DRVN, thereby raising the level of the internal voltage INV. On the other hand, when the level of the internal voltage INV is high, the number of turn-on of the NMOS transistors N61 to N6N of the internal voltage driver 220 is increased according to the driving signals DRV1 to DRVN to reduce the level of the internal voltage INV.

At this time, in order to increase the reaction speed of the internal voltage driver 220, the gate nodes of the NMOS transistors N61 to N6N must be driven quickly. In order to rapidly supply the current from the output terminal of the internal voltage INV to the ground voltage VSS, the gate nodes of the NMOS transistors N61 to N6N must quickly rise to a high voltage. To this end, a large amount of current must flow through each transistor of the driver 210 for controlling the driving signals DRV1 to DRVN.

Here, the amount of current flowing through each transistor of the driver 210 increases in proportion to the transistor size of the internal voltage driver 220. At this time, as the transistor size of the internal voltage driver 220 is increased, the amount of capacitance of the driving signals DRV1 to DRVN is increased, and the driving operation of the driving signals DRV1 to DRVN is slowed down. That is, the smaller the transistor size of the internal voltage driving unit 220, the faster the response speed of the internal voltage driving unit 220 is.

However, if the transistor size of the internal voltage driving unit 220 is reduced, the internal voltage driving unit 220 may not have enough current to transmit the internal voltage INV, so that the internal power supply may be continuously increased or decreased. Accordingly, there is a limit in reducing the size of the transistor of the internal voltage driver 220 to reduce the operating current. Therefore, the embodiment of the present invention controls the level of the internal voltage INV by selectively adjusting the number of turn-on of the NMOS transistors N61 to N6N included in the internal voltage driver 220 according to the driving signals DRV1 to DRVN.

Further, in the embodiment of the present invention, the number of turn-on of each of the NMOS transistors N61 to N6N is adjusted according to the drive signals DRV1 to DRVN generated by the driver 210. [ The number of NMOS transistors N61 to N6N of the driver 210 corresponds to the number of pairs of the PMOS transistors N41 to P4N and the NMOS transistors N41 to N4N. That is, when the number of the NMOS transistors N61 to N6N is N, the PMOS transistors P41 to P4N for controlling the N transistors are provided and N NMOS transistors N41 to N4N are provided. Thus, one pair of transistors drives one driver. For example, one NMOS transistor N61 is driven in accordance with the drive signal DRV1 generated by the PMOS transistor P41 and the NMOS transistor N41.

In order to drive the internal voltage driver 220, a plurality of drivers of the driver 210 are provided. For example, it is assumed that the size of one output driver and the total size of the NMOS transistors N61 to N6N of the internal voltage driver 220 are the same in the prior art. It is assumed that the sum of the current flowing in the output node and the current flowing in the driving unit 210 is the same in the prior art. Then, the current flowing in the pair of the PMOS transistor P41 and the NMOS transistor N41 becomes smaller than the current flowing in the output node of the prior art. If all of the N NMOS transistors N61 to N6N are driven, the same current is consumed as in the case where one driver operates in the prior art.

The driving control unit 240 adjusts the number of driving transistors operating in the driving unit 210 in accordance with the voltage level of the internal voltage INV. The drive control unit 240 controls the number of turn-on of the NMOS transistors N51 to N5N according to the voltages of the drive enable signals EN1 to ENN. The operation state of the driving unit 210 connected to the NMOS transistors N51 to N5N is determined according to the number of turn-on operations of the NMOS transistors N51 to N5N.

For example, when the level of the internal voltage INV gradually rises, the voltage of the drive enable signal EN1 becomes equal to or higher than the threshold voltage Vth of the NMOS transistor N51. (Step T11) Therefore, according to the drive enable signal EN1, N51 is turned on and a current starts to flow in the NMOS transistor N51.

As a result, the voltage level of the drive signal DRV1 rises. Then, the current level of the NMOS transistor N61 rises. Then, in the NMOS transistor N61, the current flows from the internal voltage INV output terminal to the ground voltage VSS terminal. In the step T11, only one NMOS transistor N51 operates, so that a large amount of driving current is not consumed.

That is, since the resistors R11 to R1N are connected in series, the drive enable signals EN2 to ENN passing through the resistors R11 and R12 gradually become lower in voltage level. Thus, it is assumed that the voltages of the drive enable signals EN2 to ENN are lowered to turn off the NMOS transistors N52 to N5N, and no current flows to the NMOS transistors N52 to N5N.

Here, the enable signals EN2B to ENNB are inverted signals of the drive enable signals EN2 to ENN. Thus, when the drive enable signals EN2 to ENN are at the low level, the enable signals EN2B to ENNB are at the high level.

If the enable signals EN2B to ENNB are at the high level, the NMOS transistors N71 to N7N of the activating unit 230 are turned on. Then, the activation unit 230 supplies the ground voltage VSS to the gate terminals of the remaining NMOS transistors N62 to N6N. Therefore, while the NMOS transistor N61 is operating, the remaining NMOS transistors N62 to N6N are turned off and do not operate.

Thereafter, when the level of the internal voltage INV continues to rise, the voltage level of the drive enable signal EN2 rises (T12). Then, the delay signal EN2D transits to the high level after the delay time of the delay section DY1, The voltage level of the drive signal DRV2 transits to the high level.

Then, the enable signal EN2N becomes low level, and the NMOS transistor N71 is turned off. Then, the NMOS transistor N62 is turned on by the drive signal DRV2, and the drive current is further consumed in the step T12.

Next, when the level of the internal voltage INV continues to rise, all of the drive signals DRV1 to DRVN are brought into the high level state, and the NMOS transistors N61 to N6N are all in the operating state. (Step T13) The number of drivers to be operated increases.

Here, the drive enable signals EN2 to ENN are driven by a voltage obtained by dividing the internal voltage INV by a predetermined ratio according to the voltage distributor 203. [ Accordingly, when the internal voltage INV rises, the voltage levels of the drive enable signals EN2 through ENN increase in proportion to the internal voltage INV.

That is, when the voltage levels of the drive enable signals EN1 to ENN become equal to or higher than the threshold voltage (Vth) of the NMOS transistors N51 to N5N, current flows through the NMOS transistors N51 to N5N and all the drivers of the internal voltage driver 220 operate . In this way, the number of drivers operating in the internal voltage driver 220 varies depending on the number of transistors turned on in the drive controller 240.

The voltage levels of the drive enable signals EN1 to ENN are determined by the output voltage of the voltage divider 203. [ That is, as the level of the internal voltage INV decreases, the output voltage of the voltage distributor 203 becomes lower, and the voltage of the drive enable signals EN1 through ENN becomes lower.

On the other hand, the higher the level of the internal voltage INV is, the higher the output voltage of the voltage distributor 203 becomes. As a result, a current flows through the NMOS transistors N51 to N5N, so that the voltages of the driving signals DRV1 to DRVN are increased to a specific voltage.

At this time, the NMOS transistors N71 to N7N of the activating unit 230 are turned off by the enable signals EN2B to ENNB. Then, current flows to all the NMOS transistors N61 to N6N. Then, the internal voltage INV is driven by the ground voltage VSS. That is, when the internal voltage INV increases, the number of drivers to be operated increases, and the internal voltage INV can be quickly lowered to a desired voltage level.

As described above, the embodiment of the present invention divides the driver into N and controls the size of the driver operating according to the internal voltage INV, thereby reducing the operating current of the driver. That is, N drivers are sequentially turned on according to the internal voltage INV.

Accordingly, in a normal state in which the internal voltage INV is close to a desired level, a current flows only to one NMOS transistor N61 of the transistor, and the operating current becomes smaller than that of the conventional release driver. On the other hand, when the internal voltage INV continues to rise, all the transistors N61 to N6N turn on to lower the internal voltage INV.

5, when the level of the internal voltage INV rises and the drivers of the internal voltage driver 220 are all operated, the voltage decreases again to reach the target value of the internal voltage INV at steps T23 to T21 . When the level of the internal voltage INV gradually decreases, the NMOS transistors N6N to N61 of the internal voltage driver 220 are sequentially turned off.

6 is a circuit diagram of a power supply driving apparatus according to another embodiment of the present invention.

The power supply driving apparatus according to the embodiment of FIG. 6 includes a voltage generating unit 100_1, a driving unit 110_1, and an internal voltage driving unit 120_1. In the embodiment of FIG. 6, the voltage generating unit 100_1 does not include the biasing unit 103 as compared with the configuration of FIG. In the embodiment of FIG. 6, the drive control unit 140 is not included in the configuration of FIG.

Since the embodiment of FIG. 6 does not include the driving control unit 140, the source terminals of the NMOS transistors N31 to N3N of the driving unit 110_1 are directly connected to the ground voltage VSS stage.

In the embodiment of FIG. 1, the drive control unit 140 is driven by the output of the biasing unit 103, but in the embodiment of FIG. 6, the turn-on state of the NMOS transistors N31 to N3N is controlled according to the output of the biasing unit 102 do. Then, the voltage levels of the drive signals DRV1 to DRVN are changed in accordance with the turn-on states of the NMOS transistors N31 to N3N, and the number of the PMOS transistors P11 to P1N operating in accordance with the drive signals DRV1 to DRVN is adjusted.

Here, the PMOS transistors P31 to P3N and the NMOS transistors N31 to N3N of the driver 110_1 have different transistor sizes. Accordingly, the magnitude ratios of the PMOS transistors P31 to P3N and the NMOS transistors N31 to N3N are adjusted to control the operation timing of the PMOS transistors P11 to P1N of the internal voltage driver 120_1 differently.

For example, the size ratio of the PMOS transistor P31 and the NNOS transistor N31 of the internal voltage driver 120_1 is set to 2: 1, and the size ratio of the PMOS transistor P32 to the NNOS transistor N32 is set to 4: 1. Although the driver ratio of the internal voltage driver 120_1 is set to 2: 1 and 4: 1 in the embodiment of FIG. 6, the present invention is not limited to this, The ratio can be sufficiently deformed.

When the driver size of the internal voltage driver 120_1 is set as described above, the resistance of the NMOS transistor N32 becomes larger than that of the NMOS transistor N31 under the criterion that the internal voltage INV is the same. Thus, the drive signal DRV1 has a lower voltage value than the drive signal DRV2.

Therefore, the PMOS transistor P11 is operated by the drive signal DRV1 having a low voltage, but the PMOS transistor P12 is not operated by the drive signal DRV2 having the high voltage. Thereafter, when the internal voltage INV is gradually lowered, the voltage level of the drive signal DRV2 is lowered, and the PMOS transistor P12 is also in an operating state.

7 is a circuit diagram of a power supply driving apparatus according to another embodiment of the present invention.

7 includes a voltage generator 200_1, a driver 210_1, and an internal voltage driver 220_1. In the embodiment of FIG. 7, the voltage generator 200_1 does not include the voltage divider 203 in comparison with the configuration of FIG. In the embodiment of FIG. 7, the drive control unit 240 is not included in the configuration of FIG.

Since the embodiment of FIG. 7 does not include the driving control unit 240, the source terminals of the NMOS transistors N41 to N4N of the driving unit 210_1 are directly connected to the ground voltage VSS stage.

4, the drive control unit 240 is driven by the output of the voltage distributor 203. However, in the embodiment of FIG. 7, the turn-on state of the NMOS transistors N41 to N4N Respectively. The voltage levels of the drive signals DRV1 to DRVN are changed in accordance with the turn-on states of the NMOS transistors N41 to N4N, and the number of the NMOS transistors N61 to N6N operating in accordance with the drive signals DRV1 to DRVN is adjusted.

Here, the PMOS transistors P41 to P4N and the NMOS transistors N41 to N4N of the driver 210_1 have different transistor sizes. Accordingly, the magnitude ratios of the PMOS transistors P41 to P4N and the NMOS transistors N41 to N4N are adjusted to control the operation timing of the NMOS transistors N61 to N6N of the internal voltage driver 220_1 differently.

For example, the size ratio of the PMOS transistor P41 and the NNOS transistor N41 of the internal voltage driver 220_1 is set to 2: 1, and the size ratio of the PMOS transistor P32 to the NNOS transistor N32 is set to 1: 1. Although the driver ratio of the internal voltage driver 220_1 is set to 2: 1 and 1: 1 in the embodiment of FIG. 7, the embodiment of the present invention is not limited to this, The ratio can be sufficiently deformed.

When the driver size of the internal voltage driver 220_1 is set as described above, the resistance of the NMOS transistor N31 becomes larger than that of the NMOS transistor N32 under the criterion that the internal voltage INV is the same. Thus, the drive signal DRV1 has a higher voltage value than the drive signal DRV2.

Thus, the NMOS transistor N62 starts operating at a higher internal voltage INV than the NMOS transistor N61. In this way, by setting the drive transistor ratio of the internal voltage driver 220_1 differently, the operating current can be reduced by controlling the driver at different times.

Claims

A voltage generator for comparing a reference voltage with an internal voltage to generate a detection signal;
A driving unit for outputting a plurality of driving signals whose voltage levels are changed corresponding to the detection signals; And
And a plurality of internal voltage drivers for controlling a level of the internal voltage and adjusting an operation number of the plurality of internal voltage drivers according to the plurality of driving signals.

The voltage generating circuit according to claim 1,
A comparator comparing the reference voltage with a first voltage;
A first biasing unit for supplying a bias current corresponding to an output of the comparing unit; And
And a first voltage divider for dividing the internal voltage and outputting the first voltage.

3. The apparatus of claim 2, wherein the driving unit
A plurality of first driving drivers connected between a power supply voltage terminal and an output terminal of the plurality of driving signals and selectively operated corresponding to a voltage level of the detection signal; And
And a plurality of second driving drivers connected between the output terminal of the plurality of driving signals and the ground voltage terminal and selectively operated by the bias current.

The power supply driving device according to claim 3, wherein the plurality of first driving drivers and the plurality of second driving drivers include a plurality of transistors having different sizes.

3. The apparatus of claim 2, wherein the voltage generator
And a second biasing unit for supplying a bias current corresponding to an output of the comparing unit.

The power source driving apparatus according to claim 5, further comprising a first drive control unit for controlling a driving state of the driving unit according to an output of the second biasing unit.

7. The apparatus of claim 6, wherein the first drive control unit
A plurality of first resistors connected in series to an output terminal of the second biasing unit and outputting a plurality of drive enable signals through respective connection nodes;
A plurality of first transistors connected between the driving unit and the ground voltage terminal and selectively driven according to the plurality of driving enable signals; And
And a plurality of first delay units for inverting and delaying the plurality of drive enable signals to output a plurality of enable signals.

The power supply according to claim 7, wherein the first drive control unit further comprises a second transistor connected between an output terminal of the plurality of first resistors and the ground voltage terminal and a power supply voltage applied through a gate terminal thereof drive.

The power supply according to claim 7, wherein the internal voltage driver further comprises a first activator connected to the power supply voltage terminal and selectively controlling an activation state of the plurality of internal voltage drivers according to the plurality of enable signals drive.

2. The apparatus of claim 1, wherein the plurality of internal voltage drivers
And a plurality of transistors connected in parallel between a power supply voltage terminal and an output terminal of the internal voltage and selectively operated in accordance with the plurality of drive signals.

2. The apparatus of claim 1, wherein the plurality of internal voltage drivers
And a plurality of transistors connected in parallel between the ground voltage terminal and the output terminal of the internal voltage and selectively operated according to the plurality of drive signals.

3. The apparatus of claim 2, wherein the voltage generator
And a second voltage distributor for outputting a drive enable signal having a value obtained by voltage-dividing the internal voltage.

13. The power supply driving device according to claim 12, further comprising a second drive control unit for controlling a driving state of the driving unit according to an output of the second voltage distributor unit.

14. The apparatus of claim 13, wherein the second drive control unit
A plurality of second resistors connected in series to an output terminal of the second voltage divider and outputting a plurality of drive enable signals through respective connection nodes;
A plurality of third transistors connected between the driving unit and the ground voltage terminal and selectively driven according to the plurality of driving enable signals; And
And a plurality of second delay units for outputting a plurality of enable signals by non-inverting delaying the plurality of drive enable signals.

15. The power supply according to claim 14, wherein the second drive control unit further comprises a fourth transistor connected between an output terminal of the plurality of second resistors and the ground voltage terminal, drive.

15. The power supply according to claim 14, wherein the internal voltage driver further comprises a second activator connected to a ground voltage terminal and selectively controlling an activation state of the plurality of internal voltage drivers according to the plurality of enable signals. drive.

A comparator comparing the reference voltage with a first voltage and outputting a detection signal;
A bias unit for supplying a bias current corresponding to an output of the comparison unit;
A voltage divider for dividing an internal voltage and outputting the first voltage;
A first driving driver pair that selectively operates by the detection signal and the bias current to output a first driving signal;
A second driving driver pair that selectively operates by the detection signal and the bias current to output a second driving signal;
A first internal voltage driver that selectively operates according to the first driving signal to control a level of the internal voltage; And
And a second internal voltage driver which selectively operates according to the second driving signal to control the level of the internal voltage.

18. The power supply driving device according to claim 17, wherein only the first internal voltage driver operates in correspondence with the level of the internal voltage.

The power supply driving apparatus according to claim 17, wherein the first internal voltage driver and the second internal voltage driver sequentially operate in response to a level of the internal voltage.

18. The power supply driving device according to claim 17, wherein the first driving driver pair and the second driving driver pair include a plurality of transistors having different sizes.