KR102217240B1 - One Time Programmable Memory and System-on Chip including One Time Programmable Memory - Google Patents

Abstract

A system-on chip comprising a one-time programmable memory and a one-time programmable memory is disclosed. The One Time Programmable (OTP) memory includes: an OTP cell array including a plurality of OTP cells including program transistors that are irreversibly changed as they are programmed; A temperature compensation reference voltage generator configured to sense a temperature of the OTP memory and generate a reference voltage having a characteristic inversely proportional to the sensed temperature; And a temperature compensation operating voltage generator configured to receive the reference voltage and generate an operating voltage proportional to the reference voltage and applied to the OTP cell array.

Description

System-on Chip including One Time Programmable Memory and One Time Programmable Memory {One Time Programmable Memory and System-on Chip including One Time Programmable Memory}

The present disclosure relates to a system-on chip including a one-time programmable memory and a one-time programmable memory, and more particularly to a system-on chip including a one-time programmable memory and a one-time programmable memory capable of improving reliability.

One Time Programmable Memory (OTP memory) is a non-volatile memory capable of permanently storing programmed data even when power is not supplied. Since it is advantageous in terms of ease of manufacture and security, it is used by replacing eFUSE in System-on Chip (SoC) and the like.

The present disclosure provides an OTP memory and an SoC including an OTP memory capable of improving reliability.

An OTP (One Time Programmable) memory according to an embodiment includes: an OTP cell array including a plurality of OTP cells including program transistors that are irreversibly changed according to programmed data; A temperature compensation reference voltage generator configured to sense a temperature of the OTP memory and generate a reference voltage having a characteristic inversely proportional to the sensed temperature; And a temperature compensation operating voltage generator configured to receive the reference voltage and generate an operating voltage proportional to the reference voltage and applied to the OTP cell array.

The temperature compensation operation voltage generation unit may include a charge pumping unit configured to generate the operation voltage with a program voltage corresponding to a program command applied to the OTP memory by charge pumping the reference voltage; And a voltage regulator that regulates the reference voltage to generate the operating voltage with a read voltage corresponding to a read command applied to the OTP memory.

The program voltage is applied to the gate of the program transistor and may be in inverse proportion to the temperature of the OTP memory.

The OTP cell may further include a read transistor to which the read voltage is applied to a gate, and the read voltage may be inversely proportional to a temperature of the OTP memory.

The charge pumping unit may include a first level up regulator for regulating the reference voltage to a first voltage having a voltage level higher than that of the reference voltage; A detector configured to detect a difference between the first voltage and a second voltage having a voltage level corresponding to the feedback voltage of the program voltage and output a detected voltage; And a charge pump for charging-pumping the detection voltage and outputting the program voltage.

The charge pumping unit may further include a voltage divider that divides the feedback voltage and outputs the voltage as the second voltage.

The voltage regulator may include a second level up regulator configured to regulate the reference voltage to a third voltage having a voltage level higher than that of the reference voltage; And a temperature compensator configured to sense the temperature of the OTP memory and generate the third voltage as the read voltage in inverse proportion to the sensed temperature.

In response to a program command applied to the OTP memory, all OTP cells of the OTP cell array may be programmed at the same time.

In response to a program command applied to the OTP memory, some of the OTP cells of the OTP cell array may be simultaneously programmed.

Each of the OTP cells includes: the program transistor having a gate connected to a program word line among word lines of the OTP cell array; And a read transistor in which one end of the program transistor is connected to one end, the other end is connected to a bit line of the OTP cell array, and a gate is connected to a read word line among word lines of the OTP cell array.

The program transistor may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

The temperature compensation operation voltage generator may include a bandgap voltage reference circuit.

The OTP memory includes: a row decoder for activating at least one word line corresponding to a row address among word lines of the OTP cell array; A column decoder for activating at least one bit line corresponding to a column address among bit lines of the OTP cell array; And an address processing unit that extracts the row address and the column address from an external address input from the outside and transmits the extracted row address and the column address to the row decoder and the column decoder, respectively.

The OTP memory includes: a sensing amplifier configured to sense and amplify an electrical signal of an activated bit line in response to a read command applied to the OTP memory; A data input/output unit for outputting the electric signal sensed and amplified by the sensing amplifier unit as data corresponding to the read command; And a current control unit that sinks a current flowing through an activated bit line to a ground in response to a program command applied to the OTP memory.

A system-on chip (SoC) according to an embodiment includes a One Time Programmable (OTP) memory, and the OTP memory includes a plurality of OTP cells having program transistors that are irreversibly changed according to programmed data. An OTP cell array; A temperature compensation reference voltage generator configured to sense a temperature of the OTP memory and generate a reference voltage having a characteristic inversely proportional to the sensed temperature; And a temperature compensation operating voltage generator configured to receive the reference voltage and generate an operating voltage proportional to the reference voltage and applied to the OTP cell array.

According to the OTP memory according to an embodiment of the present disclosure, regardless of a change in temperature, there is an advantage of improving reliability while improving program characteristics.

According to the OTP memory according to an embodiment of the present disclosure, there is an advantage of improving the yield.

1A and 1B are block diagrams illustrating an OTP memory according to an exemplary embodiment, and graphs illustrating characteristics of a reference voltage and an operating voltage.
2 to 4 are diagrams showing the structure of the OTP cell of FIG. 1A and examples of program and read operations in the OTP cell.
5 and 6 are graphs respectively showing characteristics and characteristics of an OTP memory according to an exemplary embodiment.
7 and 8 are graphs showing characteristics of an OTP memory according to an embodiment, respectively.
9 is a diagram illustrating an example of the OTP memory of FIG. 1A.
10 is a diagram illustrating an example of a temperature compensation reference voltage generator according to an exemplary embodiment.
11 is a diagram illustrating an example of an operation of applying the program voltage of FIG. 9 to an OTP cell array.
12 is a diagram illustrating an example of an operation of applying the read voltage of FIG. 9 to an OTP cell array.
13 is a diagram illustrating an SoC according to an embodiment.
14 is a diagram illustrating a computing device according to an embodiment.

In order to fully understand the present disclosure, operational advantages of the present disclosure, and objects achieved by the implementation of the present disclosure, reference should be made to the accompanying drawings illustrating preferred embodiments of the present disclosure and the contents described in the drawings. Hereinafter, the present disclosure will be described in detail by describing a preferred embodiment of the present disclosure with reference to the accompanying drawings. The same reference numerals in each drawing indicate the same member.

1A and 1B are block diagrams illustrating an OTP memory according to an embodiment. Referring to FIG. 1A, the OTP memory 100 according to an embodiment is one type of nonvolatile memory. Among devices that store data, a device that retains the stored data even when the power supply is cut off is called a nonvolatile memory. For example, the nonvolatile memory includes a read only memory (ROM), a magnetic disk, an optical disk, and a flash memory. In particular, OTP memory refers to a type of nonvolatile memory that cannot be changed once data is written. When data is programmed into the OTP memory, the structure of the OTP cell, which is a storage unit of data included in the OTP memory, is irreversible, and 0 or 1 may be stored using this.

The OTP memory 100 according to an exemplary embodiment may be used to store configuration data that controls the operation of the included semiconductor device or SoC. For example, the OTP memory 100 may be used to store setting data (code) used to perform a trim function in a Display Driver IC (DDI). Alternatively, the OTP memory 100 according to an exemplary embodiment may be used to repair the included semiconductor device. For example, by testing a semiconductor device, the characteristics of the semiconductor device according to the test result are stored in the OTP memory 100 inside the semiconductor device, and the semiconductor device operates based on the information stored in the OTP memory 100, It can prevent malfunction.

The OTP memory 100 according to an embodiment includes an OTP cell array 120, a temperature compensation reference voltage generation unit 140, and a temperature compensation operation voltage generation unit 160. The OTP cell array 120 includes a plurality of OTP cells MC connected to the word line WL and the bit line BL. Among the plurality of OTP cells MC of the OTP cell array 120, an OTP cell MC connected to a word line WL and a bit line BL activated according to a row address and a column address, respectively, may be selected. . Data may be programmed in the selected OTP cell MC, or data may be read from the selected OTP cell MC.

The OTP cell MC includes a program transistor whose electrical characteristics are irreversibly changed as they are programmed. In the present disclosure, the program may be described as an operation of storing data 0 or 1 in the OTP cell MC. At this time, the OTP cell MC is treated as storing data 0 as a default, and at the time of programming, the program voltage (VPP) is limited to the OTP cell MC to program data 1 among the OTP cells MC. ) Can be applied to irreversibly change the electrical characteristics of the program transistor. For example, if you want to program data of 1 and 0 in the adjacent first OTP cell and the second OPT cell, respectively, the program voltage VPP is applied only to the first OTP cell, and the second OTP cell has a default state. By holding the program operation can be performed.

However, it is not limited thereto. In the present disclosure, the program may be understood as an operation of storing the OTP cell MC. In this case, the program command CMDp may be applied only to the OTP cell MC in which data 1 is to be stored. For example, an external address applied together with the program command CMDp or included in the program command CMDp may indicate only the OTP cell MC for which data 1 is to be stored. Details of the structure of the program transistor and the OTP cell MC included in the OTP cell MC will be described later.

The temperature compensation reference voltage generator 140 senses the temperature of the OTP memory 100 and generates a reference voltage VREF as shown in FIG. 1B having a characteristic inversely proportional to the sensed temperature. Referring to FIG. 1B, the reference voltage VREF is generated at a voltage level higher than a high temperature (eg, high temperature HT) at a low temperature (eg, low temperature CT). The voltage level of the reference voltage VREF at the low temperature CT and the high temperature HT may be set to an experimental value in consideration of characteristics of the OTP memory 100. Low temperature (CT) and high temperature (HT) do not refer to a specific temperature, but are used as concepts representing relative low and high temperatures. It is the same below.

The temperature compensation operating voltage generator 160 receives the reference voltage VREF and generates an operating voltage VOP proportional to the reference voltage VREF as shown in FIG. 1B. Since the reference voltage VREF has a characteristic inversely proportional to the temperature, the operating voltage VOP also goes from a low temperature (e.g., low temperature (CT)) to a higher voltage level than a high temperature (e.g., high temperature (HT)). Is created. The voltage level of the operating voltage VOP at the low temperature CT and the high temperature HT may be set to an experimental value in consideration of characteristics of the OTP memory 100.

The operating voltage VOP is applied to the OTP cell array 120. The operating voltage VOP may be a program voltage VPP corresponding to the program command CMDp applied to the OTP memory 100 or a read voltage IVC corresponding to the read command CMDr. Details of the operating voltage VOP will be described below along with the structure of the OTP cell MC.

2 is a diagram illustrating an example of the OTP cell of FIG. 1A.

1A and 2, an OTP cell MC according to an exemplary embodiment may include a program transistor TRp and a read transistor TRr. The program transistor TRp has a gate connected to the program word line WL among the word lines WL. In the read transistor TRr, one end of the program transistor TRp is connected to one end, the other end is connected to the bit line BL, and the gate is connected to the read word line WL of the word lines WL.

The program transistor TRp and the read transistor TRr are MOSFETs (Metal Oxide Semiconductor Field Effect Transistor). The OTP memory 100 according to an embodiment includes an OTP cell MC composed of only MOSFETs as shown in FIG. 2, and thus, a mask step or a layer is performed by a standard CMOS (Complementary Metal Oxide Semiconductor) process. Can be manufactured without the addition of, it can reduce the production cost. In addition, since the OTP memory 100 according to an embodiment does not cause a physical change in the structure of an OTP cell during programming, security can be maintained. Therefore, the OTP memory 100 according to an embodiment may be easy to replace an e-fuse in an SoC or the like.

The program voltage VPP is applied to the activated program word line WL. The program word line WL corresponds to the program command CMDp, for example, a row address extracted from the external address EAdd included in the program command or input to the OTP memory 100 together with the program command CMDp. XAdd), it can be activated. For example, in response to the program command CMDp, all OTP cells MC of the OTP cell array 120 may be programmed at the same time. Alternatively, in response to the program command CMDp, some of the OTP cells MC of the OTP cell array 120 may be simultaneously programmed. For example, 1/2 of the OTP cells MC of the OTP cell array 120 may be programmed at the same time, or 1/8 may be programmed at the same time.

The program voltage VPP is applied to the gate of the program transistor TRp through the program word line WL. As described above, the program transistor TRp of the OTP cell MC is irreversibly changed according to the program. In the OTP cell MC, for example, a program operation (a program operation for data 1) may be performed by breaking down a gate oxide film of the program transistor TRp. However, it is not limited thereto. The program operation for data 1 may be performed by breaking down the junction of the program transistor TRp. However, in the following description, for convenience of description, only the case of breaking down the gate oxide layer.

Before the gate oxide film breaks down, the both ends of the program transistor TRp, that is, the node N1 and the node N2, are separated by the gate oxide film, and the resistance thereof is quite large. Therefore, node N1 and node N2 are in a non-conducting state. On the other hand, when the gate oxide layer breaks down, both ends of the program transistor TRp and the program transistor TRp, that is, the node N1 and the node N2 may irreversibly change from a non-conducting state to a conducting state. When the gate oxide film breaks down, the resistance between the node N1 and the node N2 decreases.

The program voltage VPP is applied at a voltage considerably higher than the threshold voltage of the program transistor TRp to the extent that the gate oxide layer can break down. For example, as shown in FIG. 3, if the threshold voltage of the program transistor TRp is about 1V, the program voltage VPP may be applied to about 5V. As described above, the program voltage VPP is applied to the gate of the program transistor TRp through the program word line WL. In this case, a voltage of about 2V may be applied to the gate of the read transistor TRr, and a voltage of about 0V may be applied to the bit line BL. The threshold voltage of the read transistor TRr may be the same as the threshold voltage of the program transistor TRp.

In the program transistor TRp of the OTP cell MC programmed as shown in FIG. 3, the gate oxide layer is broken down, and as shown in FIG. 4, the program transistor TRp may be converted into a low resistance state. As the read voltage IVC of about 2.5V is applied to the gate of the read transistor TRr of the OTP cell MC programmed as shown in FIG. 3 and a voltage of about 0V is applied to the bit line BL, the node N1 As the current I corresponding to the voltage and resistance of is flowed to the bit line BL, a read operation may be performed.

As described above, a high voltage is applied to the program transistor TRp of the OTP memory 100 according to an exemplary embodiment, so that the gate oxide layer can be broken down. Due to the device characteristics of the MOSFET, when such a high voltage is applied, The yield or reliability may vary depending on the temperature. For example, the program voltage VPP for accurately programming all of the OTP cells MC requiring programming may be required to be higher than the high temperature HT at the low temperature CT. That is, the program success rate may be lower than the high temperature (HT) in the low temperature (CT).

For example, as shown in Figs. 5A and 5B showing the yield characteristics according to the voltage level of the program voltage applied equally regardless of temperature, when the program is executed at high temperature (HT) (Fig. 5A), the program When the voltage (VPP) is 4.9V or higher, the program for all OTP cells (MC) is successful, whereas when the program is performed at low temperature (CT) (Fig. 5b), the program voltage (VPP) must be 5.4V or higher. It can be seen that the program for the OTP cell (MC) is successful. That is, as the temperature is relatively low, the yield characteristic may decrease due to deterioration of characteristics such as gate oxide breakdown or junction breakdown, which are OTP programming mechanisms. Accordingly, as shown in FIG. 5C, the program margin may be poor at a relatively low temperature.

On the other hand, during program and read operations, reliability issues such as Time Dependent Dielectronic Breakdown (TDDB) related to the life of adjacent gate gate oxide films, and HCI related to the life of NMOS transistors are more problematic at high temperature (HT) than at low temperature (CT). I can. For example, as shown in FIG. 6A, which shows a reliability margin according to a program voltage applied equally regardless of temperature, the reliability margin may decrease as the temperature increases. In addition, at high temperature HT, a program margin problem may be caused by the adjacent OTP cell MC than at low temperature.

5 and 6 show an example in which the low temperature (CT) is set to -40 °C and the high temperature (HT) is set to 100 °C. The phenomena of FIGS. 5 and 6 may become more problematic, particularly in situations where microprocessing is required. The OTP memory 100 according to an exemplary embodiment can satisfy both yield improvement and reliability margin security regardless of temperature by compensating for the yield and reliability problems with respect to temperature.

7 is a graph showing a program voltage margin characteristic of an OTP memory according to an embodiment, and FIG. 8 is a graph showing a reliability margin characteristic of an OTP memory according to an embodiment. First, referring to FIGS. 1A and 7, the program voltage VPP according to an exemplary embodiment is set to a higher voltage level at a low temperature or a relatively high temperature. For example, the program voltage VPP may be set to about 5.5V at a low temperature and about 5.1V at a high temperature. Unlike FIG. 5C described above, the program voltage VPP may have a constant margin regardless of the temperature of the OTP memory 100. Next, referring to FIGS. 1A and 8, the program voltage VPP according to an exemplary embodiment is set to a higher voltage level at a low temperature and a relatively high temperature, and thus, unlike FIG. 6, the OTP memory 100 It can have a certain reliability margin regardless of the temperature.

In the above description, the program voltage VPP is mainly described, but the read voltage IVC may be set in the same manner. That is, just as the program voltage VPP is set in inverse proportion to the temperature, the read voltage IVC is set in inverse proportion to the temperature. For example, the read voltage IVC may be set to 1/2 of the program voltage VPP. The reason that the program voltage (VPP) and the read voltage (IVC) are in inverse proportion to the temperature is because the program voltage (VPP) and the read voltage (IVC) are generated based on the reference voltage (VREF) that is generated in inverse proportion to the temperature. to be. For example, the program voltage VPP may be generated by charge pumping the reference voltage VREF, and the read voltage IVC may be generated by regulating the reference voltage VREF. This will be described.

9 is a diagram illustrating an example of the OTP memory of FIG. 1A. Referring to FIG. 9, the OTP memory 100 includes an OTP cell array 120, a temperature compensation reference voltage generation unit 140, and a temperature compensation operation voltage generation unit 160, as described in FIG. 1A. Since the OTP cell array 120 is as described above, a detailed description will be omitted. As described above, the temperature compensation reference voltage generator 140 senses the temperature of the OTP memory 100, for example, an external temperature, and generates a reference voltage VREF as shown in FIG. 1B that is inversely proportional to the sensed temperature.

10 is a diagram illustrating an example of a temperature compensation reference voltage generator 140 according to an exemplary embodiment. 9 and 10, the temperature compensation reference voltage generator 140 may include a bandgap voltage reference circuit 1000 capable of sensing temperature. In generating the reference voltage VREF, the bandgap voltage reference circuit 1000 adjusts the size of a resistor connected to a node to which the reference voltage VREF is output, thereby adjusting the reference voltage VREF in inverse proportion to the sensed temperature. Can be generated. For example, the bandgap voltage reference circuit 1000 of FIG. 10 operates according to a temperature coefficient (CTAT) and an opposite temperature coefficient (PTAT) that cancels the temperature coefficient (CTAT). The reference voltage VREF may be generated, and the degree of temperature compensation may be adjusted by making the resistance value of the resistor R2 connected to the node from which the reference voltage VREF is output smaller than that of the other resistors R1. Specifically, in the bandgap voltage reference circuit 1000 of FIG. 10, since the voltages of nodes T3 and T4 are the same by the amplifier A1, the following equation (1) is established.

V _EB1 = △V _EB + V _EB2 (1)

Then, the following equation (2) is established by the current mirror composed of the transistors T1, T2, and T3.

I1 = I2 = I3 (2)

V _EB1 of Equation 1 is as shown in Equation 3 below, due to the operation characteristic of a bipolar junction transistor (BJT) Q1.

V _EB1 = Vtln(I1/Is) (3)

In Equation (3), Vt is the base-emitter voltage of Q1, and Is is the collector current. ΔV _EB can be expressed as Equation (4) below by Equations (1) and (3). At this time, it is assumed that the ratio of I1 = I2 and BJT Q1 and Q2 in Equation (2) is 1:N.

△V _EB = VtlnN (4)

Since ΔV _EB is the product of resistance R1 and current I2, I3 can be expressed as Equation (5) below.

I3 = I2 = VtlnN/R1 (5)

Since the reference voltage VREF is the sum of the base-emitter voltage V _EB3 of BJT Q3 and the voltage applied to the resistor R2, it can be expressed as Equation (6) below.

VREF = V _EB3 + Vtln(R2/R1) (6)

V _EB3 is the CTAT (Complementary To Absolute Temperature) voltage that decreases as the temperature increases, and the voltage Vtln (R2/R1) across the resistor R2 is the PTAT (Proportional To Absolute Temperature) voltage that increases as the temperature increases. Accordingly, since the resistance value of the resistor R2 is smaller than the resistance R1, the reference voltage VREF may be generated to have a characteristic as shown in FIG. 1B that decreases with an increase in temperature. The slope according to the temperature of the reference voltage VREF of FIG. 1B may be set by the ratio R2/R1 of the resistor R2 and the resistor R1.

Through the above operation, the bandgap voltage reference circuit 1000 of FIG. 10 may generate the reference voltage VREF at a voltage level higher than the high temperature at a low temperature. However, it is not limited thereto. The temperature compensation reference voltage generator 140 according to an embodiment may be implemented in a configuration different from that of the bandgap voltage reference circuit 1000 of FIG. 10.

Referring back to FIG. 9, the temperature compensation operation voltage generator 160 of the OTP memory 100 according to an embodiment receives a reference voltage VREF that is inversely proportional to temperature, and operates in proportion to the reference voltage VREF. Generate voltage (VOP). The temperature compensation operation voltage generation unit 160 is a charge pumping unit 162 that generates a program voltage VPP that is one of the operating voltages VOP and a voltage that generates a read voltage IVC that is one of the operating voltages VOP. A regulator 164 may be included. The charge pumping unit 162 and the voltage regulator 164 increase the voltage level of the reference voltage VREF to generate the program voltage VPP and the read voltage IVC, respectively.

As described above, the program voltage VPP and the read voltage IVC according to an embodiment may be about 5V and about 2.5V, respectively. The temperature compensation operation voltage generation unit 160 includes a charge pumping unit 162 and a voltage regulator 164, respectively, to level up the reference voltage VREF to the same voltage level as in the above example. , But is not limited thereto. For an example in which the voltage levels of the reference voltage VREF, the program voltage VPP, and the read voltage IVC are different, the temperature compensation operation voltage generator 160 uses the reference voltage VREF to the program voltage VPP with a different configuration. And it may be leveled up with the read voltage IVC.

As illustrated in FIG. 9, in addition to the OTP cell array 120, the temperature compensation reference voltage generation unit 140, and the temperature compensation operation voltage generation unit 160 of FIG. 1, the OTP memory 100 according to an embodiment , A row decoder 110, a column decoder 130, an address processing unit 150, a sensing amplification unit 170, a data output unit 180, and a current controller 190 are further provided to perform the above-described operation. I can.

The row decoder 110 activates the word line WL corresponding to the row address XAdd. The column decoder 130 activates the bit line BL corresponding to the column address YAdd. The row address XAdd and the column address YAdd are transmitted from the address processing unit 150. The address processing unit 150 extracts an external address EAdd applied to the OTP memory 100 as a row address XAdd and a column address YAdd, respectively. Accordingly, the address processing unit 150 may be implemented as an address latch.

The sensing amplifier 170 senses a current (I of FIG. 4) supplied from the bit line BL activated by the column decoder 130 in response to the read command CMDr applied to the OTP memory 100 And amplify. The data output unit 180 outputs the data DTA as the current from the amplified OTP cell MC as the current itself or a voltage corresponding to the current. The current controller 190 sinks the current from the bit line BL to the ground in response to the program command CMDp. The current controller 190 may include a sink transistor TRs connected to ground and a reference current generator 192 that supplies a reference current Iref to the gate of the sink transistor TRs.

FIG. 11 is a diagram for describing an operation of applying the program voltage of FIG. 9 to an OTP cell array. Referring to FIG. 11, the charge pumping unit 162 may include a first regulator 162_1, a voltage detector 162_2, and a charge pump 162_3. In response to the program command CMDp, the first regulator 162_1 regulates the reference voltage VREF received from the temperature compensation reference voltage generator 140 to output a first voltage VREFA having a higher voltage level. . The voltage detector 162_2 may detect a difference between the voltage VPP_REF corresponding to the feedback voltage VPP_PB of the first voltage VREFA and the program voltage VPP and output the detection voltage VPP_ON.

11 shows the difference between the second voltage VPP_REF and the first voltage VREFA obtained by distributing the feedback voltage VPP_PB, not the feedback voltage VPP_PB of the program voltage VPP, in the voltage detector 162_2. VPP_ON) is shown. To this end, the charge pumping unit 162 may further include a voltage divider 162_4 for distributing the feedback voltage VPP_PB at a predetermined ratio and outputting the second voltage VPP_REF. However, the voltage VPP_REF corresponding to the feedback voltage VPP_PB may be the feedback voltage VPP_PB itself. In this case, the voltage divider 162_4 may not be provided.

The charge pump 162_3 outputs the voltage VPP_REF corresponding to the detection voltage VPP_ON as the program voltage VPP. In FIG. 11, the charge pump 162_3 may change the charge pumping operation according to the voltage level of the detection voltage VPP_ON. The charge pump 162_3 may be controlled by a control clock VPP_COS applied from the charge pump oscillator 162_5.

The program voltage VPP generated from the charge pumping unit 162 is applied to the word line WL activated by the row decoder 110. As described above, the row decoder 110 activates the word line WL corresponding to the row address XAdd transmitted from the address processing unit 150. The column decoder 130 activates the bit line BL corresponding to the column address YAdd transmitted from the address processing unit 150. For example, the column decoder 130 may apply a voltage of 0V to the bit line BL corresponding to the column address YAdd, and apply about 2V to the remaining bit lines BL.

FIG. 12 is a diagram for describing an operation of applying the read voltage of FIG. 9 to an OTP cell array. Referring to FIG. 12, the voltage regulator 164 may include a second regulator 164_1 and a temperature compensator 164_2. The second regulator 164_1 regulates to a third voltage VREFB having a voltage level higher than the reference voltage VREF. The temperature of the OTP memory 100 is sensed to generate the third voltage VREFB as the read voltage IVC. The temperature compensating unit 164_2 provides stable power to the external power source and generates a read voltage IVC so that the voltage level decreases from a low temperature to a high temperature. The temperature compensation unit 164_2 may be implemented in a structure similar to the bandgap voltage reference circuit 1000 of FIG. 10 described above.

The OTP memory 100 according to an exemplary embodiment may increase a program success rate and improve a reliability margin by setting the program voltage VPP and the read voltage IVC to be lower at a higher temperature than at a lower temperature. Therefore, it is possible to improve the yield by preventing product defects. Further, the OTP memory 100 according to an embodiment can secure a program success rate and a reliability margin by setting the program voltage (VPP) and the read voltage (IVC) to be lower at a higher temperature than at a lower temperature, so that the program voltage (VPP) The voltage level of) can be set low. Accordingly, in the OTP memory 100 according to an exemplary embodiment, a reliability margin of an adjacent OTP cell MC that is not selected during a program operation may be improved. In addition, since the voltage level of the program voltage VPP can be set low at a high temperature, the area of the charge pumping unit 162 can be reduced, thereby reducing the chip size.

13 is a diagram illustrating an SoC according to an embodiment. Referring to FIG. 13, the SoC 1300 includes a central processing unit 1310, a system memory 1320, an interface 1330, an OTP memory 100, function blocks 1340, and a bus 1350 connecting them. Can include. The central processing unit 1310 controls the operation of the SoC 1300. The central processing unit 1310 may include a core and an L2 cache. For example, the central processing unit 1310 may include a multi-core. Each core of the multi-core may have the same or different performance from each other. In addition, each core of the multi-core can be activated at the same time or can be activated at different times. The system memory 1320 may store a result of processing by the function blocks 1340 under the control of the central processing unit 1310. For example, as content stored in the L2 cache of the central processing unit 1310 is flushed, it may be stored in the system memory 1320. The interface 1330 may interface with external devices. For example, the interface 1330 may interface with a camera, an LCD, and a speaker.

The OTP memory 100 may store setting information on the SoC 1300. As described above, the OTP memory 100 senses the temperature of the OTP memory 100 or the SoC 1300 to set the program voltage VPP and the read voltage IVC lower than the low temperature, thereby increasing the program success rate. And improve the reliability margin. Accordingly, the reliability of the SoC 1300 including the OTP memory 100 can be improved. The functional blocks 1340 may perform various functions required for the SoC 1300. For example, the functional blocks 1340 may perform a video codec or may process 3D graphics.

14 is a diagram illustrating a computing system including an SoC according to an embodiment. The SoC 1300 according to an embodiment may be mounted in a computing system 1400 such as a mobile device, a desktop computer, or a server. In addition, the computing system 1400 may further include a memory device 1420, an input/output device 1440, and a display device 1460, and these components may be electrically connected to the bus 1480, respectively. The computing system 1400 may operate based on setting information stored in the OTP memory 100 of the SoC 1300. Accordingly, the reliability of the computing system 1400 may be improved.

As described above, an optimal embodiment has been disclosed in the drawings and specifications. Although they were specific terms herein, they are used only for the purpose of describing the present disclosure, and are not used to limit the meaning or the range described in the claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. The true technical scope of protection according to the present disclosure should be determined by the technical spirit of the appended claims.

Claims (10)

In OTP (One Time Programmable) memory,
An OTP cell array including a plurality of OTP cells having program transistors that are irreversibly changed as they are programmed;
A temperature compensation reference voltage generator configured to sense a temperature of the OTP memory and generate a reference voltage having a characteristic inversely proportional to the sensed temperature; And
A temperature compensation operating voltage generator configured to receive the reference voltage, generate at least one operating voltage proportional to the reference voltage, and apply the at least one operating voltage to the OTP cell array, ,
The temperature compensation operating voltage generator,
The OTP memory, wherein voltage regulation is performed on the reference voltage to generate a read voltage corresponding to a read command as a first operating voltage among the at least one operating voltage. The method of claim 1,
The temperature compensation operating voltage generator,
A charge pumping unit configured to charge pump the reference voltage to generate the at least one operating voltage with a program voltage corresponding to a program command applied to the OTP memory,
The voltage regulator,
And generating the operating voltage with a read voltage corresponding to a read command applied to the OTP memory by regulating the reference voltage. The method of claim 2,
The program voltage is applied to a gate of the program transistor and is in inverse proportion to a temperature of the OTP memory. The method of claim 2,
The OTP cell further includes a read transistor to which the read voltage is applied to a gate,
The read voltage is inversely proportional to the temperature of the OTP memory. The method of claim 2,
The charge pumping unit,
A first level up regulator for regulating to a first voltage having a voltage level higher than the reference voltage;
A voltage detector configured to detect a difference between the first voltage and a second voltage having a voltage level corresponding to the feedback voltage of the program voltage and output a detected voltage; And
And a charge pump for outputting a voltage corresponding to the detected voltage as the program voltage. The method of claim 5,
The charge pumping unit,
And a voltage divider that divides the feedback voltage and outputs the voltage as the second voltage. The method of claim 2,
The voltage regulator,
A second level up regulator for regulating to a third voltage having a voltage level higher than the reference voltage; And
And a temperature compensator configured to sense the temperature of the OTP memory and generate the third voltage as the read voltage in inverse proportion to the sensed temperature. The method of claim 1,
Each of the OTP cells,
The program transistor having a gate connected to a program word line among word lines of the OTP cell array; And
And a read transistor having one end connected to one end of the program transistor, the other end connected to a bit line of the OTP cell array, and a gate connected to a read word line among word lines of the OTP cell array. Memory. The method of claim 1,
The program transistor is an OTP memory, characterized in that the MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the SoC (System-on Chip) including OTP (One Time Programmable) memory,
The OTP memory,
An OTP cell array including a plurality of OTP cells having program transistors that are irreversibly changed as they are programmed;
A temperature compensation reference voltage generator configured to sense a temperature of the OTP memory and generate a reference voltage having a characteristic inversely proportional to the sensed temperature; And
A temperature compensation operating voltage generator configured to generate at least one operating voltage proportional to the reference voltage by receiving the reference voltage, and to apply the at least one operating voltage to the OTP cell array, ,
The temperature compensation operating voltage generator,
SoC, wherein voltage regulation is performed on the reference voltage to generate a read voltage corresponding to a read command as a first operating voltage among the at least one operating voltage.

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