KR20120063768A - Electrophoresis display device and power control method thereof - Google Patents

Electrophoresis display device and power control method thereof Download PDF

Info

Publication number
KR20120063768A
KR20120063768A KR1020100124893A KR20100124893A KR20120063768A KR 20120063768 A KR20120063768 A KR 20120063768A KR 1020100124893 A KR1020100124893 A KR 1020100124893A KR 20100124893 A KR20100124893 A KR 20100124893A KR 20120063768 A KR20120063768 A KR 20120063768A
Authority
KR
South Korea
Prior art keywords
voltage
pull
response
gate
data
Prior art date
Application number
KR1020100124893A
Other languages
Korean (ko)
Inventor
배형국
Original Assignee
엘지디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to KR1020100124893A priority Critical patent/KR20120063768A/en
Publication of KR20120063768A publication Critical patent/KR20120063768A/en

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1685—Operation of cells; Circuit arrangements affecting the entire cell
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: An electrophoretic display and a power control method thereof are provided to prevent degradation of display quality due to discharge delay of driving voltages by discharging an output terminal voltage of a module power circuit. CONSTITUTION: A display panel(10) includes data lines, gate lines, and a plurality of electrophoretic cells. A data driving circuit(12) selects a positive data voltage and a negative data voltage according to the digital video data. A gate driving circuit(13) supplies gate pulse between the positive data voltage and the negative data voltage to the gate lines.

Description

Electrophoretic display and its power control method {ELECTROPHORESIS DISPLAY DEVICE AND POWER CONTROL METHOD THEREOF}

The present invention relates to an electrophoretic display and a method for controlling the power thereof.

When a substance with a charge is placed in an electric field, the substance moves in a specific way depending on the charge, the size and shape of the molecule. Such behavior is referred to as electrophoresis, and the phenomenon of separation of materials due to the difference in movement is called electrophoresis. Recently, display apparatuses using electrophoresis have been developed and attract attention as a medium to replace existing paper media or display elements.

Electrophoretic displays have been disclosed in US Pat. No. 7,012,600, US Pat. No. 7,119,772. The electrophoretic display includes data lines, gate lines (or scan lines) intersecting the data lines, and an electrophoretic film. The data driving circuit supplies the data lines generated with the positive voltage or the negative voltage to the data lines according to the gray level of the data. The gate driving circuit sequentially supplies gate pulses (or scan pulses) swinging between the gate high voltage and the gate low voltage to the gate lines.

The electrophoretic display has a memory function of writing new data to pixels through a data update process for approximately one second and then maintaining the current data until the next data update. Therefore, the electrophoretic display device can reduce power consumption because it maintains the current data without supplying a separate driving power from the outside due to the memory function inherent to the electrophoretic pixel.

The electrophoretic display turns off the driving power sources according to a preset power off sequence after the data update. However, the driving power supplies are gradually discharged due to the panel load at power off. During this time, when the driving voltages are slowly discharged (hundreds of ms to several seconds), the discharge delay results in fading off or gradation unevenness in which the currently displayed image gradually disappears.

The present invention provides an electrophoretic display device and a method for controlling the power thereof, which can prevent the display quality from being degraded due to the discharge delay of the driving voltages immediately after the image update.

An electrophoretic display of the present invention includes a display panel including data lines, gate lines intersecting the data lines, and a plurality of electrophoretic cells; A data driving circuit which selects a positive data voltage and a negative data voltage according to the digital video data to supply the data lines during the image update period; A gate driving circuit for supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during the image update period; And outputting the positive data voltage, the negative data voltage, the positive gate voltage, and the negative gate voltage through output terminals in response to the enable signals, and input the input signal immediately after the image update period. And a module power supply circuit for forcibly discharging the voltages of the output terminals in response to the inverted signals of the signals.

In the method of controlling power of the electrophoretic display device, an enable signal is input to a module power circuit, and the positive data voltage, the negative data voltage, the positive gate voltage, and the negative polarity are output through output terminals of the module power circuit. Outputting a gate voltage; And inverting the enable signals immediately after the image update period and inputting the enable signals to the module power circuit to force discharge of the output terminal voltage of the module power circuit.

The present invention forcibly discharges the output terminal voltage of the module power supply circuit immediately after the image update. As a result, the present invention can prevent the display quality from deteriorating due to the discharge delay of the driving voltages immediately after the image update in the electrophoretic display.

1 is a block diagram illustrating an electrophoretic display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating in detail a microcapsule structure of a pixel illustrated in FIG. 1.
3 is a diagram illustrating an example of a power-on sequence.
4 is a diagram illustrating an example of a power off sequence.
5 is a view showing in detail the module power circuit shown in FIG.
FIG. 6 is a circuit diagram showing in detail the first DC-DC converter and the first pull-down circuit shown in FIG. 5.
7 is a flowchart illustrating a power control method of an electrophoretic display according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a block diagram illustrating an electrophoretic display device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating in detail a microcapsule structure of a pixel illustrated in FIG. 1.

1 and 2, an electrophoretic display device according to an exemplary embodiment of the present invention includes a display panel 10 in which m × n pixels Ce are arranged in a matrix, and data voltages of the display panel 10. To control the data driving circuit 12 for supplying the scan 14, the gate driving circuit 13 for supplying the scan pulse to the gate lines 15 of the display panel 10, and the driving circuits 12 and 13. And a control unit 11 and a module power supply circuit 20.

In the display panel 10, a plurality of microcapsules 3 as shown in FIG. 2 are formed between the common electrode 2 and the pixel electrode 1. The common electrode 2 is formed of a transparent electrode material, for example, indium tin oxide (ITO). Each of the microcapsules 3 comprises negatively charged white particles 5 and positively charged black particles 4.

The data lines 14 and the gate lines 15 formed on the lower substrate of the display panel 10 cross each other. The lower substrate may be made of glass, metal, plastic, or the like. TFTs are formed at intersections of the data lines 14 and the gate lines 15.

The TFTs are turned on according to the scan pulse from the gate line 15 to select the pixels Ce of one line to be displayed and select the data voltages from the data lines 14 to select the pixels of the fill cells Ce. It is supplied to the electrode 1. Gate electrodes of the TFTs are connected to the gate lines 15. The source electrodes of the TFTs are connected to the data line 14, and the drain electrodes thereof are connected to the pixel electrode 1 of the pixel Ce. When the positive voltage Vpos is applied to the pixel electrode 1 of the pixel Ce, the pixel Ce displays a black gray level, and the negative voltage Vneg is applied to the pixel electrode 1 of the pixel Ce. When applied, the pixel Ce displays white gradation. New data is written to the pixels Ce during the image update process. After the image update, the pixels Ce maintain the gradation of the currently written data until the next image update.

A common electrode line 16 is formed on the upper transparent substrate of the display panel 10 to simultaneously supply the common voltage Vcom to all the pixels. The upper substrate can be made of a transparent glass or plastic substrate.

The data driving circuit 12 outputs a positive data voltage Vpos of + 15V when the digital data input from the controller 11 is '01 2 'during the image update period. The data driving circuit 12 outputs a negative data voltage Vneg of -15V when the digital data input from the controller 11 is '10 2 'during the image update period. In addition, the data driving circuit 12 outputs a base voltage Vss of 0V when the digital data input from the controller 11 is '00 2 or 11 2 'during the image update period. Accordingly, the data driving circuit 12 selects one of the three-phase voltages Vpos, Vneg, and Vss as the data voltage in response to the digital data input from the controller 11 in the image updating process, and thereby the data lines 14. Will output The output voltage of the data driving circuit 12 is supplied to the pixel electrode 1 of the pixel Ce via the data lines 14 and the TFT.

The gate driving circuit 13 sequentially outputs scan pulses synchronized with the data voltages supplied to the data lines 14 during the image update period. The scan pulses swing between the positive gate voltage GVDD and the negative gate voltage GVEE.

The control unit 11 receives the vertical / horizontal synchronization signals V and H and the clock signal CLK to generate control signals for controlling the operation timing of the data driving circuit 12 and the gate driving circuit 13. The control signals include a source timing control signal for controlling the operation timing of the data driving circuit 12 and a gate timing control signal for controlling the operation timing of the gate driving circuit 13. In addition, the controller 11 uses the frame memory to store the input image and the lookup table in which the data voltage waveform is set, and the digital data set for each gray level of the data according to the current gray state of the pixel and the next state of the pixel to be updated. It supplies to the furnace 12.

When the power of the electrophoretic display device is turned on, the module power circuit 20 converts a DC-DC converter (hereinafter, referred to as a "DC-DC converter") according to a preset power-on sequence. The driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE necessary for driving the display panel 10 are generated using the input voltage Vin. The power on sequence may be set in advance in the control unit 11 or an external host system. When applied to the module power circuit 20, the module power circuit 20 is applied to enable signals of each of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE input from the controller 11 or the host system. In response, driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE are generated.

The logic power supply voltage Vcc is logic required for driving an application specific integrated circuit (ASIC) of the control unit 11, a source drive IC (integrated circuit) of the data driving circuit 12, and a gate drive IC of the gate driving circuit 13. As a voltage, it is generally generated at a DC voltage of 3.3V. The positive data voltage Vpos is generated at a DC voltage of + 15V and the negative voltage Vneg is generated at a DC voltage of -15V. The common voltage is generated with a DC voltage between 0V and -2V. The negative gate voltage GVEE is generated at a DC voltage of -20V. The positive gate voltage GVDD is generated at a DC voltage of + 22V.

The module power supply circuit 20 rapidly discharges the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE according to a preset power off sequence immediately after the image update. The power off sequence may be preset in the controller 11 or the host system. The control unit 11 or the host system inverts the enable signal of each of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE according to the power-on sequence immediately after the image update. As a result, the module power supply circuit 20 discharges the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE to the base voltage source GND in response to the inverted enable signals (or disable signals). .

The method of updating an image on the display panel 10 is disclosed in Korean Patent Application Laid-Open No. 10-2008-0054779 (June 19, 2008) and Korean Patent Application Laid-Open No. 10-2008-0054781 (filed by the present applicant). 2008. 06. 19), Republic of Korea Patent Publication No. 10-2008-0055331 (2008. 06. 19), Republic of Korea Patent Publication No. 10-2008-0058956 (June 26, 2008), Republic of Korea Patent Publication 10-2008-0083425 (2008. 09. 18), Republic of Korea Patent Publication No. 10-2008-0090185 (2008. 10. 08), Republic of Korea Patent Publication No. 10-2009-0105488 (2009. 10. 07) ) And the like can be used.

3 is a diagram illustrating an example of a power-on sequence.

Referring to FIG. 3, when the power of the electrophoretic display is turned on, the external host system supplies an input voltage Vin to the module power circuit 20, and the host system or the controller 11 supplies driving voltages. Enable signals of (Vcc, Vcom, Vpos, Vneg, GVDD, GVEE) are supplied to the module power supply circuit 20 based on a preset power-on sequence. Then, the module power supply circuit 20 outputs the negative gate voltage GVEE, then outputs the positive gate voltage GVDD, and then outputs the positive data voltage Vpos and the negative data voltage Vneg. .

4 is a diagram illustrating an example of a power off sequence.

Referring to FIG. 4, immediately after the image update, the host system or the controller 11 inverts the enable signals of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE based on a preset power-on sequence. Then, the module power supply circuit 20 discharges the positive gate voltage GVDD and the negative gate voltage GVEE to the ground voltage GND in response to the inverted enable signal, and then the positive data voltage Vpos and the negative voltage. The polarity data voltage Vneg is discharged to the ground voltage GND.

5 is a view showing the module power supply circuit 20 in detail.

Referring to FIG. 5, the module power supply circuit 20 includes first to fourth DC-DC converters 201 to 204, pull-down circuits 101 to 104, and the like.

The DC-DC converters 201 to 204 are supplied with a DC voltage Vin such as 5V, 9V, and 12V, and the enable signals GVDD_EN, GVEE_EN, Vpos_EN, and Vneg_EN have a first logic value (for example, High). ), It generates output voltages (GVDD, GVEE, Vpos, Vneg). Each of the pull-down circuits 101 to 104 quickly discharges the output voltage of each of the DC-DC converters 201 to 204 to the ground voltage source GND in response to the inverted enable signals.

FIG. 6 is a circuit diagram illustrating in detail the first DC-DC converter 201 and the first pull-down circuit 101. Since the basic circuit configuration of the second to fourth DC-DC converters 202 to 204 is substantially the same as that of the first DC-DC converter 201, a detailed description thereof will be omitted. Since the circuit configurations of the second to fourth pull-down circuits 102 to 104 are substantially the same as the first pull-down circuit 101, detailed description thereof will be omitted.

Referring to FIG. 6, the first DC-DC converter 201 may include a power control IC 200, an inductor L, a diode D, resistors VR1 and R1, capacitors C1 to C3, and the like. Include.

The inductor L charges the input current to increase the output voltage. The diode D is connected between the inductor L and the output terminal of the first DC-DC converter 201 to block reverse current. The resistors VR1 and R1 are connected between the output terminal of the first DC-DC converter 201 and the ground voltage source GND to divide the output voltage GVDD_out to provide a reference voltage of the power control IC 200 as a reference voltage. Enter in (FB). The first capacitor C1 stabilizes the input terminal voltage of the first DC-DC converter 201, and the third capacitor C3 stabilizes the output terminal voltage of the first DC-DC converter 201. The second capacitor C2 is connected between the node between the variable resistor VR1 and the resistor R1 constituting the feedback voltage divider circuit, and the base voltage source GND to connect to the feedback terminal FB of the power control IC 200. Eliminates noise mixed in the supplied reference voltage.

The power control IC 200 operates when the first enable signal GVDD_EN input to the shutdown terminal / SHDN is high logic to generate an output voltage GVDD_out. When the reference voltage is changed according to the panel load according to the reference voltage input from the feedback terminal FB, the power control IC 200 controls the built-in transistor SW to control the pulse width modulation (PWM) to control the inductor L and the diode. The output voltage is kept constant by controlling the current flowing through the current path between (D). The power control IC 200 stops generation of the output voltage GDD_out by blocking the current path between the inductor L and the diode D when the first enable signal GVDD_EN is inverted immediately after the image update.

The first pull-down circuit 101 includes an inverter INV, a transistor Q, a variable resistor VR2, and the like.

The inverter INV inverts the first enable signal GVDD_EN and inputs it to the gate electrode of the transistor Q. The transistor Q may be implemented as an N-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). The transistor Q discharges the output voltage GVDD_out of the first DC-DC converter 201 to the ground voltage source GND in response to the inverted enable signal / GVDD_EN input through the inverter INV. The gate electrode of the transistor Q is connected to the output terminal of the inverter INV. The drain electrode of the transistor Q is connected to the output terminal of the first DC-DC converter 201 through the variable resistor VR2, and the source electrode of the transistor Q is connected to the ground voltage source GND. The variable resistor VR2 may adjust the output voltage discharge rate of the first DC-DC converter 201 according to the resistance value.

The first enable signal GVDD_EN is inverted to low logic immediately after the image update. Then, the first enable signal GVDD_EN of the low logic is inverted to the high logic of the inverter INV to turn on the transistor Q. As a result, immediately after the image update, the output of the first DC-DC converter 201 is quickly discharged to the ground voltage source GND.

Similarly, the second to fourth pull-down circuits 102-104 quickly discharge the output voltages of the second to fourth DC-DC converters 202-204 immediately after the image update. The pull-down circuits 101-104 may be integrated into one package together with the DC-DC converters 201-204.

Meanwhile, in the pull-down circuits 101 to 104, the inverter INV and the transistor Q are omitted, and the pull-down resistor VR2 is connected to the output terminal of the DC-DC converter 201 to 204 and the ground voltage source GND. You can connect directly between them. In this case, if the resistance value of the pull-down resistor VR2 is reduced, the output of the first DC-DC converter 201 leaks through the small pull-down resistor VR2 even in the image updating process, resulting in a large current loss. Power consumption is increased. In order to reduce the current loss, increasing the resistance value of the pull-down resistor VR2 reduces the discharge effect. Accordingly, the present invention increases the pull-down resistance of the output terminal to several MΩ when the DC-DC converters 201 to 204 are operated by adding an inverter and a transistor Q to the pull-down circuits 101 to 104. Prevents current loss and quickly discharges the output voltage by lowering the pull-down resistance of the output terminal to a few ohms when the DC-DC converters 201-204 stop the output.

7 is a flowchart illustrating a power control method of an electrophoretic display according to an exemplary embodiment of the present invention.

Referring to FIG. 7, when the power of the electrophoretic display device is turned on, the module power circuit 20 may be configured to drive the display panel 10 in response to the enable signals generated according to the power-on sequence shown in FIG. 3. The required driving voltages GVDD, GVEE, Vpos, and Vneg are output. (S1 and S2)

After the user data is input and the new image is updated on the display panel 10, the controller 11 or the host system inverts the enable signal. Then, the module power supply circuit 20 stops outputting the driving voltages GVDD, GVEE, Vpos, and Vneg in response to the inverted enable signals according to the power-off sequence shown in FIG. 4. At the same time, the pull-down circuits 201 to 204 are enabled in response to the inverted enable signal to forcibly discharge the driving voltages GVDD, GVEE, Vpos, and Vneg to the base voltage source GND. To S5)

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 11: control unit
12: data driving circuit 13: gate driving circuit
20: module power supply circuit 101 ~ 104: pull-down circuit
201 ~ 204: DC-DC converter

Claims (8)

A display panel including data lines, gate lines crossing the data lines, and a plurality of electrophoretic cells;
A data driving circuit which selects a positive data voltage and a negative data voltage according to the digital video data to supply the data lines during the image update period;
A gate driving circuit for supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during the image update period; And
The enable signal is outputted through the output terminals in response to the enable signals and outputs the positive data voltage, the negative data voltage, the positive gate voltage, and the negative gate voltage, and is input immediately after the image update period. And a module power circuit for forcibly discharging the voltages of the output terminals in response to the inverted signals of the two electrodes.
The method of claim 1,
The module power circuit,
A first DC-DC converter generating the positive gate voltage in response to a first enable signal;
A first pull-down circuit for forcibly discharging an output terminal voltage of the first DC-DC converter in response to an inversion signal of the first enable signal;
A second DC-DC converter generating the negative gate voltage in response to a second enable signal;
A second pull-down circuit forcibly discharging an output terminal voltage of the second DC-DC converter in response to an inversion signal of the second enable signal;
A third DC-DC converter generating the positive data voltage in response to a third enable signal;
A third pull-down circuit forcibly discharging an output terminal voltage of the third DC-DC converter in response to an inversion signal of the third enable signal;
A fourth DC-DC converter generating the negative data voltage in response to a fourth enable signal; And
And a fourth pull-down circuit for forcibly discharging the output terminal voltage of the fourth DC-DC converter in response to the inverted signal of the fourth enable signal.
The method of claim 2,
The first pull-down circuit,
A pull-down resistor connected to the output terminal of the first DC-DC converter;
An inverter for inverting an inversion signal of the first enable signal; And
And a transistor for conducting a current path between the pull-down resistor and a ground voltage source in response to an output signal of the inverter.
The method of claim 2,
The second pull-down circuit,
A pull-down resistor connected to the output terminal of the second DC-DC converter;
An inverter for inverting the inversion signal of the second enable signal; And
And a transistor for conducting a current path between the pull-down resistor and a ground voltage source in response to an output signal of the inverter.
The method of claim 2,
The third pull-down circuit,
A pull-down resistor connected to the output terminal of the third DC-DC converter;
An inverter for inverting the inversion signal of the third enable signal; And
And a transistor for conducting a current path between the pull-down resistor and a ground voltage source in response to an output signal of the inverter.
The method of claim 2,
The fourth pull-down circuit,
A pull-down resistor connected to the output terminal of the fourth DC-DC converter;
An inverter for inverting the inversion signal of the fourth enable signal; And
And a transistor for conducting a current path between the pull-down resistor and a ground voltage source in response to an output signal of the inverter.
A display panel including data lines, gate lines intersecting the data lines, and a plurality of electrophoretic cells, and selecting a positive data voltage and a negative data voltage according to digital video data during an image update period. And a gate driving circuit for supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during the image update period. In the method,
Inputting enable signals to a module power circuit to output the positive data voltage, the negative data voltage, the positive gate voltage, and the negative gate voltage through output terminals of the module power circuit; And
And inverting the enable signals immediately after the image update period and inputting the enable signals to the module power circuit to force discharge of the voltages of the output terminals.
The method of claim 7, wherein
Forcibly discharging the voltage of the output terminal,
Inverting the inverted signal of the enable signals input immediately after the image update period through an inverter; And
Conducting a current path between a pull-down resistor and a ground voltage source connected to an output terminal of the module power circuit immediately after the image update period by using a transistor turned on / off in response to an output signal of the inverter. Power control method of the electrophoretic display device.
KR1020100124893A 2010-12-08 2010-12-08 Electrophoresis display device and power control method thereof KR20120063768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100124893A KR20120063768A (en) 2010-12-08 2010-12-08 Electrophoresis display device and power control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100124893A KR20120063768A (en) 2010-12-08 2010-12-08 Electrophoresis display device and power control method thereof

Publications (1)

Publication Number Publication Date
KR20120063768A true KR20120063768A (en) 2012-06-18

Family

ID=46684109

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100124893A KR20120063768A (en) 2010-12-08 2010-12-08 Electrophoresis display device and power control method thereof

Country Status (1)

Country Link
KR (1) KR20120063768A (en)

Similar Documents

Publication Publication Date Title
US8264454B2 (en) Electrophoretic display and driving method thereof
KR101165842B1 (en) Mobile Liquid Crystal Display And Method for Driving the same
JP4510530B2 (en) Liquid crystal display device and driving method thereof
TWI481945B (en) Electrophoresis display device and driving method the same
JP5565098B2 (en) Electro-optical device and electronic apparatus
JP2007004109A (en) Method and apparatus for driving liquid crystal display device
KR101906421B1 (en) Electrophoresis display device and method for controling stabilization period thereof
US8564531B2 (en) Electronic apparatus and method of driving the same
KR101323049B1 (en) Electrophoresis display device and power control method thereof
JP2007011346A (en) Display device and drive apparatus for the display device
US20140078034A1 (en) Electrophoretic display device
US20120200549A1 (en) Display Device And Drive Method For Display Device
JP2011248038A (en) Electro-optic device, driving method and control circuit thereof, and electronic equipment including the same
JP6010966B2 (en) Integrated circuit device, electro-optical device and electronic apparatus
KR20130065333A (en) Electrophoresis display apparatus and method for driving the same
KR20080046934A (en) Liquid crystal display and method of driving the same
KR101117983B1 (en) A liquid crystal display device and a method for driving the same
KR20120063768A (en) Electrophoresis display device and power control method thereof
KR101864123B1 (en) Electrophoresis display device and driving method the same
KR101217158B1 (en) Liquid crystal display device
JP2011085801A (en) Tft liquid crystal drive circuit, and tft liquid crystal drive method using the same
KR100472360B1 (en) Liquid crystal display device and driving method thereof
KR101948286B1 (en) Electrophoresis display apparatus and method for driving the same
KR20060027194A (en) Flat panel display device having the same, and method for driving thereof
KR20110057956A (en) Electrophoresis display device and method of controlling a power sequence

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination