KR101864123B1 - Electrophoresis display device and driving method the same - Google Patents

Abstract

The present invention relates to a method of driving an electrophoretic display device capable of reducing manufacturing costs and improving display quality.
An electrophoretic display device according to an embodiment of the present invention includes: a display panel including gate lines and data lines and a plurality of electrophoresis cells formed so as to cross each other; A data driving circuit for selecting a positive polarity data voltage and a negative polarity data voltage according to digital video data and supplying the same to the data lines during an image data updating period; A gate driving circuit for supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during the image update period; A power supply circuit for generating and outputting the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage, and the negative polarity gate voltage through output terminals in response to the enable signals; And a plurality of discharge circuits for forcibly discharging the positive data voltage, the negative data voltage, the positive gate voltage, and the negative gate voltage in response to an inverted signal of the enable signals input immediately after the image update period. .

Description

ELECTROPHORESIS DISPLAY DEVICE AND DRIVING METHOD THE SAME [0002]

The present invention relates to an electrophoretic display device, and more particularly, to an electrophoretic display device and a method of driving the electrophoretic display device that can reduce manufacturing cost and improve display quality.

An electrophoretic display device refers to an apparatus that displays an image by using an electrophoresis phenomenon in which colored charged particles move by an electric field applied from the outside. Here, the electrophoresis phenomenon means that the charged particles move in the liquid by the Coulomb force when an electric field is applied to an electrophoretic dispersion (e-ink) in which the charged particles are dispersed in the liquid.

When a substance with a charge is placed in an electric field, the substance moves in a specific manner depending on the charge, the size and shape of the molecule, and the like. Electrophoresis is a phenomenon in which substances are separated by the difference in the degree of movement.

The electrophoretic display using electrophoresis has a characteristic of bistability, so that the original image can be displayed for a long time even when the applied voltage is removed. That is, the electrophoretic display device is suitable for the e-book field in which it is not required to swiftly change the screen because the electrophoretic display device can maintain a certain screen for a long time without continuously applying a voltage.

In addition, the electrophoretic display device has no dependency on the viewing angle, unlike the liquid crystal display device, and can provide a comfortable image on the eye to a degree similar to paper. In addition, demand is increasing as it has the advantages of flexing freely, flexibility, low power consumption and eco-like.

The electrophoretic display includes data lines, gate lines (or scan lines) that intersect the data lines, and an electrophoretic film. The data driving circuit supplies data voltages to the data lines, which are generated by a positive polarity voltage or a negative polarity voltage, according to the gradation of the data. The gate drive circuit sequentially supplies gate pulses (or scan pulses) swinging between the gate high voltage and the gate low voltage to the gate lines.

The electrophoretic display device supplies the display panel with the data voltage according to the wave form to the pixels of the display panel for switching from the current screen to the next screen. Here, since the electrophoretic display device is not fast in screen switching due to its bistability, the data voltage corresponding to the waveform, which is a sequence of image data for screen switching, is supplied to the display panel to switch from the current screen to the next screen .

At this time, the image processing apparatus has a memory function of writing new image data to the pixels through the data update process for about one second, and then keeping the current data until the next data update.

Therefore, the electrophoretic display device can reduce the power consumption because the electrophoretic display device retains the current data without supplying any external driving power due to the memory function inherent to the electrophoretic pixel.

The electrophoretic display device turns off the driving power sources according to a preset power off sequence after data update. However, due to the panel load during the power-off, the driving power sources are gradually discharged.

This causes fading off or gradation irregularities in which the currently displayed image gradually disappears during the time period during which the driving voltages are gradually discharged (several hundreds ms to several seconds). This is disadvantageous in that the display quality is degraded due to fading off and non-uniformity of the gradation due to the discharge delay of the driving voltages.

Korean Patent Publication No. 10-2008-0001208, Korean Patent Laid-Open No. 10-2008-0054779 discloses an electrophoretic display device and a driving method. However, the electrophoretic display devices proposed so far have problems of fading off due to discharge delay of driving voltages and display quality degradation due to non-uniformity of gradation.

Disclosure of Invention Technical Problem [8] Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an electrophoretic display device and a method of driving the electrophoretic display device capable of preventing discharge delays of driving voltages immediately after image data update, .

An object of the present invention is to provide an electrophoretic display device and a method of driving the electrophoretic display device capable of preventing display quality from being lowered due to a discharge delay of driving voltages immediately after image data update.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

An electrophoretic display device according to an embodiment of the present invention includes: a display panel including gate lines and data lines and a plurality of electrophoresis cells formed so as to cross each other; A data driving circuit for selecting a positive polarity data voltage and a negative polarity data voltage according to digital video data and supplying the same to the data lines during an image data updating period; A gate driving circuit for supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during the image update period; A power supply circuit for generating and outputting the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage, and the negative polarity gate voltage through output terminals in response to the enable signals; And a plurality of discharge circuits for forcibly discharging the positive data voltage, the negative data voltage, the positive gate voltage, and the negative gate voltage in response to an inverted signal of the enable signals input immediately after the image update period. ; And

The power supply circuit of the electrophoretic display device according to the embodiment of the present invention includes a first DC-DC converter for generating the positive gate voltage in response to a first enable signal; A second DC-DC converter for generating the negative gate voltage in response to a second enable signal; A third DC-DC converter for generating the positive polarity data voltage in response to a third enable signal; And a fourth DC-DC converter for generating the negative data voltage in response to the fourth enable signal.

The plurality of discharge circuits of the electrophoretic display device according to the embodiment of the present invention includes a first discharge circuit for forcibly discharging the output terminal voltage of the first DC-DC converter in response to an inverted signal of the first enable signal ; A second discharging circuit for forcibly discharging the output terminal voltage of the second DC-DC converter in response to an inverted signal of the second enable signal; A third discharging circuit for forcibly discharging the output terminal voltage of the third DC-DC converter in response to an inverted signal of the third enable signal; And a fourth discharge circuit for forcibly discharging the output terminal voltage of the fourth DC-DC converter in response to an inverted signal of the fourth enable signal.

The first discharge circuit to the fourth discharge circuit of the electrophoretic display device according to the embodiment of the present invention are packaged together with the power supply circuit and directly formed.

The first discharge circuit and the second discharge circuit of the electrophoretic display device according to the embodiment of the present invention are formed in the data driving circuit and the third discharge circuit and the fourth discharge circuit are formed in the gate drive circuit .

A method of driving an electrophoretic display according to an embodiment of the present invention includes a display panel including gate lines and data lines and a plurality of electrophoresis cells formed to cross each other, and driving circuits for driving the display panel A method of driving an electrophoretic display, comprising: supplying a gate pulse to a gate pulse swinging between a positive gate voltage and a negative gate voltage during an image update period; Selecting and supplying a positive polarity data voltage and a negative polarity data voltage to the data lines according to the digital video data during the image data update period; And generating and outputting the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage, and the negative polarity gate voltage through output terminals in response to the enable signals generated by the control unit among the driving circuits ; And forcibly discharging the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage and the negative polarity gate voltage of the output terminals in response to an inverted signal of the enable signals input immediately after the image update period ; And

The electrophoretic display device and the driving method thereof according to the embodiment of the present invention discharge the output terminal voltage of the module power supply circuit immediately after the update of the image data to reduce the display quality degradation due to the discharge delay of the driving voltages immediately after the update of the image data .

The electrophoretic display device and the driving method thereof according to the embodiment of the present invention can provide an electrophoretic display device and a driving method thereof that can prevent discharge delay of driving voltages immediately after image data update and can force discharge of driving voltages have.

Other features and effects of the present invention may be newly understood through the embodiments of the present invention in addition to the features and effects of the present invention mentioned above.

1 is a block diagram showing an electrophoretic display device according to a first embodiment of the present invention;
Fig. 2 is a detailed view of the microcapsule structure of the pixel shown in Fig. 1. Fig.
3 is a detailed view of the microcup structure of the pixel shown in Fig.
4 is a diagram showing an example of a power-on sequence;
5 is a diagram showing an example of a power-off sequence;
FIG. 6 is a detailed circuit diagram of the power supply circuit shown in FIG. 1. FIG.
Fig. 7 is a circuit diagram showing details of the first DC-DC converter and the first discharge circuit shown in Fig. 6; Fig.
8 and 9 are block diagrams showing an electrophoretic display device according to a second embodiment of the present invention.
10 is a detailed view of the power supply circuit and the discharge circuit shown in Figs. 8 and 9. Fig.
11 is a circuit diagram showing details of the DC-DC converters and the discharge circuits shown in Figs. 8 and 9. Fig.
12 is a circuit diagram showing in detail the third direct-current (DC-DC) converter and the fourth direct-current (DC-DC) converter and the second discharge circuit shown in FIG.
13 is a view showing a power control method of the electrophoretic display device according to the embodiments of the present invention.

Hereinafter, an electrophoretic display device and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, detailed descriptions of configurations / functions that are not related to the core configuration of the present invention and those known in the technical field of the present invention can be omitted.

1 is a block diagram showing an electrophoretic display device according to a first embodiment of the present invention.

Referring to FIG. 1, an electrophoretic display device according to a first embodiment of the present invention includes a display panel 110; A data driving circuit 120; A gate drive circuit 130; A control unit 140; And a power supply circuit 200.

The display panel 110 is formed so that m data lines 114 and n gate lines 115 intersect with each other and the intersection of the data lines 114 and the gate lines 115 causes m x n pixels (Ce) are formed in a matrix form.

FIG. 2 is a detailed view of the microcapsule structure of the pixel shown in FIG. 1, and FIG. 3 is a view illustrating the microcup structure of the pixel shown in FIG. 1 in detail.

Referring to FIG. 2, an electrophoretic film including a plurality of microcapsules 103 is interposed between the pixel electrode 111 and the common electrode 112 of the display panel 110.

Here, when the electrophoretic display device displays a monochrome image, the microcapsule 103 includes a plurality of white charged particles 104 colored white and a plurality of black charged particles 105 colored in black, And a solvent which allows the charged particles 104 and the black charged particles 105 to flow by electrophoresis.

At this time, the white charged particles 104 are charged with a negative polarity, the black charged particles 105 can be charged with a positive polarity, and white charged particles 104 and black The charged particles 105 are moved by electrophoresis to display an image.

In FIG. 2, the electrophoretic layer is formed through the electrophoretic film. On the other hand, as shown in FIG. 3, the electrophoretic layer can be formed by the microcup structure.

A pixel electrode 111 is formed on a lower substrate 106 and a barrier rib 107 is formed of a non-polar organic or non-polar inorganic material so as to surround the pixel electrode 111 to define a filling space.

The electrophoretic layer may be formed by filling the electrophoretic dispersion composed of the white charged particles 104, the black charged particles 105 and the solvent 108 in the filling space defined by the partition wall 107. [

2 and 3, since the common electrode 112 is located on the side where an image is displayed, the common electrode 112 is formed of a transparent electrode, and may be formed of ITO (Indium Tin Oxide), for example.

The pixel electrode 111 is not necessarily formed of a transparent material because it is located on the opposite side of the display screen, and may be formed of ITO (Indium Tin Oxide) or an opaque metal.

Here, the pixel electrode is formed on the lower substrate of the display panel 110, and the common electrode 112 is formed on the upper substrate of the display panel 110.

The lower substrate and the upper substrate of the display panel 110 may be formed of a glass substrate, a metal substrate, a flexible plastic substrate, or the like.

The data lines 114 and the gate lines 115 are formed on the lower substrate and the TFTs are formed on the intersecting regions of the data lines 114 and the gate lines 115.

The gate electrode of the TFTs is connected to the gate line 115, the source electrode thereof is connected to the data line 114, and the drain electrode is formed to be connected to the pixel electrode 111. [

The TFTs are turned on according to the scan pulse from the gate line 115 to select one line of pixels Ce to be displayed. And supplies the data voltages from the data lines 114 to the pixels Ce selected by the scan signals to supply the data voltages to the pixel electrodes 111. [

When the positive voltage Vpos, that is, the positive data voltage, is applied to the pixel electrode 111 of the pixel Ce, the white charged particles 104 of the pixel Ce move to the lower portion of the pixel, 105 are moved to the upper portion of the pixel. Therefore, the black charged particles 105 absorb the light incident from the outside of the pixel Ce and display the black gradation.

On the other hand, when the negative voltage Vneg, that is, the negative data voltage, is applied to the pixel electrode 111 of the pixel Ce, the black charged particles 105 of the pixel Ce move to the lower portion of the pixel, The charged particles 104 are moved to the upper portion of the pixel. Accordingly, the white charged particles 104 reflect the light incident from the outside of the corresponding pixel Ce to display white gradation.

New image data is written to the pixels Ce during the update of the image data using the waveform. That is, the data voltage according to the waveform is applied. After the update of the image data, the pixels Ce maintain the gradation of the currently written image data until the update of the next image data.

A common electrode 112 for supplying a common voltage Vcom to all the pixels Ce is formed on the upper substrate of the display panel 110. When the electrophoretic display device displays a color image, a color filter for converting light into color light of red, green, and blue may be formed on the upper substrate.

The data driving circuit 120 generates a positive or negative polarity data voltage according to the image data supplied from the controller 140 and supplies the positive or negative polarity data voltage to the data lines 114 of the display panel 110.

The gate driving circuit 130 generates a scan pulse in accordance with a gate control signal supplied from the control unit 140 and supplies the generated scan pulse to the gate lines 115 of the display panel 110.

The control unit 140 generates a data control signal for controlling the data driving circuit 120 based on the inputted horizontal synchronizing signal H, vertical synchronizing signal V, clock signal CLK and image data And generates a gate control signal for controlling the gate drive circuit 130.

The control signals include a source timing control signal for controlling the operation timing of the data driving circuit 120. And a gate timing control signal for controlling the operation timing of the gate driving circuit 130.

In order to switch from the current screen to the next screen, the controller 140 converts the image data for one frame to several tens of frames into a sequence form to generate a waveform, and transmits the generated waveform to the data driving circuit 120. [ . Further, the control unit 140 supplies a data control signal to the data driving circuit 120, and supplies the gate control signal to the gate driving circuit 130.

In this case, the control unit 140 may use a frame memory that stores an input image, and a lookup table in which a data voltage waveform is set, digital data set by the current gradation state of the pixel and the next state of the pixel to be updated, To the data driving circuit 120 in the form of a signal.

The data driving circuit 120 supplies data voltages of positive (+), negative (-), or ground voltage (Vss) to the display panel 110 according to the digital data input from the controller during the image data update period.

For example, the data driving circuit 120 outputs a positive data voltage Vpos when the digital data input from the control unit 140 is '00' during the image data update period.

The data driving circuit 120 outputs a negative data voltage Vneg of -15 V when the digital data input from the control unit 140 is '01' during the update period of the image data.

The data driving circuit 120 outputs a base voltage Vss of 0V as a data voltage when the digital data input from the control unit 140 is '10' or '11' during the update period of the image data.

Accordingly, the data driving circuit 120 selects one of the three-phase voltages Vpos, Vneg, and Vss as the data voltage in response to the digital data input in the form of a waveform from the controller 140 in the course of updating the image data do. Then, the selected data voltage is output to the data lines 114. The output voltages Vpos, Vneg and Vss of the data driving circuit 120 are supplied to the pixel electrode 111 of the pixel Ce via the data line 114 and the TFT.

The gate driving circuit 130 sequentially outputs scan pulses synchronized with the data voltage supplied to the data lines 114 during the update period of the image data. The scan pulses swing between the positive (+) gate voltage (GVDD) and the negative (-) gate voltage (GVEE).

When the power source of the electrophoretic display device is turned on, the power source circuit 200 supplies a DC-DC converter (DC-DC converter) according to a preset power on sequence (Vcc, Vcom, Vpos, Vneg, GVDD, GVEE, and Vss) necessary for driving the display panel 110 using the input voltage Vin.

The generated driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE are supplied to the data driving circuit 120 and the gate driving circuit 130. At this time, the power-on sequence may be preset in the control unit 140 or an external host system.

When the input voltage Vin is applied to the power supply circuit 200, the power supply circuit 200 supplies the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE, which are input from the controller 140 or the host system, (Vcc, Vcom, Vpos, Vneg, GVDD, GVEE, and Vss) in response to the enable signals.

The logic power supply voltage Vcc is applied to the application specific integrated circuit (ASIC) of the control unit 140, the source drive IC (Integrated Circuit) of the data drive circuit 120, the logic necessary for driving the gate drive IC of the gate drive circuit 130 And is generally generated as a direct current voltage of 3.3 V as a voltage.

The positive polarity data voltage Vpos is generated with a direct voltage of + 15V and the negative voltage Vneg is generated with a direct voltage of -15V.

The common voltage is generated by a DC voltage between 0V and -2V or between -2V and 0V. The negative gate voltage (GVEE) is generated with a DC voltage of -20V. The positive gate voltage (GVDD) is generated by a DC voltage of + 22V.

The power supply circuit 200 quickly discharges the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE according to a predetermined power off sequence immediately after the update of the image data. At this time, the power-off sequence may be preset in the control unit 140 or the host system.

The control unit 140 or the host system inverts the enable signal of each of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE according to the power-on sequence immediately after the update of the image data. As a result, the power supply circuit 200 discharges the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE to ground (GND) in response to the inverted enable signals (or the disable signal).

A method for updating an image on the display panel 110 is disclosed in Korean Patent Application Publication No. 10-2008-0054779 (2008. 06. 19) filed by the present applicant, Korean Patent Application Publication No. 10-2008-0054781 2008. 06. 19), Korean Patent Publication No. 10-2008-0055331 (2008. 06. 19), Korean Patent Publication No. 10-2008-0058956 (2008. 06. 26), Korean Patent Laid- 10-2008-0083425 (2008. 09. 18), Korean Patent Publication No. 10-2008-0090185 (2008. 10. 08), Korean Patent Publication No. 10-2009-0105488 ) Can be used.

4 is a diagram showing an example of a power-on sequence.

Referring to FIG. 4, when the power source of the electrophoretic display device is turned on, the external host system supplies the input voltage Vin to the power source circuit 200. The host system or the control unit 140 supplies the enable signals of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE to the power supply circuit 200 based on the preset power-on sequence.

The power supply circuit 200 outputs the positive gate voltage GVDD after outputting the negative gate voltage GVEE when the enable signal of the driving voltages is inputted from the host system or the control unit 140 )do. Then, the positive polarity data voltage Vpos and the negative polarity data voltage Vneg are outputted (?).

5 is a diagram showing an example of a power-off sequence.

5, immediately after the update of the image data, the host system or the control unit 140 controls the enable signals of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE based on the preset power- .

The power supply circuit 200 discharges the positive gate voltage GVDD to the ground GND in response to the inverted enable signal and then discharges the negative gate voltage GVEE to the ground GND ). Thereafter, the positive polarity data voltage Vpos and the negative polarity data voltage Vneg are discharged to the ground GND.

Hereinafter, the driving method of the driving voltages Vpos, Vneg, GVDD, and GVEE will be described in detail with reference to FIGS. 6 and 7. FIG.

FIG. 6 is a detailed circuit diagram of the power supply circuit shown in FIG. 1. FIG.

Referring to FIG. 6, the power supply circuit 200 includes first to fourth DC-DC converters 210 to 240 and first to fourth discharge circuits 250 to 280, respectively.

A DC voltage Vin of 5V, 9V, 12V, or the like is supplied to the first to fourth DC-DC converters 210 to 240. When the enable signals GVDD_EN, GVEE_EN, Vpos_EN, and Vneg_EN are input as the first logic value (for example, High), the first to fourth DC-DC converters 210 to 240 output the output drive voltages GVDD and GVEE , Vpos, Vneg).

Each of the first to fourth discharge circuits 250 to 280 quickly outputs the output voltages of the first to fourth DC-DC converters 210 to 240 to the ground GND in response to the inverted enable signals. Discharge.

7 is a circuit diagram showing the details of the first DC-DC converter and the discharging circuit shown in Fig.

7, the basic circuit configuration and operation method of the second to fourth DC-DC converters 220 to 240 are the same as those of the first DC-DC converter 220, except that the output drive voltages GVDD, GVEE, Vpos, and Vneg are different. DC converter < RTI ID = 0.0 > 210 < / RTI >

Accordingly, the configuration and the driving method of the second to fourth DC-DC converters 220 to 240 can be fully understood through the description of the first DC-DC converter 210, and a detailed description thereof will be omitted.

The first DC-DC converter 210 includes a power control IC 211, an inductor L, a diode D, resistors VR1 and R1, capacitors C1 to C3, and the like.

The inductor L charges the input current to increase the output voltage. The diode D is connected between the inductor L and the output terminal of the first DC-DC converter 210 to cut off the reverse current.

The resistors VR1 and R1 are connected between the output terminal of the first DC-DC converter 210 and the ground GND to constitute a feedback voltage dividing circuit. The reference voltage is detected through the partial pressure of the output voltage GVDD_out and input to the feedback terminal FB of the power control IC 211. [

The first capacitor (C1) stabilizes the input terminal voltage of the first DC-DC converter (210).

The second capacitor C2 is connected between the node between the variable resistor VR1 and the resistor R1 constituting the feedback voltage divider circuit and the ground GND and supplied to the feedback terminal FB of the power control IC 211 Thereby eliminating the noise mixed into the reference voltage.

The third capacitor (C3) stabilizes the output terminal voltage of the first DC-DC converter (210).

The power control IC 211 operates when the first enable signal GVDD_EN input to the shutdown terminal SHDN is high logic to generate the output voltage GVDD_out.

In addition, the power control IC 211 maintains the output voltage constant when the reference voltage is varied due to the load of the display panel 110 according to the reference voltage input from the feedback terminal FB.

For example, when the reference voltage is varied due to the load of the display panel 110, the built-in transistor SW is controlled by a PWM (Pulse Width Modulation) method to change the current flowing through the current path between the inductor L and the diode D Thereby maintaining the output voltage constant.

When the first enable signal GVDD_EN is inverted by the power supply unit immediately after the image data is updated, the power control IC 211 cuts off the current path between the inductor L and the diode D to generate the output voltage GVDD_out, .

The first discharge circuit 250 includes an inverter INV, a transistor Q and a variable resistor VR2.

The inverter INV inverts the first enable signal GVDD_EN and inputs the inverted signal to the gate electrode of the transistor Q. [

The transistor Q may be implemented as an N-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or a P-channel MOSFET.

The transistor Q discharges the output voltage GVDD_out of the first DC-DC converter 210 to ground (GND) in response to the inverted enable signal / GVDD_EN input through the inverter INV.

Here, the gate electrode of the transistor Q is connected to the output terminal of the inverter INV. The source electrode of the transistor Q is connected to the ground GND and the drain electrode of the transistor Q is connected to the output terminal of the first DC-DC converter 210 through the variable resistor VR2.

The variable resistor VR2 can adjust the output voltage discharge rate of the first DC-DC converter 210 according to the resistance value thereof.

The first enable signal GVDD_EN is inverted to low logic immediately after the update of the image data. Then, the first enable signal GVDD_EN of the low logic is inverted to the high logic of the inverter INV to turn on the transistor Q. As a result, immediately after the update of the image data, the output voltage GVDD of the first DC-DC converter 210 is quickly discharged to the ground GND.

Similarly, the second to fourth discharge circuits 260 to 280 output the output voltages (GVEE, Vpos, Vneg) of the second to fourth DC-DC converters 220 to 240 immediately after image data update Discharges to the ground at a low voltage (Vss).

That is, the second discharging circuit 260 discharges the GVEE_out voltage output from the second DC-DC converter 220 to the base voltage Vss immediately after the image data update.

The third discharge circuit 270 rapidly discharges the Vpos_out voltage output from the third DC-DC converter 230 to the base voltage Vss immediately after the image data update.

The fourth discharge circuit 280 quickly discharges the Vpos_out voltage output from the fourth DC-DC converter 240 to the base voltage Vss immediately after the image data update.

The first to fourth DC-DC converters 210 to 240 and the first to fourth discharge circuits 250 to 280 may be directly integrated into one package.

However, the present invention is not limited thereto. In another embodiment of the present invention, the first to fourth DC-DC converters 210 to 240 are directly integrated into one package, and the first to fourth discharge circuits 250 to 280 And may be directly converted into a single package.

Meanwhile, the first to fourth DC-DC converters 210 to 240 and the first to fourth discharge circuits 250 to 280 may be implemented independently.

The inverter INV and the transistor Q are omitted from the first to fourth discharge circuits 250 to 280 and the pull-down resistor VR2 is connected to the DC-DC converters 220 to 240, And the ground (GND).

In this case, if the resistance value of the pull-down resistor VR2 is decreased, the output of the first DC-DC converter 210 leaks through the small pull-down resistor VR2 even in the image data update process, The power consumption increases. In order to prevent the current loss, if the resistance value of the pull-down resistor VR2 is increased, the discharge effect is reduced.

Therefore, the present invention is characterized in that an inverter and a transistor Q are added to the first to fourth discharge circuits 250 to 280 so that the first to fourth DC- The down resistance can be increased to several MΩ to prevent current loss.

Also, when the first to fourth DC-DC converters 210 to 240 stop the output, the pull-down resistance of the output terminal may be reduced to several ohms to quickly discharge the output voltage.

The electrophoretic display device completes the manufacture of the display panel module through the cell process of forming the pixel on the display panel 110 by the module manufacturer and the module process of connecting the driving circuit portion for driving the display panel 110.

Then, the set maker releases the electrophoretic display device of finished product through program mounting and case assembly process for driving the display panel module in accordance with the model of the set.

In the case where the first to fourth discharge circuits 250 to 280 are not included in the display panel module, the set vendor sets the first to fourth discharge voltages for discharging the driving voltages Vpos, Vneg, GVDD, and GVEE. It is troublesome to perform the FPC process of connecting the power rail discharge circuit to the display panel module after manufacturing the discharge circuits 250 to 280, that is, the power rail discharging circuit, The manufacturing cost of the electrophoretic display device is increased.

Therefore, in order to lessen the manufacturing burden of the set maker in manufacturing the electrophoretic display device, the electrophoretic display device should be manufactured in the form of being included in the first to fourth discharge circuits 250 to 280 in the display panel module.

Hereinafter, the electrophoretic display device and the driving method thereof according to the second embodiment will be described with reference to FIGS. 8 to 12. FIG. In the second embodiment of the present invention, an electrophoretic display device included in the first to fourth discharge circuits 250 to 280 is proposed for the display panel module.

8 to 12, a detailed description of the same configuration and driving method as those of the first embodiment of the present invention can be omitted in the description of the second embodiment of the present invention.

8 and 9 are block diagrams showing an electrophoretic display device according to a second embodiment of the present invention.

8 and 9, an electrophoretic display device according to a second embodiment of the present invention includes a display panel 110; A data driving circuit 120; A gate drive circuit 130; A control unit 140; And a power supply circuit 200.

The control unit 140 generates a data control signal for controlling the data driving circuit 120 based on the inputted horizontal synchronizing signal H, vertical synchronizing signal V, clock signal CLK and image data And generates a gate control signal for controlling the gate drive circuit 130.

The controller 140 generates first to fourth enable signals Vpos_EN, Vneg_EN, GVDD_EN, and GVEE_EN for discharging the first to fourth driving voltages Vpos, Vneg, GVDD, and GVEE.

The controller 140 supplies the generated first enable signal Vpos_EN and the second enable signal Vneg_EN to the data driving circuit 130. Then, the controller 140 supplies the generated third enable signal GVDD_EN and the fourth enable signal GVEE_EN to the gate driving circuit 130.

In order to switch from the current screen to the next screen, the controller 140 converts the image data for one frame to several tens of frames into a sequence form to generate a waveform, and transmits the generated waveform to the data driving circuit 120. [ . Further, a data control signal is supplied to the data driving circuit 120, and a gate control signal is supplied to the gate driving circuit 130.

The data driving circuit 120 generates a data voltage according to the image data supplied from the control unit 140 and supplies the generated data voltage to the data lines 114 of the display panel 110.

The data driving circuit 120 generates a first driving voltage Vpos supplied from the power supply circuit 300 using the first enable signal Vpos_EN and the second enable signal Vneg_EN supplied from the controller 140, And the second driving voltage Vneg to the ground voltage Vss.

To this end, the data driving circuit 120 includes a first discharging circuit 410. A detailed description of the first discharge circuit 410 will be given later with reference to FIGS. 10 and 11. FIG.

The gate driving circuit 130 generates a scan pulse in accordance with the gate control signal supplied from the control unit 140 and supplies the generated scan pulse to the gate lines 115 of the display panel 110.

The gate driving circuit 130 receives the third driving voltage GVDD supplied from the power supply circuit 300 using the third enable signal GVDD_EN and the fourth enable signal GVEE_EN supplied from the controller 140, And the fourth driving voltage GVEE to the ground voltage Vss.

To this end, the gate drive circuit 130 includes a second discharge circuit 420. A detailed description of the second discharge circuit 420 will be given later with reference to FIGS. 10 and 11. FIG.

New image data is written to the pixels Ce of the display panel 110 in the process of updating image data using a waveform. After the update of the image data, the pixels Ce maintain the gradation of the currently written image data until the update of the next image data.

To this end, the data driving circuit 120 supplies positive (+), negative (-) or base low voltage (Vss) to the display panel 110 according to the digital data input from the control unit during the image data update period.

For example, the data driving circuit 120 outputs a positive data voltage Vpos of + 15V when the digital data input from the control unit 140 is '00' during the image data update period.

The data driving circuit 120 outputs a negative data voltage Vneg of -15 V when the digital data inputted from the control unit 140 is '01' during the update period of the image data.

The data driving circuit 120 outputs a base voltage Vss of 0V as a data voltage when the digital data input from the control unit 140 is '10' or '11' during the update period of the image data.

Accordingly, the data driving circuit 120 selects one of the three-phase voltages Vpos, Vneg, and Vss as the data voltage in response to the digital data input from the controller 140 in the process of updating the image data. Then, the selected data voltage is output to the data lines 114. The output voltages Vpos, Vneg and Vss of the data driving circuit 120 are supplied to the pixel electrodes 111 of the pixel Ce via the data lines 114 and the TFTs.

The gate driving circuit 130 sequentially outputs scan pulses synchronized with the data voltage supplied to the data lines 114 during the update period of the image data. The scan pulses swing between the positive (+) gate voltage (GVDD) and the negative (-) gate voltage (GVEE).

When the power source of the electrophoretic display device is turned on, the power source circuit 300 drives the display panel 110 using the input voltage Vin through the DC-DC converter according to a preset power on sequence (Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE) necessary for the driving of the display device.

The generated driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE are supplied to the data driving circuit 120 and the gate driving circuit 130. At this time, the power-on sequence may be preset in the control unit 140 or an external host system.

When the input voltage Vin is applied to the power supply circuit 300, the power supply circuit 300 generates the driving voltages Vcc, Vcom, Vpos, Vneg, Vss, and Vss in response to the enable signals input from the controller 140 or the host system. GVDD, GVEE).

The logic power supply voltage Vcc is applied to the application specific integrated circuit (ASIC) of the control unit 140, the source drive IC (Integrated Circuit) of the data drive circuit 120, the logic necessary for driving the gate drive IC of the gate drive circuit 130 And is generally generated as a direct current voltage of 3.3 V as a voltage.

The positive polarity data voltage Vpos is generated with a direct voltage of + 15V and the negative voltage Vneg is generated with a direct voltage of -15V.

The common voltage is generated by a DC voltage between 0V and -2V or between -2V and 0V. The negative gate voltage (GVEE) is generated with a DC voltage of -20V. The positive gate voltage (GVDD) is generated by a DC voltage of + 22V.

Here, the first to fourth drive voltages Vpos, Vneg, GVDD, and GVEE must be rapidly discharged according to a predetermined power off sequence immediately after the update of the image data. At this time, the power-off sequence may be supplied to the control unit 140 or the host system in advance, and may be supplied to the data driving circuit 120 and the gate driving circuit 130.

To this end, the control unit 140 or the host system inverts the enable signal of each of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE according to the power-on sequence immediately after the update of the image data.

As a result, the first discharging circuit 410 formed in the data driving circuit 120 and the second discharging circuit 420 formed in the gate driving circuit 130 are turned on in response to the inverted enable signals (or the disable signal) And discharges the first to fourth driving voltages Vpos, Vneg, GVDD, and GVEE to ground (GND).

As shown in FIG. 4, when the power source of the electrophoretic display device is turned on, the external host system supplies the input voltage Vin to the power source circuit 300. The host system or the control unit 140 supplies the enable signals of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE to the data driving circuit 120 and the gate driving circuit 130 based on the preset power- .

9, the first enable signal Vpos_EN and the second enable signal Vneg_EN are supplied to the data driving circuit 120, and the third enable signal GVDD_EN and the fourth enable signal The enable signal GVEE_EN is supplied to the gate driving circuit 130.

The power supply circuit 300 outputs the positive gate voltage GVDD after outputting the negative gate voltage GVEE when the enable signal of the driving voltages is input from the host system or the control unit 140. [ Then, the positive polarity data voltage Vpos and the negative polarity data voltage Vneg are output.

5, immediately after the update of the image data, the host system or the control unit 140 sets the enable signals of the driving voltages Vcc, Vcom, Vpos, Vneg, GVDD, and GVEE to a predetermined power on sequence .

Here, when the first enable signal Vpos_EN and the second enable signal Vneg_EN are input from the controller 140, the data driving circuit 120 outputs the positive polarity data voltage Vpos and the negative polarity data voltage Vneg, To ground (GND).

When the third enable signal GVDD_EN and the fourth enable signal GVEE_EN are inputted, the gate driving circuit 130 applies the positive gate voltage GVDD and the negative gate voltage GVEE to the ground GND, .

Hereinafter, the driving method of the driving voltages Vpos, Vneg, GVDD, and GVEE will be described in detail with reference to FIGS. 10 and 11. FIG.

Fig. 10 is a detailed circuit diagram of the power supply circuit and the discharge circuit shown in Figs. 8 and 9. Fig.

Referring to FIG. 10, the power supply circuit 300 includes first to fourth DC-DC converters 310 to 340. The data driving circuit 120 includes a first discharging circuit 410 and the gate driving circuit 130 includes a second discharging circuit 420.

Here, a DC voltage Vin of 5V, 9V, 12V, or the like is supplied to the first to fourth DC-DC converters 310 to 340. When the enable signals GVDD_EN, GVEE_EN, Vpos_EN and Vneg_EN are generated in the control unit 140 to a first logic value (for example, High), the first to fourth DC-DC converters 310 to 340 1 to the fourth drive voltages GVDD, GVEE, Vpos, and Vneg.

The first discharging circuit 410 included in the data driving circuit 120 receives the first driving voltage Vpos and the second driving voltage Vpos in response to the first enable signal Vpos_EN and the second enable signal Vneg_EN, The voltage Vneg is quickly discharged to the ground GND.

The second discharging circuit 420 included in the gate driving circuit 130 receives the third driving voltage GVDD and the fourth driving voltage GVDD in response to the third enable signal GVDD_EN and the fourth enable signal GVEE_EN, And discharges the voltage (GVEE) to the ground (GND) quickly.

11 is a circuit diagram showing details of the DC-DC converters and the discharge circuits shown in Figs. 8 and 9. Fig.

The basic circuit configuration and operation method of the second DC-DC converter 320 is substantially the same as that of the first DC-DC converter 310 except that the output drive voltages Vpos, Vneg are different.

The basic circuit configuration and operation method of the third DC-DC converter 330 and the fourth DC-DC converter 340 are the same as those of the first DC-DC converter 340 except that the output drive voltages GVDD and GVEE are different 310). ≪ / RTI >

 Therefore, the configuration and driving method of the second to fourth DC-DC converters 320 to 340 can be fully understood through the description of the first DC-DC converter 310, and a detailed description thereof will be omitted.

Referring to FIG. 11, the first DC-DC converter 310 includes a power control IC 301, an inductor L, a diode D, resistors VR1 and R1, capacitors C1 to C3, .

The inductor L charges the input current to increase the output voltage. The diode D is connected between the inductor L and the output terminal of the first DC-DC converter 310 to block reverse current.

The resistors VR1 and R1 are connected between the output terminal of the first DC-DC converter 310 and the ground GND to divide the output voltage Vpos_out. Thereby, the reference voltage is inputted to the feedback terminal (FB) of the power control IC (301).

The first capacitor (C1) stabilizes the input terminal voltage of the first DC-DC converter (310).

The second capacitor C2 is connected between a node between the variable resistor VR1 and the resistor R1 constituting the feedback voltage divider circuit and the ground GND and supplied to the feedback terminal FB of the power control IC 301 Thereby eliminating the noise mixed into the reference voltage.

The third capacitor (C3) stabilizes the output terminal voltage of the first DC-DC converter (310).

The power control IC 301 operates when the first enable signal GVDD_EN input to the shutdown terminal SHDN is high logic to generate the output voltage Vpos_out.

The power control IC 301 maintains the output voltage Vpos_out constant when the reference voltage is varied due to the load of the display panel 110 according to the reference voltage input from the feedback terminal FB.

For example, when the reference voltage is varied due to the load of the display panel 110, the built-in transistor SW is controlled by a PWM (Pulse Width Modulation) method to change the current flowing through the current path between the inductor L and the diode D Thereby maintaining the output voltage constant.

When the first enable signal Vpos_EN is inverted immediately after the image data is updated, the power control IC 301 interrupts the current path between the inductor L and the diode D to generate the output voltage Vpos_out Stop.

The first discharge circuit 410 formed in the data driving circuit 120 includes an inverter INV, a transistor Q and a variable resistor VR2.

The inverter INV inverts the first enable signal Vpos_EN and inputs the inverted signal to the gate electrode of the transistor Q. [

The transistor Q may be implemented as an N-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or a P-channel MOSFET.

The transistor Q discharges the output voltage GVDD_out of the first DC-DC converter 310 to ground (GND) in response to the inverted enable signal / GVDD_EN input through the inverter INV.

Here, the gate electrode of the transistor Q is connected to the output terminal of the inverter INV. The source electrode of the transistor Q is connected to the ground GND and the drain electrode of the transistor Q is connected to the output terminal of the first DC-DC converter 210 through the variable resistor VR2.

The variable resistor VR2 may adjust the output voltage discharge rate of the first DC-DC converter 310 according to the resistance value.

The first enable signal Vpos_EN is inverted to low logic immediately after the update of the image data. Then, the first enable signal Vpos_EN of the low logic is inverted to the high logic of the inverter INV to turn on the transistor Q. As a result, immediately after the update of the image data, the first output voltage Vpos of the first DC-DC converter 310 is quickly discharged to the ground (GND).

Also, the second enable signal Vneg_EN is inverted to low logic immediately after the update of the image data. Then, the second enable signal Vneg_EN of the low logic is inverted to the high logic of the inverter INV to turn on the transistor Q. [ As a result, immediately after the update of the image data, the second output voltage Vneg of the second DC-DC converter 320 is quickly discharged to the ground GND.

Likewise, the second discharging circuit 420 is responsive to the third enable signal GVDD_EN and the fourth enable signal GVEE_EN input from the control unit 140 to turn on the third and fourth DC-DC converters (GVDD, GVEE) of the pixel cells 330 to 340 to the base voltage Vss immediately after the image data update.

That is, the second discharge circuit 420 quickly discharges the GVDD_out voltage output from the third DC-DC converter 330 to the base voltage Vss immediately after the image data update.

Then, the GVEE_out voltage output from the fourth DC-DC converter 340 is discharged quickly to the base voltage Vss immediately after the image data update.

The first to fourth DC-DC converters 310 to 340 may be directly integrated into one package. The first discharging circuit 410 may be directly packaged in the data driving circuit 120 and the second discharging circuit 420 may be packaged in the gate driving circuit 130.

As another example of the present invention, in the first and second discharge circuits 410 to 420, the inverter INV and the transistor Q are omitted and the pull-down resistor VR2 is connected to the DC-DC converters 310 to 340, And the ground (GND).

The present invention is characterized in that an inverter and a transistor Q are added to the first and second discharge circuits 410 and 420 so that the pull-down resistance of the output terminal during the operation of the first to fourth DC- Can be increased to the level of several MΩ to prevent current loss. In addition, when the DC-DC converters 310 to 340 stop the output, the pull-down resistance of the output terminal may be reduced to several ohms to quickly discharge the output voltage.

13 is a diagram illustrating a power control method of the electrophoretic display device according to the embodiments of the present invention.

Referring to FIG. 13, when the power source of the electrophoretic display device is turned on (S1), the power source circuit drives the display panel 110 in response to the enable signals generated according to the power- And outputs the necessary first to fourth driving voltages GVDD, GVEE, Vpos and Vneg (S2).

At this time, the first to fourth enable signals Vpos_EN, Vneg_EN, GVDD_EN, and GVEE_EN are generated to maintain the first to fourth driving voltages Vpos, Vneg, GVDD, and GVEE or discharge to the ground (GND) do.

If the new image is not updated in the display panel 110, the first to fourth driving voltages Vpos, Vneg, GVDD, and GVEE supplied to the display panel 110 are maintained (S4).

When new data is input from the user or the outside and the new image is updated in the display panel 110 in step S3, the controller 110 or the host system outputs the first to fourth enable signals Vpos_EN, Vneg_EN, GVDD_EN, GVEE_EN) (S5).

Then, the power supply circuit 200 generates the first to fourth driving voltages GVDD, GVDD, and GVDD in response to the inverted first to fourth enable signals Vpos_EN, Vneg_EN, GVDD_EN, and GVEE_EN according to the power- , GVEE, Vpos, Vneg).

In addition, the discharge circuits 210 to 240 or 410 and 420 rapidly discharge the first to fourth drive voltages GVDD, GVEE, Vpos, and Vneg to the ground GND in response to the inverted enable signal. (S6).

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

103: microcapsules 104, 105: charged particles
106: lower substrate 107: partition wall
108: solvent 109: upper substrate
110: display panel 111: pixel electrode
112: common electrode 114: data line
115: gate line 120: data driving circuit
130: Gate driving circuit 140:
200: power supply circuits 210 to 240, 310 to 340: DC-DC converter
211: Power control ICs 250 to 280, 410, 420: Discharge circuit

Claims (11)

A display panel including gate lines and data lines and a plurality of electrophoresis cells formed to cross each other;
A data driving circuit for selecting a positive polarity data voltage and a negative polarity data voltage during the image data update period according to the digital data input from the control unit and supplying the positive polarity data voltage and the negative polarity data voltage to the data lines;
A gate driving circuit for supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during the image data update period;
A power supply circuit for generating and outputting the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage, and the negative polarity gate voltage through output terminals in response to the enable signals; And
And a plurality of discharge circuits for forcibly discharging the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage and the negative polarity gate voltage in response to an inverted signal of the enable signals input immediately after the image data update period. / RTI >
The discharge circuit includes:
After discharging the positive gate voltage to the ground in response to an inverted signal of the enable signals, discharging the negative gate voltage to the ground, and then discharging the positive data voltage and the negative data voltage to the ground And discharging the electrophoretic display device. The power supply circuit according to claim 1,
A first DC-DC converter for generating the positive gate voltage in response to a first enable signal;
A second DC-DC converter for generating the negative gate voltage in response to a second enable signal;
A third DC-DC converter for generating the positive polarity data voltage in response to a third enable signal; And
And a fourth DC-DC converter for generating the negative data voltage in response to a fourth enable signal. The plasma display apparatus according to claim 2,
A first discharging circuit for forcibly discharging the output terminal voltage of the first DC-DC converter in response to an inverted signal of the first enable signal;
A second discharging circuit for forcibly discharging the output terminal voltage of the second DC-DC converter in response to an inverted signal of the second enable signal;
A third discharging circuit for forcibly discharging the output terminal voltage of the third DC-DC converter in response to an inverted signal of the third enable signal; And
And a fourth discharging circuit for forcibly discharging the output terminal voltage of the fourth DC-DC converter in response to an inverted signal of the fourth enable signal. The method of claim 3,
Wherein the first discharge circuit to the fourth discharge circuit are packaged together with the power supply circuit and integrated. The method of claim 3,
Wherein the first discharge circuit and the second discharge circuit are formed in the gate drive circuit,
And the third discharge circuit and the fourth discharge circuit are formed in the data driving circuit. The plasma display apparatus according to claim 4 or 5, wherein the first discharge circuit
A pull-down resistor connected to an output terminal of the first DC-DC converter;
An inverter for inverting the inverted signal of the first enable signal; And
And a transistor for conducting a current path between the pull-down resistor and the ground voltage in response to an output signal of the inverter. The plasma display apparatus according to claim 4 or 5,
A pull-down resistor connected to an output terminal of the second DC-DC converter;
An inverter for inverting an inverted signal of the second enable signal; And
And a transistor for conducting a current path between the pull-down resistor and the ground voltage in response to an output signal of the inverter. The plasma display apparatus according to claim 4 or 5,
A pull-down resistor connected to an output terminal of the third DC-DC converter;
An inverter for inverting the inverted signal of the third enable signal; And
And a transistor for conducting a current path between the pull-down resistor and the ground voltage in response to an output signal of the inverter. The plasma display apparatus according to claim 4 or 5,
A pull-down resistor connected to an output terminal of the fourth DC-DC converter;
An inverter for inverting the inverted signal of the fourth enable signal; And
And a transistor for conducting a current path between the pull-down resistor and the ground voltage in response to an output signal of the inverter. A method of driving an electrophoretic display device including a display panel including gate lines and data lines and a plurality of electrophoresis cells formed to cross each other, and driving circuits for driving the display panel,
Supplying a gate pulse swinging between a positive gate voltage and a negative gate voltage to the gate lines during an image data update period;
Selecting and supplying a positive polarity data voltage and a negative polarity data voltage to the data lines according to the digital video data during the image data update period;
And generating and outputting the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage, and the negative polarity gate voltage through output terminals in response to the enable signals generated by the control unit among the driving circuits ; And
Forcibly discharging the positive polarity data voltage, the negative polarity data voltage, the positive polarity gate voltage and the negative polarity gate voltage of the output terminals in response to an inverted signal of the enable signals input immediately after the image data update period / RTI >
The step of discharging includes:
After discharging the positive gate voltage to the ground in response to an inverted signal of the enable signals, discharging the negative gate voltage to the ground, and then discharging the positive data voltage and the negative data voltage to the ground And discharging the electrophoretic display device. 11. The method of claim 10,
The step of forcibly discharging the voltages of the output terminals comprises:
Inverting an inverted signal of the enable signals inputted immediately after the image data update period through an inverter; And
And turning on the current path between the pull-down resistor connected to the output terminals of the DC-DC converter and the base voltage immediately after the image data update period using a transistor which is turned on / off in response to the output signal of the inverter Wherein the electrophoretic display device comprises:

Images