KR20120062376A - Thin film transistor for display and method of forming the same - Google Patents

Abstract

PURPOSE: A thin film transistor for a display and a manufacturing method thereof are provided to repeat an etching process and an ashing process by using a multi-tone mask, thereby successively forming electrode layers. CONSTITUTION: A gate pattern is formed on a substrate(200). A dielectric layer(220), an active layer, a transparent bonding layer, and an electrode metal film are formed on the substrate. Photoresist patterns are formed on the electrode metal film. A source electrode(245) and a drain contact layer are formed on an active layer pattern.

Description

Thin film transistor for display and manufacturing method thereof {Thin Film Transistor for Display and Method of forming the same}

The present invention relates to a display device and a manufacturing method thereof, and more particularly, to a method of manufacturing a thin film transistor of an active display device and a thin film transistor formed through the same.

Recent display apparatuses are largely classified into liquid crystal display devices and organic light emitting display devices.

A liquid crystal display device is a device in which a predetermined image is displayed by liquid crystal whose orientation is changed according to a pixel signal through an active element. In particular, a thin film transistor is used as an active element used in the liquid crystal display device. The thin film transistor is implemented in a pattern on a predetermined region of the substrate, and the channel region is composed of amorphous silicon. In the case of amorphous silicon, there is a disadvantage that the mobility of charge is lower than that of monocrystalline silicon or polycrystalline silicon. However, it has the advantage of being easy to form in a relatively low temperature state, the liquid crystal display device is used as a thin film transistor of the liquid crystal display device because the display is implemented by the application of an electric field rather than the movement of current.

The organic light emitting device has a mechanism for driving a light emitting diode made of organic material with a plurality of transistors. In the light emitting operation, a current is supplied to the light emitting diode, and the brightness of the light emitting diode is determined by the amount of current supplied. Therefore, when the transistor is formed of amorphous silicon, there is a problem that precise control of the amount of current is impossible. To solve this problem, organic electroluminescent devices use polycrystalline silicon.

The two display apparatuses described above all have in common that amorphous silicon or polycrystalline silicon is used as the thin film transistor.

In particular, in the liquid crystal display device, the aperture ratio decreases due to the low light transmittance of the thin film transistor made of amorphous silicon. In addition, the bottom gate type is mostly applied, and a plurality of masks are used for patterning various elements.

Recently, a manufacturing process of a thin film transistor using a 3 or 4 mask, which can reduce the number of processes instead of a 5 mask process, has emerged.

However, in the conventional thin film transistor manufacturing method, opaque amorphous silicon is used as the active layer, opaque metal is also used as the source / drain electrode, and transparent ITO is used as the pixel electrode. Accordingly, there is a problem in that a separate photo mask process for connecting the source / drain electrodes and the pixel electrodes to each other is required.

A first object of the present invention for solving the above problems is a method of manufacturing a thin film transistor that can be used as an active layer of a thin film transistor using a semiconductor oxide of a transparent material, and can simplify the manufacturing process through a three mask process. To provide.

In addition, a second object of the present invention is to provide a thin film transistor formed by achieving the first object.

The present invention for achieving the first object, forming a gate pattern on a substrate; Forming a dielectric film, an active layer composed of a transparent oxide semiconductor, a transparent bonding layer, and a metal film for electrodes on the substrate; Forming a photoresist pattern having a different thickness in the source region, the channel region, and the drain region using a multitone mask on the electrode metal film; Forming a source electrode and a drain junction layer on the active layer pattern formed of the transparent oxide semiconductor through sequential etching and ashing using the photoresist pattern as an etching mask; And exposing the gate pad and the drain junction layer of the gate pattern.

The first object of the present invention, forming a gate pattern on a substrate; Forming a dielectric layer, an active layer composed of a transparent oxide semiconductor, and a transparent bonding layer on the substrate; Forming a photoresist pattern having a different thickness in the source region, the channel region, and the drain region by using a multitone mask on the transparent bonding layer; And forming a source electrode on the active layer pattern composed of the transparent oxide semiconductor through sequential etching and ashing using the photoresist pattern as an etching mask, and forming a drain junction layer through modification of the active layer pattern. It is also achieved through the provision of a method for manufacturing a transistor.

In addition, the present invention for achieving the second object, the gate line formed on the substrate; A dielectric film formed over the gate line; An active layer pattern formed on the dielectric layer and formed on the source region and the channel region and having a transparent oxide semiconductor material; A source electrode formed on the active layer pattern and formed on the source region; And a drain electrode formed on the drain region and the pixel region, wherein a part of the active layer pattern is modified with a conductive material through a plasma process.

According to the present invention, the active layer is composed of a transparent semiconductor oxide. In addition, the manufacturing process can be simplified by using the three mask process. In particular, the electrode layer may be sequentially formed by repeating an etching and ashing process by introducing a multitone mask, and patterning of an active layer using a transparent semiconductor may be performed.

In addition, there is an advantage that the pixel signal transferred to the transistor can be transferred to the pixel region without the introduction of a separate stacked structure through the reforming operation using the plasma treatment of the transparent semiconductor oxide.

1 to 8 are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor according to a first embodiment of the present invention.
9 to 12 and 14 to 17 are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor according to a second exemplary embodiment of the present invention.
13 is a graph showing a change in resistance with plasma treatment time.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

First embodiment

1 to 8 are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor according to a first embodiment of the present invention.

Each drawing is composed of a plan view for forming a thin film transistor on a substrate and a cross-sectional view cut in the A-A 'direction to the H-H' direction. This configuration is equally applied to all the drawings throughout this embodiment.

Referring to FIG. 1, a gate pattern is formed on the substrate 100. The gate pattern includes a gate line 110 and a gate pad 115. The gate pad 115 is provided to supply a voltage to the gate line 110 and is integrally connected to the gate line 110. In addition, the gate pattern may include Cr, Mo, Al, or Cu as a conductive material on the substrate 100. In addition, the gate pattern may be formed in the form of an alloy of a conductive material. In addition, since the gate pattern may be any conductive material, the gate pattern may be formed of a polycrystalline silicon material.

The gate pattern is formed by patterning using a first mask after forming a metal film. For example, a photoresist may be coated on the metal layer, and a gate pattern may be formed through a photolithography process using a first mask.

Referring to FIG. 2, the dielectric layer 120, the active layer 130, the transparent bonding layer 140, and the electrode metal layer 150 are sequentially formed on the substrate 100 and the gate pattern. Subsequently, a photoresist pattern is formed on the electrode metal film 150.

First, the dielectric film 120 may be Si ₃ N ₄ , SiO _2, or HfO _2. And a material having a predetermined dielectric constant. In addition, the dielectric layer 120 may have a non-stoichiometric composition with an amorphous structure.

The active layer 130 has ZnO, indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), and is preferably a transparent semiconductor layer having a predetermined light transmittance.

Subsequently, the transparent bonding layer 140 is formed on the active layer 130, and any transparent conductive material may be used. Therefore, it may be indium tin oxide (ITO), fluorine doped tin oxide (FTO), or doped ZnO, and graphene or CNT may be used as necessary.

The electrode metal film 150 formed on the transparent bonding layer 140 may include Cr, Mo, Al, or Cu, or an alloy thereof.

Subsequently, a photoresist pattern is formed on the electrode metal film 150. The photoresist pattern is implemented by a second mask that is a multitone mask. For example, the second mask has the lowest first light transmittance in the portion where the first pattern 161 is formed on the source region, and the second mask is formed in the portion where the second pattern 163 on the drain region and the pixel region is formed. A second light transmittance higher than one light transmittance is shown. In addition, the second mask has a third light transmittance higher than the second light transmittance in a portion where the third pattern 165 is formed on the channel region. In portions other than the region, the second mask shows a fourth light transmittance higher than the third light transmittance.

Accordingly, the first pattern 161 on the source region and the pad pattern 162 on the source pad region integrally connected thereto have the largest first thickness, and the second pattern 163 formed on the drain region and the pixel region. ) Has a second thickness less than the first thickness. In addition, the third pattern 165 above the channel region is provided to have a third thickness smaller than the second thickness. In addition, since the pad pattern 162 is integrally formed with the first pattern 161, the pad pattern 162 may be processed in the same manner as the first pattern 161 in a subsequent etching or ashing process.

In addition, the pixel region is defined by the first pattern 161 and the gate line 110 crossing the gate pattern 110.

The second mask may control light transmittance through thickness control of the chromium oxide layer. That is, by increasing the thickness of the chromium oxide film, it is possible to implement a low light transmittance, to form a pattern of various thickness, it can be applied to the photoresist pattern formed on the lower. The photoresist pattern may implement a pattern having a different thickness on the region where the thin film transistor is formed and the pixel region by using the second mask that implements the multitone.

Referring to FIG. 3, an etching process is performed using the first to third patterns 161, 163, and 165 as an etching mask. Through the etching process, the electrode metal film 150, the transparent bonding layer 140, and the active layer 130 in regions other than the first to third patterns 161, 163, and 165 are sequentially removed. The etching process may be performed by wet etching or dry etching. In addition, wet etching and dry etching may be performed in parallel depending on the characteristics of the film to be etched. Therefore, wet etching may be performed to remove a specific film, and dry etching may be performed to remove the film below.

An active layer pattern 131, a transparent bonding layer pattern 141, and an electrode pattern 151 are formed under the first to third patterns 161, 163, and 165 through an etching process. In addition, the dielectric layer 120 is opened in regions other than the first to third patterns 161, 163, and 165.

Subsequently, the first to third patterns 161, 163, and 165 are ashed to remove the third pattern 165 above the channel region. The ashing is O ₂ It can be performed by a plasma. In addition, the thickness of the first pattern 161 and the second pattern 163 is reduced by ashing, and a part of the surface of the electrode pattern 151 on the channel region is removed by removing the third pattern 165. Is exposed.

Referring to FIG. 4, an etching process is performed by using the first pattern 161 and the second pattern 163 of FIG. 3, which are uniformly reduced in thickness, as etch masks. The electrode pattern 151 and the transparent bonding layer pattern 141 on the channel region are removed through an etching process, and the source electrode 153 and the drain electrode are respectively formed by the remaining electrode pattern 151 and the transparent bonding layer pattern 141. 155, source junction layer 143, and drain junction layer 145 are formed. In addition, the channel region of the active layer pattern 131 is exposed. That is, the source electrode 153 and the drain electrode 155 are formed on both sides of the channel region through etching of the electrode pattern 151, and the source junction layer on both sides of the channel region through etching of the transparent bonding layer pattern 141. 143 and the drain junction layer 145 are formed.

The drain electrode 155 and the drain junction layer 145 are formed to cover the drain region and the pixel region of the active layer pattern 131.

Subsequently, an ashing process is performed on the remaining first pattern 161 and the second pattern 163. Through ashing, the first pattern 161 having a relatively high thickness remains with a reduced thickness, and the second pattern 163 having a low thickness is removed. The drain electrode 155 formed on the drain region and the pixel region is exposed through the removal of the second pattern 163.

Referring to FIG. 5, an etching process is performed using the first pattern 161 remaining in FIG. 4 as an etching mask. The drain electrode 155 exposed by the etching process is removed, and the drain junction layer 145 having a lower transparent material is exposed.

In addition, the first pattern 161 remaining through the ashing process is removed. Therefore, the source electrode 153 is exposed in the source region, the channel region is exposed in the active layer pattern 131, and the drain junction layer 145 is exposed in the drain region and the pixel region. In addition, the source pad 156 of the source pad area formed under the pad pattern 162 is exposed. The source pad 156 is integrally provided with the source electrode 153.

Referring to FIG. 6, a passivation film 170 is applied to the entire surface of the structure disclosed in FIG. 5. The passivation film 170 is Si ₃ N ₄ , SiO ₂ or HfO ₂ It is composed of a material having a predetermined dielectric constant such as excellent insulating properties. In addition, the passivation film 170 may have a non-stoichiometric composition with an amorphous structure.

Subsequently, a photoresist is applied as shown in FIG. 7, and a photoresist pattern 180 is formed through conventional photolithography. The passivation layer 170 on the pixel area, the gate pad, and the source pad is exposed by the photoresist pattern. In order to form the photoresist pattern described above, a third mask is used in a photolithography process.

Referring to FIG. 8, an etching process is performed using the photoresist pattern 180 illustrated in FIG. 7 as an etching mask. The lower portion of the passivation film 170 exposed by the etching process is removed. Subsequently, through the etching process, the dielectric layer 130 on the gate pad 115 is removed, and the lower gate pad 115 is exposed. In addition, the drain junction layer 145 of the pixel area is exposed by the etching of the exposed passivation film 170, and the surface of the source pad 156 is exposed.

Through the above-described process, the gate pad 115, the drain junction layer 145, and the source pad 156 of the metal material are exposed. Thereafter, a structure in which a voltage is supplied to the drain gate pad and the source pad is formed through a separate wiring process.

Through the above-described process, the active layer of the thin film transistor may be used as a transparent oxide series, and the thin film transistor may be manufactured using three photo masks. In addition, in order to implement this, selective etching in the source region, the drain region, and the channel region may be performed using a multitone mask.

Second Embodiment

9 to 12 and 14 to 17 are plan views and cross-sectional views illustrating a method of manufacturing a thin film transistor according to a second exemplary embodiment of the present invention.

Each of the figures consists of a plan view and a cross-sectional view cut in the I-I 'direction to the P-P' direction.

In addition, the method and material for forming the gate pattern including the gate line 210 and the gate pad 215 on the substrate 200 are the same as those described with reference to FIG. 1 of the first embodiment. Therefore, the gate pattern forming process is performed using the first mask. This is the same as described in FIG.

Next, referring to FIG. 9, the dielectric layer 220, the active layer 230, and the transparent bonding layer 240 are sequentially formed on the substrate 200 on which the gate pattern is formed.

The dielectric layer 220 may be Si ₃ N ₄ , SiO _2, or HfO _2. And a material having a predetermined dielectric constant. In addition, the dielectric layer 220 may have a non-stoichiometric composition with an amorphous structure.

The active layer 230 has ZnO, indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), and is preferably a transparent semiconductor layer having a predetermined light transmittance.

Subsequently, the transparent bonding layer 240 is formed on the active layer 230, and any transparent conductive material may be used. Therefore, it may be indium tin oxide (ITO), fluorine doped tin oxide (FTO), or doped ZnO, and graphene or CNT may be used as necessary.

Subsequently, a photoresist pattern is formed on the transparent bonding layer 240 formed on the uppermost portion. The photoresist pattern includes a first pattern 261, a second pattern 263, and a third pattern 265. The first pattern 261 is formed across the gate pattern and is formed over the source region of the thin film transistor. In addition, the pixel region is defined through this. That is, the pixel region is defined by the gate pattern and the first pattern 261 crossing over each other.

In addition, the first pattern 261 has a first thickness. In addition, the first pattern 261 is formed integrally with the pad pattern 262. Therefore, a process such as ashing for the first pattern 261 is applied to the pad pattern 262 in the same manner, and the pad pattern 262 maintains the same thickness as the first pattern 261. The second pattern 263 is formed over the drain region and the pixel region of the thin film transistor and has a second thickness smaller than the first thickness. In addition, the third pattern 265 is formed on the channel region of the thin film transistor, and is disposed between the first pattern 261 and the second pattern 263. In addition, the third pattern 265 has a third thickness smaller than the first thickness and larger than the second thickness. Therefore, the size of the thickness of the photoresist pattern is shown in the order of the first pattern 261, the third pattern 265, and the second pattern 263.

In addition, the transparent bonding layer 240 is opened in a region other than the first to third patterns 261, 263, and 265.

The formation of patterns having different thicknesses described above is realized through the introduction of a second mask, which is a multitone mask. That is, similarly to the description of the first embodiment, the region of the second mask corresponding to the region where the first pattern 261 is formed is provided to have the first light transmittance which is the lowest transmittance. In addition, an area of the second mask corresponding to the second pattern 263 is provided to have a second light transmittance higher than the first light transmittance. In addition, the region of the second mask corresponding to the third pattern 265 is provided to have a third light transmittance higher than the first light transmittance and lower than the second light transmittance. An area of the second mask corresponding to an area other than the first to third patterns 261, 263, and 265 is provided to have a fourth light transmittance that is the highest transmittance.

The photoresist disclosed in FIG. 9 is of positive type. Therefore, as the intensity of the irradiated light increases, the thickness of the photoresist pattern decreases. Of course, the photoresist may be of negative type. When the negative type is applied, the thickness of the photoresist pattern increases as the intensity of the irradiated light increases.

Referring to FIG. 10, an etching process is performed on the exposed transparent bonding layer 240 using the first to third patterns 261, 263, and 265 formed in FIG. 9 as an etching mask. The etching process removes the transparent bonding layer 240 and the active layer 230 other than the transistor region, the pixel region, and the pad pattern, and exposes the lower dielectric layer 220. Through this, the active layer pattern 231 on the transistor region and the pixel region is defined, and the transparent bonding layer pattern 241 on the active layer pattern 231 is defined.

An ashing process is then performed on the remaining first to third patterns 261, 263, and 265. The ashing process is performed such that the second pattern 263 having the smallest thickness can be removed. Thus, the first pattern 261 and the third pattern 265 remain in a reduced thickness. In addition, the transparent bonding layer pattern 241 under the removed second pattern 263 is exposed.

Referring to FIG. 11, an etching process is performed using the first pattern 261 and the third pattern 265 remaining in FIG. 10 as an etching mask. The transparent bonding layer pattern 241 exposed through the etching process is removed. Therefore, the transparent bonding layer pattern 241 on the drain region and the pixel region is removed, and the source bonding layer 243 remains. The source bonding layer 243 is made of the same material as the transparent bonding layer pattern 241 and is an element defined by the residue by removing a part of the transparent bonding layer pattern 241. In addition, the active layer pattern 231 on the drain region and the pixel region is exposed by partially removing the transparent bonding layer pattern 241.

Subsequently, an ashing process is performed on the first pattern 261 and the third pattern 265. The ashing process is performed such that the third pattern 265 having a relatively small thickness can be removed. As a result, the third pattern 265 is removed, and the first pattern 261 remains in a reduced thickness.

Referring to FIG. 12, plasma processing is performed on the active layer pattern 231 exposed on the drain region and the pixel region. Since the active layer pattern 231 has a transparent oxide semiconductor material, the semiconductor material is modified into a conductor through plasma treatment. Preferably hydrogen or argon plasma is used.

For example, an active layer pattern of an IZO material is formed on the silicon substrate through RF sputtering. The thickness of the formed IZO is 17 ± 2 nm. Argon plasma or hydrogen plasma treatment is performed using a PECVD process at an argon / oxygen ratio of 87/13 vol%.

13 is a graph showing a change in resistance with plasma treatment time under the above-described conditions.

Referring to FIG. 13, it can be seen that an active layer pattern having a semiconductor material is modified to a conductor having a low resistance value by plasma treatment.

Referring back to FIG. 12, the active layer pattern 231 of the drain and the pixel region is modified to a conductor through plasma processing. This is called the drain electrode 233. Accordingly, the drain electrode 233 is in a modified state through plasma treatment of a part of the active layer pattern.

Referring to FIG. 14, an etching process using the first pattern 261 disclosed in FIG. 12 as an etching mask is performed. Due to the etching process, the source bonding layer 243 under the first pattern 261 remains as the source electrode 245, and the source bonding layer 243 on the channel region is removed. The channel region of the active layer pattern 231 is opened by removing the source bonding layer 243 on the channel region. In addition, the source pad 246 is exposed by removing the pad pattern integrally connected with the first pattern. Therefore, the source electrode 245 is formed on the source region, the active layer pattern 231 is disposed on the channel region, and the drain electrode 233 modified by the transparent conductor through the plasma treatment is disposed on the drain region and the pixel region. Is formed.

Subsequently, the remaining first pattern 261 is removed through an ashing process. As a result, the source electrode 245 under the first pattern 261 is opened.

Referring to FIG. 15, a passivation film 270 is formed on the entire surface of the structure disclosed in FIG. 14. The passivation film 270 is Si ₃ N ₄ , SiO ₂ or HfO ₂ It is composed of a material having a predetermined dielectric constant such as excellent insulating properties. In addition, the passivation film 270 may have a non-stoichiometric composition with an amorphous structure.

Referring to FIG. 16, a photoresist is coated on the passivation layer 270 and a photoresist pattern 280 is formed using a third mask. The passivation film 270 on the gate pad 215 is exposed by the photoresist pattern 280, and the passivation film 270 on the pixel area is exposed. In addition, the passivation film 270 on the source pad 246 is exposed.

Referring to FIG. 17, an etching process is performed using the photoresist pattern 280 as an etching mask. Sequential etching is performed in the open regions other than the region shielded by the photoresist pattern 280 through the etching process.

Thus, the dielectric layer 210 on the gate pad 215 is removed, and the surface of the gate pad 215 is exposed. In addition, the drain electrode 233 over the pixel area is exposed, and the source pad 246 is exposed.

Through the above process, a thin film transistor using an oxide semiconductor of a transparent material is formed. In addition, in the present embodiment, the drain electrode may be formed through the plasma treatment of the oxide semiconductor, and thus, the process may be simplified and the productivity may be improved. In addition, in the present embodiment, the semiconductor material is modified into a conductor material through plasma treatment without introducing a separate transparent electrode into the pixel region. As a result, contact resistance between the semiconductor active layer and the electrode can be reduced, and the pixel signal can be transmitted without loss to the display.

100, 200: substrate 110, 210: gate line
120, 220: dielectric film 130, 230: active layer
140, 240: transparent bonding layer

Claims (15)

Forming a gate pattern on the substrate;
Forming a dielectric film, an active layer composed of a transparent oxide semiconductor, a transparent bonding layer, and a metal film for electrodes on the substrate;
Forming a photoresist pattern having a different thickness in the source region, the channel region, and the drain region using a multitone mask on the electrode metal film;
Forming a source electrode and a drain junction layer on the active layer pattern formed of the transparent oxide semiconductor through sequential etching and ashing using the photoresist pattern as an etching mask; And
Exposing the gate pad and the drain junction layer of the gate pattern. The method of claim 1, wherein the active layer comprises ZnO, Indium Zinc Oxide (IZO), or Indium Gallium Zinc Oxide (IGZO). The method of claim 1, wherein the transparent bonding layer comprises indium tin oxide (ITO), fluorine doped tin oxide (FTO), doped ZnO, graphene, or CNT. The method of claim 1, wherein the photoresist pattern,
A first pattern formed on the source region and having a first thickness;
A second pattern formed on the drain region and the pixel region, the second pattern having a second thickness smaller than the first thickness; And
And a third pattern formed on the channel region, the third pattern having a third thickness smaller than the second thickness. The method of claim 4, wherein the forming of the source electrode and the drain junction layer comprises etching the remaining first pattern, the second pattern, or the third pattern as a mask and the first to third patterns. Method of manufacturing a thin film transistor, characterized in that carried out by repeating the sequential removal for. The method of claim 4, wherein the forming of the source electrode and the drain junction layer comprises:
Etching the active layer, the transparent bonding layer, and the electrode metal film using the first to third patterns as etch masks to form an active layer pattern, a transparent bonding layer pattern, and an electrode pattern;
Removing the second pattern, etching the electrode pattern to form the source electrode and the drain electrode, and etching the transparent bonding layer pattern to form a source junction layer and the drain junction layer; And
And removing the third pattern and removing the drain electrode to form the drain junction layer. The method of claim 6, wherein the removing of the second pattern is performed through ashing of the first to third patterns, and the removing of the third pattern is performed through ashing of the first pattern and the third pattern. A method of manufacturing a thin film transistor, characterized in that. The method of claim 6, wherein the drain junction layer is formed on the drain region and the pixel region. Forming a gate pattern on the substrate;
Forming a dielectric layer, an active layer composed of a transparent oxide semiconductor, and a transparent bonding layer on the substrate;
Forming a photoresist pattern having a different thickness in the source region, the channel region, and the drain region by using a multitone mask on the transparent bonding layer; And
Forming a source electrode on the active layer pattern composed of the transparent oxide semiconductor through sequential etching and ashing using the photoresist pattern as an etching mask, and forming a drain junction layer by modifying the active layer pattern Manufacturing method. The method of claim 9, wherein the active layer comprises ZnO, Indium Zinc Oxide (IZO), or Indium Gallium Zinc Oxide (IGZO). The method of claim 9, wherein the photoresist pattern,
A first pattern formed on the source region and having a first thickness;
A second pattern formed on the drain region and the pixel region, the second pattern having a second thickness smaller than the first thickness; And
And a third pattern formed on the channel region and having a third thickness smaller than the first thickness and larger than the second thickness. The method of claim 11, wherein the forming of the source electrode and the drain junction layer comprises:
Etching the transparent bonding layer and the active layer using the first to third patterns as an etching mask to form a transparent bonding layer pattern and an active layer pattern;
The transparent bonding layer pattern is etched by removing the second pattern and using the remaining first pattern and the third pattern as an etching mask to form a source bonding layer, and expose the active layer pattern on the drain region and the pixel region. Making a step;
Plasma processing the exposed active layer pattern to modify a semiconductor material into a drain electrode of a conductive material; And
And removing the third pattern and etching the source junction layer using the remaining first pattern as an etch mask to form the source electrode. The method of claim 12, wherein the plasma processing uses argon plasma or hydrogen plasma. A gate line formed on the substrate;
A dielectric film formed over the gate line;
An active layer pattern formed on the dielectric layer and formed on the source region and the channel region and having a transparent oxide semiconductor material;
A source electrode formed on the active layer pattern and formed on the source region; And
And a drain electrode formed on the drain region and the pixel region, wherein a portion of the active layer pattern is modified with a conductive material through a plasma process. The thin film transistor according to claim 14, wherein the plasma treatment uses argon plasma or hydrogen plasma on the active layer pattern having ZnO, indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO).

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