KR20120054511A - Signal pattern and dispersion tolerant statistical reference oscillator - Google Patents

Abstract

PURPOSE: A statistical reference oscillator for being tolerant to a signal pattern and dispersion is provided to obtain a locking frequency regardless of data patterns by minimizing the error of input data. CONSTITUTION: A statistical reference clock generator(100) outputs a reference signal dividing input data into a first division ratio. A divider(400) outputs feedback signals by dividing the frequency of an output signal into a second division ratio. A frequency detector(200) outputs a difference signal according to the difference of a reference signal and the feedback signal. An output signal generator(300) outputs the output signal according to the difference signal. The statistical reference clock generator includes a multiple threadhold slicer(110) and a frequency divider(120).

Description

Signal Pattern and Dispersion Tolerant Statistical Reference Oscillator}

The present invention relates to a statistical reference oscillator having robustness to signal patterns and variances.

Most wired communication systems that include a phase locked circuit (PLL) with a limited operating range require an additional frequency acquisition loop. Phase Frequency Detectors (PFDs) typically used in frequency acquisition loops require an external reference clock, such as a crystal oscillator. This causes the cost and power consumption of the entire system to increase.

Various Clock and Data Recovery (CDR) techniques that do not require a reference base extract data rate directly from the input data. In addition, some techniques use frequency detectors based on finite-state machines (FSMs), while others use frequency locked circuits based on delay-locked loops (DLLs). Loop: FLL), and another technique uses a line coding analyzer.

However, the above technologies are limited to commercialization in the high-speed wired communication industry. This is due to the difficulty of making complex logic blocks that operate at the speed of the input data. Moreover, these logic blocks not only consume excessive power, but also depend on the type of oscillator used or the input data pattern.

In addition, in the case of the conventionally used voltage controlled delay line (VCDL), due to the process, voltage and temperature variation (PVT) variation, it is impossible to provide the same delay in all chips. Therefore, there is a problem that causes incorrect frequency locking.

Therefore, there is a need for a technology that is easy to fabricate and that enables accurate frequency locking while reducing power consumption.

Korean Laid-Open Publication No. 10-2003-0061291 (2003.07.18)

The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a frequency acquisition technique suitable for high speed serial communication at low power. It is an object of the present invention to provide a statistical reference oscillator that can minimize power consumption by reducing the use of devices operating at line rates. An object of the present invention is to provide a statistical reference oscillator capable of providing a reference clock through a frequency divider without an external device such as a crystal oscillator. It is also an object of the present invention to provide a statistical reference oscillator that can reduce absolute jitter. It is also an object of the present invention to provide a statistical reference oscillator capable of minimizing errors in input data in a distributed and noisy environment and obtaining a locking frequency regardless of the data pattern.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

 A statistical reference oscillator according to an embodiment of the present invention includes a statistical reference clock generator for receiving input data and outputting a reference signal obtained by dividing the input data by a first division ratio; A divider for dividing a frequency of the output signal by a second divider to output a feedback signal; A frequency detector configured to output a difference signal according to a difference between the reference signal and the feedback signal; And an output signal generator for outputting the output signal according to the difference signal.

A statistical reference clock generator includes a multi-threshold slicer and a frequency divider, wherein the multi-threshold slicer detects and inputs a signal of the input data to the frequency divider using the multi-threshold, wherein the frequency divider The signal input from the multiple threshold slicer may be divided by the first division ratio.

The apparatus may further include a CID compensation block capable of skipping a non-random signal in the input data.

According to the present invention, it is possible to provide a frequency acquisition technique suitable for high speed serial communication at low power. The present invention can provide a statistical reference oscillator that can minimize power consumption by reducing the use of devices operating at line rates. The statistical reference oscillator of the present invention can provide a reference clock through a frequency divider without an external device such as a crystal oscillator. In addition, the statistical reference oscillator of the present invention can minimize the error of the input data in a distributed and noisy environment and obtain the locking frequency regardless of the data pattern. In addition, the statistical reference oscillator of the present invention can provide an accurate locking frequency even for actual data.

1 illustrates a statistical reference oscillator according to an embodiment of the present invention.
2 shows a probability distribution of edge separation of input data divided by N according to the value of N. FIG.
Figure 3 shows through simulation the power spectral density (PSD) of the divided NRZ signal and the ideal square wave clock signal.
4 illustrates bilinearly converted single sideband phase noise of SRCG according to an embodiment of the present invention.
5 compares the theoretical form of single sideband phase noise of SRCG according to an embodiment of the present invention with simulation results.
Figure 6 shows the analysis results of the single sideband spectrum L (f) simulation of the SRCG according to an embodiment of the present invention.
7 shows phase noise and L (f) of SRCG according to an embodiment of the present invention.
8 illustrates cumulative jitter generation when using SRCG with a conventional phase frequency detector according to an embodiment of the present invention.
9 is a transient simulation result of a PFD based PLL used with SRCG according to an embodiment of the present invention when N = 1024.
10 shows a phaser diagram of a conventional rotational frequency detector.
11 is an S domain block diagram of an FLL according to an embodiment of the present invention.
12 is a board plot of SRCG, FLL, and filtered phase noise in accordance with an embodiment of the present invention.
Figure 13 shows the phase noise and the theoretical curve of the SRCG according to an embodiment of the present invention modified according to the split ratio.
Fig. 14 is a curve showing a conventional rotation frequency detector transfer function, edge probability distribution, and their product.
Fig. 15 is a curve showing the relationship between the frequency offset according to the division ratio N in the conventional rotational frequency detector.
Fig. 16 is a curve showing a frequency detector transfer function and edge probability distribution of a conventional count method.
Figure 17 shows the transfer function of the quantized count frequency detector.
Fig. 18 is a curve showing the relationship between the frequency offset according to the reference value M and the division ratio N in the conventional frequency detector.
Figure 19 shows the final theoretical equation and the phase noise simulation results of the FLL according to the embodiment of the present invention.
Figure 20 shows the relationship between the frequency and BER of the SRCG in a distributed environment.
21A-21D illustrate the structure of a single threshold slicer and multiple threshold slicers and their operation.
Fig. 22 shows the results of simulating the transient response of SRCG at the output of the charge pump.
Figure 23 illustrates a statistical reference oscillator according to another embodiment of the present invention.
24 illustrates an implementation circuit of a CID compensation block according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals as much as possible even if they are shown in different drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

1 illustrates a statistical reference oscillator according to an embodiment of the present invention. The statistical reference oscillator according to the exemplary embodiment of the present invention shown in FIG. 1 receives the input data and outputs a reference signal obtained by dividing the input data by the first division ratio (SRCG (Stochastic Reference Clock Generator) 100). The frequency divider 400 outputs a feedback signal by dividing a frequency of the output signal by a second division ratio, a frequency detector 200 outputting a difference signal according to a difference between a reference signal and a feedback signal, and the difference signal. And an output signal generator 300 for outputting an output signal. The statistical reference oscillator according to the embodiment of the present invention may optionally further include a CID (consecutive Identical Digit) compensation block.

In an embodiment of the present invention, the divider 400, the frequency detector 200, and the output signal generator 300 are added to form a frequency locked loop (FLL).

The statistical reference clock generator 100 (SRCG) according to the embodiment of the present invention may include a multiple threshold slicer 110 and a frequency divider 120. The multiple threshold slicer 110 detects a signal of the input data using the multiple threshold and inputs it to the frequency divider 120. The description thereof will be described later in detail with reference to FIG.

The frequency divider 120 divides the input data by the first division ratio N and generates and outputs a signal such as a clock. The output signal of the frequency divider 120 is referred to as a reference signal. The probability of transition of a random Non-Return-to-Zero (NRZ) signal is 50%. Therefore, when the random data coming into the input is divided through a divider, the divided signal is output as a reference clock having a duty cycle of 50% as the division multiple increases. . This is shown in FIG. Thus, the use of such a multi-phase frequency divider 120 eliminates the need for an external device such as a crystal oscillator for use as a reference clock.

The time interval between adjacent transition edges of random data divided by the frequency divider 120 according to an embodiment of the present invention may be modeled by a negative binomial random process. The time interval may be defined as edge separation.

Negative binomial random processes are represented by the number of attempts repeated until the expected number of successes occur. In an embodiment of the present invention, the number of successes is a specific data transition and the number of attempts is a unit interval (T _unit ) of divided random data.

In a random NRZ signal, the probability of a particular data transition occurring at the edge of the unit interval is 0.5 and the events in which such data transition occurs are independent of each other. If the divider only captures a particular edge (e.g., rising edge), then a specific data transition in N divided data occurs every 2N data transition. In this case, the probability of having a specific edge in 2T _units of the divided random signal is 0.5.

Therefore, if the signal divided by N is analyzed, the average μ and the variance σ ² of the edge separation are as follows.

수학식1

Equation 1

수학식2

Equation 2

이다. 도2는 분할 비율(N)을 1부터 2,048로 2의 배수로 변화시키면서 분할된 신호의 에지 세퍼레이션의 확률분포를 나타낸 것이다. 확률분포는 중심극한정리(Central Limit Theorem)에 의해서 분할 비율이 증가할수록 표준 분포(Normal Distribution)에 가까워진다. The average frequency of the signal divided by N is

to be. Fig. 2 shows the probability distribution of the edge separation of the divided signal while changing the split ratio N from 1 to 2,048 in multiples of two. The probability distribution is closer to the normal distribution as the split ratio increases due to the Central Limit Theorem.

When both the mean and the variance of the edge separation increase linearly to N, the RMS period jitter (J _period ) of the SRCG 100 according to the embodiment of the present invention may be defined as follows.

수학식3

Equation 3

, J _period as can be seen from the equation (3) is inversely proportional to N ^1/2. In other words, the output spectrum of the divided NRZ signal approaches the spectrum of the clock signal as the division ratio increases. Figure 3 shows through simulation the power spectral density (PSD) of the divided NRZ signal and the ideal square wave clock signal. It can be seen that the PSD of the NRZ signal divided by N = 1024 is similar to the PSD of the clock signal near the fundamental frequency. From this, it can be seen that when the division ratio is 1024 (N = 1024), the divided random signal can function substantially as a reference clock.

The average, variance, and period jitter values of the divided data are shown in Table 1 below.

N 32 64 128 256 512 1024 Mean (UI) 128 256 512 1024 2048 4096 Var. (UI) 128 256 512 1024 2048 4096 Jitter (UI _rms ) 0.088 0.0625 0.0442 0.0315 0.0221 0.0156

의 라디안 표현식은 아래와 같다. Absolute jitter, defined as the maximum phase deviation from the ideal clock edge, is expressed as phase noise L (f) in the frequency domain. Phase jitter is defined as the time difference between the ideal and actual periods. phase jitter in the k period

The radian expression of is

수학식4

Equation 4

는 신호의 주기를 나타낸다. 총 출력 지터는 아래와 같다. here

Denotes the period of the signal. The total output jitter is shown below.

수학식5

Equation 5

는 위상 지터

의 전력스펙트럼밀도(PSD)이다.here

Phase jitter

Is the power spectral density (PSD).

이다. 피리어드 지터는 아래와 같이 표현된다.The cycle of SRCG

to be. Period jitter is expressed as

수학식6

Equation 6

는 k번째 주기의 제로 교차점 시간이고,

는 클록 주기이다. 피리어드 지터 시퀀스는 절대지터 시퀀스의 1차 미분에 해당하고, 이것은 Z-도메인에서

으로 모델링 할 수 있다. 따라서 절대 위상 지터의 전력스펙트럼 밀도 함수

는 피리어드 지터의 전력스펙트럼밀도함수

와 아래와 같은 관계를 가진다. here

Is the zero crossing time of the kth cycle,

Is the clock period. The period jitter sequence corresponds to the first derivative of the absolute jitter sequence, which is the Z-domain

Can be modeled with Therefore, power spectrum density function of absolute phase jitter

Is the power spectrum density function of the period jitter.

And have the following relationship.

수학식7

Equation 7

는 수학식2의

와 같고,

와 아래와 같은 관계를 가진다.Dispersion of Periodic Jitter

Is the equation

Is the same as

And have the following relationship.

수학식8

Equation 8

는 상수값으로 아래와 같다.Since the jitter of SRCG is an independent white process, the power spectrum density function of the jitter

Is a constant value:

수학식9

Equation 9

The power spectrum density of the absolute phase is expressed by Equation 7 as follows.

수학식10

Equation 10

Bilinear transformation of D (z) in Equation 7 is as follows.

수학식11

Equation 11

 4 shows bilinearly transformed single side band noise of a divided NRZ signal. The 3-dB corner frequency is given by

수학식 12

Equation 12

지역에서는 분할비율 N이 증가함에 따라 선형적으로 감소한다. 고주파 위상 잡음 바닥은

에 위치해 있고 분할비율과는 무관하다. 도5는 분할비율 N=1024 및 데이터 천이확률 p=0.5일 때, 수학식 10, 11에 대한 싱글-사이드밴드 위상잡음의 이론적인 형태와 시뮬레이션 결과를 나타낸다. 시뮬레이션 결과는 수학식 10과 정확히 일치하고 양선형변환에 의한 수학식 11은

지역에서는 적절히 근사화하는 반면 고주파 영역에서는 다소 어긋남을 보여준다. 이는 양선형 변환이 Z도메인에서

에 해당하는 영역을 연속시간도메인에서

로 매핑시켜주기 때문이다. 그러나, 양선형변환을 통해 예상되는 고주파영역의 위상잡음바닥은 수학식10의 최소값과 같고, 실제 위상잡음바닥을 잘 표현해준다. The absolute jitter power spectrum density function (PSD) of the divided NRZ signals is

In regions, the ratio decreases linearly as the split ratio N increases. High frequency phase noise flooring

It is located at and is independent of the split ratio. Fig. 5 shows the theoretical shape of the single-sideband phase noise and the simulation results for the equations 10 and 11 when the split ratio N = 1024 and the data transition probability p = 0.5. The simulation result exactly matches Equation 10, and Equation 11 by bilinear transformation

Appropriate approximation in the region, while somewhat misaligned in the high frequency region. This means that the bilinear transformation in Z domain

In the continuous time domain,

Because it maps to. However, the phase noise floor of the high frequency region predicted through the bilinear transformation is equal to the minimum value of Equation 10, and represents the actual phase noise floor well.

의 PSD 특성 함수식 11을 이용해서 계산할 수 있고 여기서

는 N이 충분히 클 때 가우시안 프로세스로 모델링 할 수 있으므로, 아래와 같이 나타낸다.SRCG output signal

Can be calculated using the PSD characteristic function

Can be modeled as a Gaussian process when N is large enough, so

수학식13

Equation 13

로 주어지는 전력스펙트럼밀도함수이고,

는

의 퓨리에 계수로 아래와 같이 정의된다.Where c is

Is the power spectrum density function given by

Is

The Fourier coefficient of is defined as

수학식14

Equation 14

The normalized form of the single side band power spectrum is shown below.

수학식15

Equation 15

이고, 작은 값의 c와

에 대해서 근사화한 형태는 아래와 같이 나타낸다.here

Where c is a small value

The approximated form is shown below.

수학식16

Equation 16

The line width and fLW of SRCG are as follows.

수학식17

Equation 17

노멀라이즈된 라인 너비는 SRCG의 출력신호에 대한 더 나은 정보를 전달해준다. 노멀라이즈된 라인너비는, 아래와 같이 나타낸다.Since the line width and average period only depend on the parameter N,

The normalized line width conveys better information about the output signal of the SRCG. The normalized line width is shown below.

수학식18

Equation 18

The normalized line width is proportional to 1 / N, and the phase noise of SRCG decreases as N increases.

FIG. 6 shows simulation results when N = 128 for Equation 16. FIG. Simulation results can be obtained through Fast Fourier transform after normalizing and down-converting the signal of SRCG, thus saving time simulation using small N . The division ratio 128 is large enough to model phase noise as a Gaussian process. 7 shows a single sideband PSD of phase noise in Equation 11 and L (f) in Equation 16. It can be seen from FIG. 7 that Equations 11 and 16 correspond to the well-known relations below.

수학식19

Equation 19

이다.Where the frequency range is

to be.

When the split ratio is not high enough in the SRCG according to the embodiment of the present invention, a malfunction may occur when the general phase frequency detector is used together with the SRCG according to the embodiment of the present invention.

8 illustrates cumulative jitter generation when using SRCG according to an embodiment of the present invention with a conventional phase frequency detector. This is outside the closed-loop bandwidth of the PLL even when the oscillation frequency of the voltage controlled oscillator 320 (VCO), which will be described later, and the average frequency of the SRCG exactly match, as shown in FIG. 8. And ultimately due to the accumulation of large period jitter that generates large update pulses. This problem is more prominent in SRCG signals divided at lower rates.

9 is a transient simulation result of a PFD based PLL used with SRCG according to an embodiment of the present invention when N = 1024. As can be seen in Figure 9, the frequency of the VCO continues to fluctuate due to untracked large phase jitter that follows the average frequency of the SRCG but outside the closed loop bandwidth of the PLL.

This problem can be mitigated by using a frequency detector that is not sensitive to accumulated phase jitter. Therefore, as shown in FIG. 1, the frequency detector 200 according to the exemplary embodiment of the present invention is output from the reference signal output from the SRCG 100 and the output signal generator 300, and passes through the divider 400. Detects the frequency difference between one feedback signal.

이고 음수이면 그 반대이다. 주파수 검출부(200)의 출력 FD_out은 아래와 같이 구할 수 있다. The operation principle in the case of using a general rotational frequency detector as the frequency detector 200 can be seen in FIG. When one cycle of the divided VCO clock signal is mapped to the axis of the phasor diagram, the two phasers are in the two close periods of the reference clock signal (the output signal of the SRCG) to the divided VCO clock signal. Means relative phase. The sign and magnitude of the phase difference mean the magnitude of the direction of rotation and the frequency difference. Positive phase difference

Negative and vice versa. The output FD _out of the frequency detector 200 can be obtained as follows.

수학식20

Equation 20

는 k번째 분주된 VCO 클록과 기준 클록(SRCG(100)의 출력 신호)의 위상 차이이다. T_REF와 T_CLK은 각각 기준 클록과 피드백 신호의 한 주기를 의미하고 f_REF와 f_CLK는 각각 기준신호와 피드백 신호의 주파수이다. here,

Is the phase difference between the kth divided VCO clock and the reference clock (output signal of SRCG 100). T _REF and T _CLK represent one period of the reference clock and feedback signals, respectively, and f _REF and f _CLK are the frequencies of the reference and feedback signals, respectively.

The phase domain transfer function of FD using Z-transformation is

수학식21

Equation 21

In order to express the S-domain, the bilinear transformation in Equation 21 is as follows.

수학식22

Equation 22

는 SRCG 출력 신호의 주파수에서 위상 업데이트가 발생하는 동안의 평균 주기이다. here

Is the average period during which phase update occurs at the frequency of the SRCG output signal.

In the statistical reference oscillator according to an embodiment of the present invention, the FLL connected to the SRCG may be designed to reduce jitter and shape the SRCG. 11 is a block diagram of an FLL in accordance with an embodiment of the present invention. The expression of the phase-frequency domain of the FLL is as follows.

수학식23

Equation 23

는 전압제 제어 발진기(VCO : 320)의 이득,

는 차지펌프의 전류, C는 루프필터(loop filter)의 커패시턴스, 그리고 N은 주파수 분주기의 분할 비율이다. 분주율 N이 증가할수록, FLL의 게인은 증가하지만 FLL의 대역폭은 일정하다. 이는 첫번째 폴(pole)이 N값과 관계 없이 다음과 같이 표현되기 때문이다.here

Is the gain of the voltage controlled oscillator (VCO: 320),

Is the current of the charge pump, C is the capacitance of the loop filter, and N is the division ratio of the frequency divider. As the division rate N increases, the gain of the FLL increases but the bandwidth of the FLL is constant. This is because the first pole is expressed as follows regardless of the value of N.

수학식24

Equation 24

The output power spectral density function of the FLL having the output signal of the SRCG as an input is given by

수학식25

Equation 25

Increasing the division ratio N reduces the output phase noise of the SRCG as shown in Equation 10, but the output phase noise of the SRCG filtered by the FLL is independent of N because the gain of the FLL increases in proportion to N. It does not change. The output phase noise of the FLL by SRCG cannot be reduced by adjusting the frequency division ratio N or the second pole frequency of the FLL. Therefore, reducing the closed-loop bandwidth is the only way to reduce the total phase noise. FIG. 12 shows a Bode plot summarizing these conditions, and FIG. 13 shows the result of simulating the total output phase noise for the closed-loop bandwidth of the FLL.

A typical rotational frequency detector (RFD) extracts the frequency difference between the VCO and the reference clock by sampling the reference clock with a multiphase VCO clock. The phase difference of adjacent samples contains frequency information. In general, the transfer characteristics of the RFD are shown in FIG. The typical RFD's operating range is ± 50% and the linear range is ± 25%.

 Fig. 14 superimposes the transmission characteristics of the probability mass function (PMF) and the RFD of the output signal when the random NRZ signal is divided at the split ratio 2. Since the linear section of the RFD covers only a portion of the generated random frequency, the nonlinearity of the RFD causes a frequency offset in the FLL output signal. If the first zero crossing of the RFD's propagation curve coincides with the mean frequency of the probability mass function, an asymmetric frequency distribution outside the linear interval produces a DC component at the output of the RFD, which produces a frequency offset. Therefore, in order to reduce the frequency offset, the division ratio N should be made large enough so that most of the range of the probability mass function should be distributed in the linear section. 15 shows the magnitude of the frequency offset according to the division ratio N through simulation. As can be seen in FIG. 15, the division ratio should be set larger than 40 so that the frequency offset is 100 ppm or less.

The FD implemented using a counter counts the VCO clock signal for one period of the reference clock signal and extracts the frequency difference by the difference from the reference value M. The reference value M is a number counted when the FLL locks to a desired frequency. In this case, since the transfer function is linear in all ranges of frequencies as shown in FIG. 16, there is no frequency offset regardless of the division ratio of the SRCG 100.

However, if M is small, the quantization effect appears as shown in FIG. Since the average transfer function of the quantized frequency detector is below the ideal case, the frequency offset appears in the FLL output signal. 18 is a graph obtained by simulation of the frequency offset according to the reference value M and the division ratio N. FIG. The frequency offset decreases with increasing M and N. M is set above 32 to make the frequency offset less than 100ppm.

In practice, the output of the frequency detector 200 is continuous for a time sample interval T ₀ that holds the update signal. This process can be modeled as a zero-order-hold (ZOH) of T ₀ cycles and the frequency response of the ZOH process appears in the phase noise curve. The frequency domain transfer function of the ZOH process is

수학식26

Equation 26

By multiplying Equations 25 and 26, phase noise can be expressed to show a ZOH effect.

수학식27

Equation 27

Asymptotic expression of Equation 27 is obtained by bilinear transformation of Equation 26 as follows.

수학식28

Equation 28

이다. 도19는 수학식 27과 28의 이론적 분석이 시스템 시뮬레이션과 비교하여 정당함을 말해준다. ZOH에 의한 폴은 분할 비율 N에 반비례 하기 때문에 N을 증가시켜 높은 주파수의 위상 잡음을 감소시킬 수 있다.The location of asymptotic poles by ZOH

to be. 19 shows that the theoretical analysis of Equations 27 and 28 is justified compared to system simulation. Since the poles caused by ZOH are inversely proportional to the split ratio N, it is possible to increase N to reduce high frequency phase noise.

If a CDR has a Signal to Noise Ratio penalty due to channel dispersion, an SRCG that shares the same input as the CDR produces a clock-like signal, but the frequency of this signal may be lower than the frequency of the ideal clock. have. Errors in the CDRs in the presence of variance can cause the SRCG to miss valid data transitions. As a result, data may remain undivided due to distribution. That is, in an environment where dispersion and noise exist, the SRCG may not properly detect input data. This results in frequency locking to unwanted values.

20 illustrates a relationship between a frequency of SRCG and a bit error rate (BER) in a distributed environment. If the CDR has a BER of 10 ^-3 because of the variance, the output of the SRCG can be as low as 1000 ppm than the ideal case. This is because most errors are caused by not detecting high frequency data. If the uncompensated BER is greater than 10 ⁻³ , the frequency offset should be compensated for by taking into account the narrow pull-in range of the phase locked loop.

21A and 21B illustrate the structure and operation of SRCG with a conventional single threshold slicer. In Fig. 21B, examples of the input signal, the detection signal, and the divided signal having dispersion are indicated by reference numerals 1 to 3 in connection with the configuration of Fig. 21A. As can be seen from Fig. 21B, a single threshold slicer (denoted small to full) does not correctly detect a valid data transition, showing that the frequency of the signal divided by the divider is lower than the frequency in the ideal case. have. That is, when the input data signal is deformed by the influence of dispersion and noise, one signal cannot detect all signals without error.

Thus, in an embodiment of the present invention, multiple threshold slicers 110 may be used to detect a signal that is modified due to dispersion and / or noise without error.

21C and 21D illustrate the structure and operation of an SRCG that is robust to dispersion with multiple threshold slicers 110 in accordance with an embodiment of the present invention.

As can be seen in Figure 21D, multiple threshold slicer 110 can detect small data transitions that a single threshold slicer may miss. That is, data transitions not detected by a single threshold slicer among the input data of the distributed environment indicated by the original drawing number 1 of FIG. 21B can be detected when the multi-threshold slicer 110 is used.

In Fig. 21D, examples of detection signals and division signals for input signals having dispersion are indicated by reference numerals 4 to 11 in connection with the configuration of Fig. 21C. As can be seen from Fig. 21D and Fig. 11, an input signal modified by variance and noise can be detected without error through a multiple threshold slicer. Therefore, it can be seen that the frequency of the signal divided by the signal detected through the multi-threshold slicer 110 is the same as the frequency of the ideal case.

In Fig. 21C, a slicer with a low threshold detects a small transition starting at '0' and a slicer with a high threshold detects a transition starting at '1'. Here, the output of each of the multiple threshold slicers may be divided (DIV_2) to lower the operating frequency of subsequent blocks. The transition edge of this divided data can be extracted using, for example, an edge detector. Here, the OR gates collect data transition information from the edge detector. The collected data can be divided after correcting the average frequency.

Multiple threshold slicer 110 according to an embodiment of the present invention may be implemented as shown in FIG. 21C. However, this is merely an example and any configuration that performs the above functions may be included in the scope of the present invention. For example, in Fig. 21C, slicers having three thresholds are used, but it is also possible to use more or fewer threshold slicers. For example, a larger number of threshold slicers can be used for SRCG, which is more robust to dispersion. According to an embodiment of the present invention, an SRCG having multiple threshold slicers only needs to detect one type of data transition, so that it is possible to operate at a data rate.

As shown in FIG. 1, the statistical reference oscillator includes an output signal generator 300 for outputting an output signal according to an up pulse signal or a down pulse signal of the frequency detector 200. The output signal generator 300 may include a charge pump 310 that charges or discharges a charge in response to the up pulse signal or a down pulse signal, and a frequency and a phase are compensated in response to an output signal of the charge pump 310. And a voltage controlled oscillator (VCO) 320 for oscillating the output signal.

The charge pump 310 increases or decreases its output voltage in response to the up pulse signal and the down pulse signal. In addition, the statistical reference oscillator according to the present invention may further include a low pass filter (not shown) for removing noise and high frequency components included in the output voltage of the charge pump 310.

The voltage controlled oscillator 320 outputs a frequency compensated output signal using the output voltage of the charge pump 310. As a result, the voltage controlled oscillator 320 increases the output frequency by using the width of the up pulse signal output from the frequency detector 200 or decreases the output frequency by using the width of the down pulse signal.

As shown in FIG. 1, the statistical reference oscillator divides an output signal generated from the output signal generator 300 by a predetermined division ratio and outputs a feedback signal 400 to output a feedback signal. It may include. In an embodiment of the present invention, the frequency division rate may be set to 4N in relation to the frequency division rate of the frequency divider 120 being N. The feedback signal, which is an output signal of the divider 400, is input to the frequency detector 200.

Fig. 22 shows the results of simulating the transient response of SRCG at the output of the charge pump. The original frequency was set to observe both rising and falling transient simulations. Here, the division ratio N is a simulation result in the case of 1024.

23 illustrates a statistical reference oscillator further comprising a CID compensation block 500 in accordance with an embodiment. Actual data input to the statistical reference oscillator includes a frame header rather than general random NRZ data. The frame header is not random data because it does not contain packet information. Therefore, inaccurate frequency locking may occur when using the value including the multiple divider as the reference signal.

For example, when the data is divided by including consecutive identical bits (CID: consecutive Identical Digits) that may exist in the frame header, the duration of the reference signal is increased and the signal output from the voltage controlled oscillator 320 is It will have a lower locking frequency than the ideal case. Therefore, in order to eliminate such an error, a process of skipping a signal having a greater duration in the frequency divider 120 is required.

This skip process is briefly described below. First, the mean value and the variance of the signal which divided the input data are theoretically calculated. From the calculated average value and the variance, the "studen t-distribution" can be used to calculate how small the duration of the signal should be with 95% or 99% reliability. The duration of the signal can be known by counting how many signals of the VCO / 16 are input during the half period of the divided input data. When the statistical reference oscillator enters a predetermined locking range with the t-test value calculated as described above, the CID compensation block 500 is turned on and an update signal is skipped when an unwanted signal, that is, a CID in the frame header is generated. Will be

An example of a circuit implementing the CID compensation block 500 is shown in FIG. This is merely an example and the CID compensation block may include other circuitry that performs the functions described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. will be. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

100: statistical reference clock generator (SRCG)
110: multiple threshold slicer 120: frequency divider
200: frequency detector 300: output signal generator
310: charge pump 320: voltage controlled oscillator (VCO)
400: dispenser
500: CID Reward Block

Claims (9)

A statistical reference clock generator which receives input data and outputs a reference signal obtained by dividing the input data by a first division ratio;
A divider for dividing a frequency of the output signal by a second divider to output a feedback signal;
A frequency detector configured to output a difference signal according to a difference between the reference signal and the feedback signal; And
Statistical reference oscillator including an output signal generator for outputting the output signal in accordance with the difference signal. The method of claim 1,
The statistical reference clock generator comprises a multiple threshold slicer,
And the multiple threshold slicer detects a signal of the input data using multiple thresholds. The method of claim 2,
The statistical reference clock generator further comprises a frequency divider,
And the frequency divider divides the signal input from the multiple threshold slicer by the first division ratio. 4. The method according to any one of claims 1 to 3,
The difference signal is a statistical reference oscillator, characterized in that the up pulse signal or the down pulse signal according to the difference between the reference signal and the feedback signal. 4. The method according to any one of claims 1 to 3,
And wherein the second frequency divider has a value four times that of the first frequency divider. The method of claim 4, wherein
The output signal generator:
A charge pump for charging or discharging charges according to the uppulse signal or the downpulse signal; And
And a voltage controlled oscillator oscillating a frequency in response to the output signal of the charge pump. The method of claim 5,
Statistical reference oscillator, characterized in that the first division rate is more than 128. 4. The method according to any one of claims 1 to 3,
And a CID compensation block for skipping an unrandom signal in the input data so that it is not input to the frequency detector. The method of claim 8,
The CID compensation block receives the reference signal and the output signal, and determines a non-random signal in the input data using the average value and the variance of the reference signal.

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