KR20130061386A - Phase-frequency decector proving frequency multiplying, phase locked loop comprising the phase-frequency decector, and clock and data recovery circuit comprising the phase-frequency decector - Google Patents

Abstract

PURPOSE: A phase frequency detector supplying a frequency multiplication function, a phase-locked loop and a data recovery circuit including the phase frequency detector are provided to reduce a jitter of an internal clock signal or a jitter of a time-controlled data signal. CONSTITUTION: A phase frequency detector(600) includes a first flip-flop(610), a second flip-flop(620), a third flip-flop(630), an n-th flip-flop(640) and a reset unit(650). The first flip-flop outputs an up-signal being set as a second logic if a specific edge of a first clock signal is inputted. The second flip-flop or the n-th flip-flop is serially connected and outputs a down-signal being set as the second logic if a specific edge of a second clock signal is inputted. The reset unit resets each n flip-flop so that the up-signal or down-signal is to be a first logic if the up-signal or down-signal is the second logic.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop, a phase-locked loop, and a phase-locked loop CIRCUIT COMPRISING THE PHASE-FREQUENCY DECECTOR}

The following embodiments relate to a phase frequency detector.

A phase and frequency recovery circuit is disclosed that includes a phase-frequency detector that provides a frequency-doubling function, a phase-locked loop that includes the phase-frequency detector, and the phase-frequency detector.

In general, when a frequency multiplying function is required in a phase-locked loop (PLL) or a clock and data recovery (CDR) circuit, the PLL or CDR circuit may be a frequency divider divider) to perform frequency multiplication.

However, when the divider is used, the signal is delayed in the signal processing inside the divider. This delay time (i.e., a dividing delay) may degrade the jitter characteristics of the PLL and CDR circuits and may degrade the accuracy of the PLL and CDR circuits. Therefore, a PLL and a CDR circuit that perform frequency multiplication without using a frequency divider are required.

When the dividing function is added to the phase-frequency detector (PFD), the accuracy of the loop of the PLL and the CDR circuit using the PFD can be improved.

Korean Patent Laid-Open No. 10-2008-0016179 (published on February 21, 2008) discloses an apparatus including a phase frequency detector and multiplying a clock. The Korean Patent Laid-Open Publication herewith discloses a configuration in which the input clock is multiplied by N times and the phase and frequency differences of the input clock and the output clock are not accumulated even when the input multiplication ratio of the input clock is increased. In addition, the clock multiplier of the apparatus can eliminate accumulated jitter when the output clock is faster than the input clock.

One embodiment of the present invention can provide a phase frequency detector that provides a frequency drain function.

One embodiment of the present invention may provide a phase locked loop using a frequency-doubled phase frequency detector.

One embodiment of the present invention may provide a clock and data recovery circuit using a frequency-doubled phase frequency detector.

According to one aspect of the present invention, n flip-flops-n comprise at least three integers and a reset portion, wherein a first one of the n flip- Flops to n-th flip-flops of the n flip-flops serially connected to each other, the specific edge of the second clock signal is input to the n-1 input And the reset unit outputs the n-th flip-flop so that the up signal and the down signal are both the first logic, if the up signal and the down signal are both the second logic, A phase frequency detector is provided for resetting each of the first and second output signals.

The reset ports R of each of the n flip-flops may be connected to the output port of the reset unit.

The input port of the first flip-flop and the input port D of the second flip-flop may be coupled to the power supply VDD.

The first clock signal may be input to the clock port CK of the first flip-flop, and the output port Q of the first flip-flop may be coupled to the first input port of the reset unit.

The second clock signal may be input to the clock port CKs of the second flip-flop to the n-th flip-flop, respectively.

The output port Q of the kth flip-flop of the n D-flip-flops may be coupled to the input port D of the k + 1 flip-flop. - k is an integer greater than or equal to 2 and less than or equal to n - 1.

The output port Q of the nth flip-flop may be coupled to a second input port of the reset unit.

Each of the n flip-flops may be a D flip-flop.

The frequency of the second clock signal may be n-1 times the frequency of the first clock signal.

The output port Q of the first flip-flop may output an up signal indicating that the phase of the second clock signal is slower than the phase of the first clock signal, and the output port Q of the nth flip- And output a down signal indicating that the phase of the second clock signal is faster than the phase of the first clock signal.

The phase frequency detector compares a time point at which the first clock signal is sampled by the first flip-flop and a time point at which a signal output from the n-th flip-flop is sampled by the nth flip-flop The value of the up signal and the value of the down signal.

The phase frequency detector detects a frequency multiple of the phase frequency detector by connecting the input port D of one of the third flip-flop to the n < th > flip-flop with the power supply VDD of the one or more flip- frequency multiplying ratio.

According to another aspect of the present invention, there is provided a charge pump circuit including: a charge pump which receives an up signal and a down signal and adjusts a control voltage based on the up signal and the down signal, a voltage outputting a clock signal having a frequency proportional to the control voltage And a control oscillator, wherein the frequency of the clock signal is m times the frequency of the reference clock signal, m is an integer equal to or greater than 2, and a control circuit that receives the reference clock signal and the clock signal, And a frequency-multiplied phase-frequency detector for adjusting and outputting the value of the up-signal and the value of the down-signal so as to be doubled.

The frequency-doubled phase frequency detector may comprise n flip-flops-n being m + 1 and a reset portion.

The first flip-flop of the n flip-flops may output the up signal.

And a second flip-flop to an n-th flip-flop connected in series among the n flip-flops may output the down signal.

The reset unit may reset each of the n flip-flops if the up signal and the down signal are both the second logic.

Wherein when the specific edge of the reference clock signal is input, the value of the up signal can be changed from the first logic to the second logic, and when the specific edge of the clock signal is inputted m times, The value of the up signal and the value of the down signal can both be changed from the first logic to the second logic, and if the value of the up signal and the value of the down signal are both the second logic, .

The charge pump may increase the control voltage if the value of the up signal is the second logic and decrease the control voltage if the value of the down signal is the second logic.

The phase locked loop may further comprise a capacitor providing a control voltage.

The charge pump can increase the control voltage by supplying a current to the capacitor and reduce the control voltage by removing current from the capacitor.

The rising edge of the clock signal may not be delayed compared to the rising edge of the reference clock signal.

According to another aspect of the present invention, there is provided a charge pump circuit including a first charge pump that receives a first up signal and a first down signal and adjusts a control voltage based on the first up signal and the first down signal, And a second charge pump for receiving the second down signal and adjusting the control voltage based on the second up signal and the second down signal, a voltage controlled oscillator for outputting a clock signal having a frequency proportional to the control voltage, - the frequency of the clock signal is m times the frequency of the reference clock signal and m is an integer equal to or greater than 2 so that the frequency of the clock signal is m times the frequency of the reference clock signal A frequency multiple phase frequency detector for adjusting and outputting the value of the first up signal and the value of the first down signal, Adjusted data signal synchronized with the clock signal and adjusting the value of the second up signal and the value of the second down signal based on the phase difference between the clock signal and the data signal A clock and data recovery circuit is provided that includes a phase detector.

The frequency-doubled phase frequency detector may comprise n flip-flops-n being m + 1 and a reset portion.

The first flip-flop of the n flip-flops may output the first up signal.

And the second flip-flop to the nth flip-flop serially connected among the n flip-flops may output the first down signal.

The reset unit may reset each of the n flip-flops if the up signal and the down signal are both the second logic.

The control voltage may be a sum of a first partial control voltage and a second partial control voltage.

The first charge pump may adjust the first partial control voltage.

The second charge pump can regulate the second partial control voltage.

Wherein the frequency doubled phase frequency detector is capable of changing the value of the first up signal from a first logic to a second logic when a specific edge of the reference clock signal is input, And if the value of the up signal and the value of the down signal are both the second logic, the value of the first up signal and the value of the first down signal can be changed from the first logic to the second logic, All the values of the signal can be changed to the first logic.

The first charge pump may increase the control voltage if the value of the first up signal is a second logic and decrease the control voltage if the value of the first down signal is a second logic.

The second charge pump may increase the control voltage if the value of the second up signal is a second logic and decrease the control voltage if the value of the second down signal is a second logic.

The rising edge of the clock signal may not be delayed compared to the rising edge of the reference clock signal.

The phase detector may set the value of the second up signal to a second logic when the data signal transitions between a falling edge and a rising edge of the clock signal, The second logic value of the second down signal may be set to the second logic.

A phase frequency detector is provided that provides a frequency doubling function.

A phase locked loop is provided that uses a frequency-doubled phase frequency detector to reduce the jitter of the internal clock signal.

A clock and data recovery circuit is provided that reduces the jitter of the internal clock signal and the jitter of the time adjusted data signal using a frequency doubled phase frequency detector.

1 is a structural view of a PLL.
2 is a circuit diagram of the PFD.
3 illustrates the phase difference between REF and CLK due to the delay time of the frequency divider.
4 is a circuit diagram of a PFD comparing twofold frequencies according to an embodiment of the present invention.
5 illustrates an operation waveform of a PFD comparing twofold frequencies according to an exemplary embodiment of the present invention.
6 is a circuit diagram of a PFD for comparing m times frequency according to an example of the present invention.
7 is a structural diagram of a PLL using a frequency multiple PFD according to an embodiment of the present invention.
8 is a conceptual diagram illustrating the CDR circuit.
9 is a structural diagram of a CDR circuit using a frequency multiple PFD according to an embodiment of the present invention.
Figure 10 illustrates the replacement of a flip-flop in accordance with an example of the present invention.
FIG. 11 shows the net charge variation of a frequency multiple PFD according to an example of the present invention.
12 shows the net charge variation of the frequency multiple PFD according to the frequency difference.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

In the following, "frequency multiple" means converting the frequency of a particular signal to n times, and can be used in the same sense as "frequency multiplication ".

Some of the following signals (eg, reference clock signal, clock signal, up signal, and down signal) may be digital signals. The digital signal may have a value of a first logic or a second logic. The first logic and the second logic have different logical values. For example, if the first logic represents a logical zero, the second logic represents a logical one. If the first logic indicates logic one, the second logic indicates logic zero.

The expression "signal is output" may mean that the value of the signal is "second logic ". That is, when a signal has a value of "second logic ", the signal can be represented as being output from a specific component, and when the signal has a value of" first logic " Can be expressed as not.

1 is a structural view of a PLL.

The PLL 100 may include a PFD 110, a charge pump (CP) 120, a voltage controlled oscillator (VCO) 130, and a frequency divider 140.

The PLL 100 can match the phase and frequency of the reference clock signal REF input from the outside and the signal VO output from the internal VCO 130 to provide a clean clock signal VO to the internal system of the semiconductor.

A divider 140 may be placed between the VCO 130 and the PFD 110 to generate a signal that is faster than REF. VO is input to the divider 140, and the divider 140 can output the clock signal CLK. VO can be N times faster than CLK. That is, the frequency of VO may be N times the frequency of CLK. A CLK faster than the REF may be input to the PFD by the divider 140.

The PFD 110 receives REF and CLK and can adjust the values of the up signal UP and the down signal DN so that REF and CLK have the same frequency and phase. PFD 110 outputs UP and DN.

CP 120 receives the UP and DN and can adjust the control voltage CV based on UP and DN. For example, CP 120 may increase CV if the value of UP is the second logic, and may decrease CV if the value of DN is the second logic.

It is possible to output a VO having a frequency proportional to the VCO 130 CV. That is, the frequency of the VO can be adjusted by the VCO 130 to be proportional to CV.

2 is a circuit diagram of the PFD.

The PFD 110 may include a first flip-flop 210, a second flip-flop 220 and a reset unit 230. The first flip-flop 210 and the second flip-flop 220 may each be a D flip-flop. The reset unit 230 may be a logical product gate.

PFD 110 may compare the times at which REF and CLK are sampled by both flip-flops, respectively, to determine the value of UP and the value of DN.

According to the circuit shown, the PFD 110 may change the value of the UP from a first logic to a second logic when a particular edge of the REF (e.g., a rising edge) is input and the particular edge of the CLK (e.g., The value of the DN can be changed from the first logic to the second logic. The PFD 110 can change both the value of the UP and the value of the DN to the first logic if both the value of the UP and the value of the DN are the second logic.

3 illustrates the phase difference between REF and CLK due to the delay time of the frequency divider.

As described above with reference to FIG. 1, PLL 100 uses frequency divider 140 to generate VO, which is a faster signal than REF. However, when the divider 140 generates CLK using VO, the generated CLK is delayed relative to VO. Since there is a delay time of this divider 140 itself, it is difficult for REF and CLK to be accurately compared by the PFD 110. [

In embodiments of the present invention to be described below, a PLL and a CDR circuit for generating a frequency faster than a reference frequency without a divider by using the PFD with the dividing function, the PFD described above, are disclosed.

4 is a circuit diagram of a PFD comparing twofold frequencies according to an embodiment of the present invention.

The frequency multiple PFD 400 includes a first flip-flop 410, a second flip-flop 420, a third flip-flop 430 and a reset unit 440. The first flip-flop 410, the second flip-flop 420 and the third flip-flop 430 may each be a D flip-flop. The reset unit 440 may include an AND gate.

The reset ports R of each of the first flip-flop 410, the second flip-flop 420 and the third flip-flop 430 are connected to the output port of the reset unit 440.

The input ports D of each of the first flip-flop 410 and the second flip-flop 420 are connected to the power supply VDD.

The first clock signal is input to the clock port CK of the first flip-flop 410. Here, the first clock signal may be the reference clock signal REF.

The output port Q of the first flip-flop 410 is connected to the first input port of the reset unit 440.

The second clock signal is input to the clock ports CK of the second flip-flop 420 and the third flip-flop 430, respectively. Here, the second clock signal is the clock signal CLK.

The output port Q of the second flip-flop 420 is connected to the input port D of the third flip-flop 430.

The output port Q of the third flip-flop 430 is connected to the second input port of the reset unit 440.

The signal output from the output port Q of the first flip-flop 410 is the up signal UP and the signal output from the output port Q of the third flip-flop 430 is the down signal DN. Also, the signal output from the output port Q of the second flip-flop 420 is the intermediate signal a.

5 illustrates an operation waveform of a PFD comparing twofold frequencies according to an exemplary embodiment of the present invention.

The waveforms of the signals (REF, CLK, a, DN and UP) output by the frequency multiple PFD 400 in FIG. 5 are shown.

When the frequency of the CLK is twice the frequency of the REF, the signal width of the DN indicating the frequency fall and the signal width of the UP indicating the frequency rise become constant.

Here, CLK is a signal output from the VCO of the PLL (which does not use the frequency divider) to be described later with reference to FIG. Therefore, the frequency and phase of the PLL using the PFD 400 are fixed when the frequency of the CLK is twice the frequency of the REF. Thus, by using the frequency multiple PFD 400, a PLL can be implemented that provides a frequency multiple without delay time caused by the divider.

The structure of the frequency divider PFD 400 described above can be modified into a phase frequency detector that compares m times the frequency. That is, the frequency multiplying ratio of the frequency multiple PFD can be adjusted by changing the structure of the frequency multiple PFD 400.

6 is a circuit diagram of a PFD for comparing m times frequency according to an example of the present invention.

The frequency multiple PFD 600 includes n flip-flops and a reset unit 650. Here, n is an integer of 3 or more, and n is m + 1. That is, when the frequency multiple number m is 3, the frequency multiple PFD 600 includes four D-flip-flops.

A first flip-flop 610, a second flip-flop 620, a third flip-flop 630 and an nth flip-flop 640 of n flip-flops are shown. The n flip-flops may each be a D flip-flop. The reset unit 650 may be a logical product gate.

The first flip-flop 610 receives the first clock signal and outputs an up signal which is set to the second logic when a specific edge of the first clock signal is input. Here, a specific edge may mean a rising edge or a falling edge.

The second flip-flop 620 to the nth flip-flop 640 are connected in series. The second flip-flop 620 to the nth flip-flop 640 connected in series receive the second clock signal and are set to the second logic when the specific edge of the second clock signal is input n-1 times Down signal.

The reset unit 650 resets each of the n flip-flops so that the up signal and the down signal are both the first logic if the up signal and the down signal are both the second logic.

The reset ports R of each of the n flip-flops are connected to the output port of the reset unit 650.

The input port of the first flip-flop 610 and the input port D of the second flip-flop 620 of the n flip-flops are connected to the power supply VDD.

The first clock signal is input to the clock port CK of the first flip-flop 610. The first clock signal may be the reference clock signal REF.

The output port Q of the first flip-flop 610 is coupled to the first input port of the reset unit 650.

A second clock signal is input to the clock ports CK of the second flip-flop 620 to the nth flip-flop 640 among the n flip-flops. The second clock signal may be the clock signal CLK.

The output port Q of the kth flip-flop of the n flip-flops is connected to the input port D of the k + 1 flip-flop. Here, k is an integer of 2 or more and n-1 or less. For example, if n is 4, the output port Q of the second flip-flop 620 is coupled to the input port D of the third flip-flop 630. The output port Q of the third flip-flop 630 is connected to the input port D of the fourth flip-flop (i.e., the nth flip-flop 640).

The output port Q of the nth flip-flop may be coupled to the second input port of the reset unit 650. [

The output port Q of the first flip-flop 610 outputs an up signal UP. The UP (or the value of UP is the second logic) may indicate that the phase of the second clock signal is slower than the phase of the first clock signal. That is, the UP (or the value of UP is the second logic) may indicate that the VCO, which will be described later, must perform a faster operation (i.e., should output a second clock signal of a faster frequency) .

The output port Q of the nth flip-flop 640 outputs the down signal DN. The DN (or the value of the DN is the second logic) may indicate that the phase of the second clock signal is faster than the phase of the first clock signal. That is, the DN (or the value of the DN is the second logic) may indicate that the VCO, which will be described later, must perform a slower operation (i.e., output a second clock signal at a slower frequency) .

Each of the n flip-flops may be a D flip-flop. Each of the n flip-flops may be a rising edge trigger flip-flop.

The frequency of the second clock signal may be m times (that is, n - 1 times) the frequency of the first clock signal by the operation of the frequency multiple PFD 600. [

The frequency multiples PFD 600 are set such that the time at which the first clock signal is sampled by the first flip-flop 610 and the time at which the signal output by the n-l flip-flop is sampled by the nth flip- The UP value and the DN value can be determined by comparing the time points.

The frequency multiple PFD 600 connects the input port D of one of the third flip-flop 630 to the nth flip-flop 640 of the one or more flip-flops with the power supply VDD, The number of frequency multiples of the PFD 600 can be adjusted. For example, when n = 4, if the input port D of the third flip-flop 630 is connected to the power supply VDD (instead of the output port Q of the second flip-flop 620), the frequency multiple PFD 600 is set to 2 And can operate as a PFD that compares the multiplied frequency. Therefore, the frequency multiple number m of the frequency multiple PFD 600 can be dynamically adjusted and the second clock signal (i.e., CLK) m times faster than the first clock signal (i.e., REF) ≪ / RTI >

7 is a structural diagram of a PLL using a frequency multiple PFD according to an embodiment of the present invention.

The PLL 700 includes a frequency multiple PFD 600, a CP 720, and a VCO 730.

The CP 720 receives the up signal UP and the down signal DN from the frequency multiple PFD 600 and adjusts the control voltage CV based on UP and DN.

The VCO 730 outputs a clock signal CLK having a frequency proportional to CV. Here, the number of frequency multiples of the frequency multiples PFD 600 is m, and the frequency of CLK is m times the reference clock signal REF. m is an integer of 2 or more. That is, when the frequency of REF is x Hz, the frequency of CLK is mx Hz.

The frequency multiple PFD 600 receives the REF and CLK and outputs the adjusted value of the UP and the value of the DN so that the frequency of the CLK becomes m times the frequency of the REF. REF may be the first clock signal as described above with reference to Fig. CLK may be the second clock signal. UP may be a signal output from the output port Q of the first flip-flop 610. DN may be a signal output from the output port Q of the nth flip-flop 640. [

For example, the frequency multiple PFD 600 may change the value of UP from the first logic to the second logic when a particular edge of the REF is input. In addition, the frequency multiple PFD 600 can change the value of the DN from the first logic to the second logic when the specific edge of the CLK is inputted m times. Here, a specific edge may mean either a rising edge or a falling edge.

The frequency multiple PFD 600 can change both the value of UP and the value of DN to the first logic if both the value of UP and the value of DN are the second logic. Also, when the value of the UP or the value of the DN is changed to the second logic, the value of the changed second logic is maintained for a specific time (e.g., one clock of REF or CLK) Falling edge) occurs. The value of the UP or the value of the DN can then return to the first logic.

CP 720 may increase CV if the value of UP is the second logic and may decrease CV if the value of DN is the second logic. Alternatively, the CP 720 may increase the CV if the value of the UP is the second logic and the value of the DN is the first logic and if the value of the UP is the first logic and if the value of the DN is the second logic, You can afford it.

The PLL 700 or the CP 720 may further include a capacitor (not shown).

One end of the capacitor may be coupled between the output end of the CP 720 and the input end of the VCO 730. The other end of the capacitor can be connected to ground.

CP 720 can increase CV by supplying current to the capacitor, and can reduce CV by removing current from the capacitor.

As discussed above, PLL 700 may not use a divider. Therefore, the phase of REF and CLK can be adjusted by the PLL 700 to be the same. That is, the rising edge of CLK is not delayed compared to the rising edge of REF.

Technical contents according to an embodiment of the present invention described above with reference to FIGS. 1 to 7 may be applied to the present embodiment as it is. Therefore, more detailed description will be omitted below.

8 is a conceptual diagram illustrating the CDR circuit.

The CDR circuit is a circuit used for a wired data link.

When data is transmitted from the transmission system to the reception system, the distorted data can be transmitted to the transmission system due to the low pass filter (LPF) characteristic of the data transmission line. The CDR circuit can be used to recover such distorted data.

In Fig. 8, due to the LPF characteristic of the data transmission line, the data signal transmitted to the receiving system is distorted. The distorted data signal is input to a clock recovery circuit 810 and a decision circuit 820. The clock recovery circuit 810 restores the clock signal synchronized to the data based on the distorted data signal. The clock recovery circuit 810 applies the recovered clock signal to the decision circuit 820. The decision circuit 720 restores the data using the distorted data signal and the recovered clock signal.

In general, data transmitted to the receiving system is transmitted in the form of a Non Return to Zero (NRZ) signal. Therefore, theoretically, the data transmitted to the receiving system does not have a particular frequency component. Therefore, it is not easy to apply clock recovery to received data transmitted in the NRZ form.

9 is a structural diagram of a CDR circuit using a frequency multiple PFD according to an embodiment of the present invention.

The CDR circuit 900 includes a frequency multiple PFD 600, a first CP 910, a phase detector (PD) 920, a second CP 930, and a VCO 940.

The CDR circuit 900 may be composed of a PLL part and a data restoration loop. The PLL part may include the top components of FIG. 9 (i.e., PFD 600, first CP 910, and VCO 940). The data recovery loop may include the components at the bottom of FIG. 9 (i.e., PD 920, second CP 930, and VCO 940).

The first CP (910) adjusts the control voltage CV based on the UP and DN _{1 1} receives the first up signal UP ₁ and a first down signal DN _1.

Second CP (930) controls the CV based on the UP and DN _{2 2} receives the second up signal UP _2, and the second down signal DN _2.

CV may be the sum of the first partial control CV ₁ and the second partial control voltage CV ₂ .

The first CP 910 may adjust CV ₁ based on UP ₁ and DN ₁ . The second CP 930 may adjust CV ₂ based on UP ₂ and DN ₂ . For example, the first CP 910 may increase CV ₁ (or CV) if the value of UP ₁ is the second logic, decrease CV ₁ (or CV) if the value of DN ₁ is the second logic, . Or, a first CP (910) is if the value of DN ₁ and the value of the UP ₁ second logical first logical CV ₁ (or, CV) a may increase, and the value of UP ₁ first logic high DN _If the value of ₁ is the second logic, CV ₁ (or CV) can be reduced. The second CP 930 can increase CV ₂ (or CV) if the value of UP ₂ is the second logic and decrease CV ₂ (or CV) if the value of DN ₂ is the second logic have. Alternatively, the second CP (930) is if the value of the UP ₂ second logic high values of DN ₂ first logic CV ₂ (or, CV) a may increase, and the value of UP ₂ first logic high DN _If the value of 2 is the second logic, CV ₂ (or CV) can be reduced.

The PLL 700 or the first CP 910 may further include a first capacitor (not shown). One end of the first capacitor may be connected between the output end of the first CP 910 and the input end of the VCO 940. The other end of the first capacitor may be connected to ground. The first CP 910 may increase CV ₁ by supplying current to the first capacitor and may reduce CV ₁ by subtracting the current from the first capacitor.

The PLL 700 or the second CP 930 may further include a first capacitor (not shown). One end of the second capacitor may be coupled between the output end of the second CP 930 and the input end of the VCO 940. The other end of the second capacitor may be connected to ground. The second CP 930 may increase CV ₂ by supplying current to the second capacitor and may reduce CV ₂ by subtracting the current from the second capacitor.

VCO 940 outputs a clock signal CLK having a frequency proportional to CV. The number of frequency multiples of the frequency multiple PFD 600 is m, and the frequency of CLK is m times the reference clock signal REF. m is an integer of 2 or more. That is, when the frequency of REF is x Hz, the frequency of CLK is mx Hz.

The frequency multiple PFD 600 receives the REF and CLK and adjusts the value of the UP _{1 and} the value of the DN ₁ so that the frequency of the CLK becomes m times the frequency of the REF. REF may be the first clock signal as described above with reference to Fig. CLK may be the second clock signal. UP ₁ may be a signal output from the output port Q of the first flip-flop 610. DN ₁ may be a signal output from output port Q of n-th flip-flop 640.

For example, the frequency multiple PFD 600 may change the value of UP ₁ from the first logic to the second logic when a particular edge of the REF is input. In addition, the frequency multiple PFD 600 can change the value of DN ₁ from the first logic to the second logic when the specific edge of the CLK is input m times. If the value of UP _{1 and} the value of DN ₁ are both the second logic, the frequency multiple PFD 600 can change both the value of UP _{1 and} the value of DN ₁ to the first logic. Here, a specific edge may mean one edge of a rising edge and a falling edge.

In addition, when the value of UP ₁ or the value of DN ₁ is changed to the second logic, the changed second logic value is maintained for a certain time (eg, 1 REF clock or 1 CLK clock), or a specific event (eg, REF Or the falling edge of CLK). Thereafter, the value of UP ₁ or the value of DN ₁ can return to the first logic again.

The PD 920 receives the REF and the data signal DATA and outputs a retimed data signal in which the DATA is synchronized with the CLK. PD 920 adjusts the value of UP _{2 and} the value of DN ₂ based on the phase difference between CLK and DATA.

PD (920) may DATA when the transition between the falling edge and the rising edge of the CLK set the value of the UP ₂ to the second logic. In addition, PD (920) may DATA when the transition between the rising and falling edges of the CLK set the value of the DN ₂ to the second logic. PD (920) has a value and DN ₂ are both a second logic value of the UP _2, can all the values of the value of the UP and DN _{2 2} change to the first logic. Further, when the value of the value or the DN of the UP _{2 2} is changed to a second logic value of the second logic changed is or maintained for a specified time (e.g., one clock of CLK), a particular event (e.g., the CLK or DATA Falling edge) occurs. Then, the value of the UP or DN _{2 2} values may be able to go back to the first logic.

The CDR circuit 900 may not use the frequency divider. Therefore, the phase of REF and CLK can be adjusted by the CDR circuit 900 to be the same. That is, the rising edge of CLK is not delayed compared to the rising edge of REF.

The PLL part can recover the clock signal CLK synchronized with the reference clock signal REF. Based on the CLK, the PD 920 can synchronize DATA to the internal clock CLK to deliver the time adjusted data to the receiving system.

As described above, the frequency multiple PFD 600 can be easily applied to a general form of CDR circuit. When the PLL of the CDR circuit uses a divider, a delay time occurs due to the divider, and the jitter of the CLK may increase. Thus, the CDR circuit can reduce the jitter of CLK by using the frequency multiple PFD 600, and can also reduce the jitter of the time adjusted DATA, which is the output of the CDR circuit, by decreasing the jitter of CLK.

The technical contents according to one embodiment of the present invention described above with reference to Figs. 1 to 8 can be directly applied to this embodiment as well. Therefore, more detailed description will be omitted below.

Figure 10 illustrates the replacement of a flip-flop in accordance with an example of the present invention.

The D flip-flops in the above embodiment may be replaced by other flip-flops.

The D flip-flop 1000 may include an SR flip-flop 1010. Alternatively, the D flip-flop 1000 may be replaced by an SR flip-flop 1010.

In this case, the signal input to the input port D of the D flip-flop 1000 may be input to the input port S of the SR flip-flop 1010. The input port R of the SR flip-flop 1010 may receive an inverse signal of a signal input to the input port D of the D flip-flop 1000.

The signal input to the clock port CK of the D flip-flop 1000 may be input to the clock port CK of the SR flip-flop 1010. [

The output port Q of the D flip-flop 1000 may output a signal output from the output port Q of the SR flip-flop 1010. [ The output port Q 'of the D flip-flop 1000 can output a signal output from the output port Q' of the SR flip-flop 1010.

FIG. 11 shows the net charge variation of a frequency multiple PFD according to an example of the present invention.

In FIG. 11, the results of experiments on the performance of a frequency multiple PFD comparing twofold frequencies are shown. In the graph of Fig. 11, the x-axis represents time. The y-axis represents the net charge.

According to the graph, it can be confirmed that the charge amount of the PLL loop changes when the ratio of the frequency of the reference clock signal REF and the frequency of the VCO clock CLK is 1: 2 and the phases of REF and CLK are different from each other.

12 shows the net charge variation of the frequency multiple PFD according to the frequency difference.

In FIG. 11, the results of experiments on the performance of a frequency multiple PFD comparing twofold frequencies are shown. In the graph of Fig. 11, the x-axis represents the period. The y-axis represents the net charge.

According to the graph, it can be confirmed that the net charge amount changes when the frequency of the reference clock signal REF and the frequency of the VOC clock CLK are different from each other.

Method according to an embodiment of the present invention is implemented in the form of program instructions that can be executed by various computer means may be recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

600: Frequency multiple PFD
700: PLL
720: CP
730: VCO
900: CDR circuit
920 PD

Claims (20)

n flip-flops - n is an integer greater than or equal to 3; And
The reset unit
Lt; / RTI >
The first flip-flop of the n flip-flops outputs an up signal that is set to the second logic when a specific edge of the first clock signal is input,
The second flip-flop to the n-th flip-flop serially connected among the n flip-flops outputs a down signal set to the second logic when the specific edge of the second clock signal is input n-1 times,
And the reset section resets each of the n flip-flops such that the up signal and the down signal are both first logic, if the up signal and the down signal are both the second logic. The method of claim 1,
The reset ports R of each of the n flip-flops are connected to the output port of the reset unit,
The input port D of the first flip-flop and the input port D of the second flip-flop are connected to the power supply VDD,
The first clock signal is input to the clock port CK of the first flip-flop,
An output port Q of the first flip-flop is connected to a first input port of the reset unit,
The second clock signal is input to each of the clock ports CK of the second flip-flop to the nth flip-flop,
The output port Q of the kth flip-flop among the n D-flip-flops is connected to the input port D of the (k + 1) th flip-flop, k is an integer of 2 or more and n -
And an output port Q of the nth flip-flop is connected to a second input port of the reset section. The method of claim 1,
Wherein each of the n flip-flops is a D flip-flop. The method of claim 1,
Wherein the frequency of the second clock signal is n - 1 times the frequency of the first clock signal. The method of claim 1,
The output port Q of the first flip-flop outputs the up signal indicating that the phase of the second clock signal is slower than the phase of the first clock signal, and the output port Q of the nth flip- And outputs the down signal indicating that the phase of the second clock signal is faster than the phase of the first clock signal. The method of claim 5,
The phase frequency detector compares a time point at which the first clock signal is sampled by the first flip-flop and a time point at which a signal output from the n-th flip-flop is sampled by the nth flip-flop And determines the value of the up signal and the value of the down signal. The method of claim 1,
Wherein the phase frequency detector connects the input port D of one of the third flip-flop to the power supply VDD of one of the one of the one or more flip-flops to the frequency multiplier < RTI ID = 0.0 > and adjusts the frequency multiplying ratio. A charge pump which receives the up signal and the down signal and adjusts the control voltage based on the up signal and the down signal;
A voltage controlled oscillator for outputting a clock signal having a frequency proportional to the control voltage, the frequency of the clock signal being m times the frequency of the reference clock signal, and m being an integer of 2 or more; And
A frequency doubling phase frequency detector for receiving the reference clock signal and the clock signal and adjusting the value of the up signal and the value of the down signal so that the frequency of the clock signal is m times the frequency of the reference clock signal,
Lt; / RTI >
Wherein the frequency-doubled phase and frequency detector comprises:
n flip-flops - n is m + 1; And
The reset unit
Lt; / RTI >
A first flip-flop of the n flip-flops outputs the up signal,
A second flip-flop to an n < th > flip-flop serially connected among the n flip-flops outputs the down signal,
Wherein the reset unit resets each of the n flip-flops if the up signal and the down signal are both the second logic, 9. The method of claim 8,
The reset ports R of each of the n flip-flops are connected to the output port of the reset unit,
The input port D of the first flip-flop and the input port D of the second flip-flop are connected to the power supply VDD,
The reference clock signal is input to the clock port CK of the first flip-flop,
An output port Q of the first flip-flop is connected to a first input port of the reset unit,
The clock signal is input to each of the clock ports CK of the second flip-flop to the nth flip-flop,
The output port Q of the kth flip-flop among the n D-flip-flops is connected to the input port D of the (k + 1) th flip-flop, k is an integer of 2 or more and n -
An output port Q of the nth flip-flop is connected to a second input port of the reset unit,
The output port Q of the first flip-flop outputs the up signal,
And the output port Q of the nth flip-flop outputs the down signal. 9. The method of claim 8,
Wherein when the specific edge of the reference clock signal is input, the frequency-doubled phase-frequency detector changes the value of the up signal from the first logic to the second logic, and when the specific edge of the clock signal is inputted m times, And changing the value of the up signal and the value of the down signal to the first logic if the value of the up signal and the value of the down signal are both the second logic Phase locked loop. 9. The method of claim 8,
Wherein the charge pump increases the control voltage if the value of the up signal is a second logic and decreases the control voltage if the value of the down signal is a second logic. 9. The method of claim 8,
A capacitor providing a control voltage
Further comprising:
The charge pump increases the control voltage by supplying current to the capacitor and decreases the control voltage by drawing current from the capacitor. 9. The method of claim 8,
And the rising edge of the clock signal is not delayed relative to the rising edge of the reference clock signal. A first charge pump receiving a first up signal and a first down signal and adjusting a control voltage based on the first up signal and the first down signal;
A second charge pump that receives the second up signal and the second down signal and adjusts the control voltage based on the second up signal and the second down signal;
A voltage controlled oscillator for outputting a clock signal having a frequency proportional to the control voltage, the frequency of the clock signal being m times the frequency of the reference clock signal, and m being an integer of 2 or more;
A frequency division circuit for receiving the reference clock signal and the clock signal and adjusting the value of the first up signal and the value of the first down signal so that the frequency of the clock signal is m times the frequency of the reference clock signal, Frequency detector; And
And outputs the time-adjusted data signal, which is received by the clock signal and the data signal and is synchronized with the clock signal, based on the phase difference between the clock signal and the data signal, A phase detector for adjusting the value of the down signal and outputting
Lt; / RTI >
Wherein the frequency-doubled phase and frequency detector comprises:
n flip-flops - n is m + 1; And
The reset unit
Lt; / RTI >
A first flip-flop of the n flip-flops outputs the first up signal,
A second flip-flop to an n-th flip-flop serially connected among the n flip-flops outputs the first down signal,
And wherein the reset unit resets each of the n flip-flops if the up signal and the down signal are both a second logic. 15. The method of claim 14,
The reset ports R of each of the n flip-flops are connected to the output port of the reset unit,
The input port D of the first flip-flop and the input port D of the second flip-flop among the n flip-flops are connected to the power supply VDD,
The reference clock signal is input to the clock port CK of the first flip-flop,
An output port Q of the first flip-flop is connected to a first input port of the reset unit,
The clock signal is input to each of the clock ports CK of the second flip-flop to the n-th flip-flop among the n flip-flops,
The output port Q of the kth flip-flop among the n D-flip-flops is connected to the input port D of the (k + 1) th flip-flop, k is an integer of 2 or more and n -
An output port Q of the nth flip-flop is connected to a second input port of the reset unit,
The output port Q of the first flip-flop outputs the first up signal,
And the output port Q of the nth flip-flop outputs the first down signal. 15. The method of claim 14,
Wherein the control voltage is a sum of a first partial control voltage and a second partial control voltage,
Wherein the first charge pump regulates the first partial control voltage,
The second charge pump regulates the second partial control voltage. 15. The method of claim 14,
Wherein the frequency-multiplied phase-frequency detector changes the value of the first up signal from a first logic to a second logic when a specific edge of the reference clock signal is input, and when the specific edge of the clock signal is inputted m times The value of the first up signal and the value of the first down signal are both the second logic when the value of the up signal and the value of the down signal are both the second logic, Values to all of the first logic. 15. The method of claim 14,
Wherein the first charge pump increases the control voltage if the value of the first up signal is a second logic and decreases the control voltage if the value of the first down signal is a second logic,
Wherein the second charge pump increases the control voltage when the value of the second up signal is the second logic and decreases the control voltage when the value of the second down signal is the second logic. 15. The method of claim 14,
And the rising edge of the clock signal is not delayed relative to the rising edge of the reference clock signal. 15. The method of claim 14,
Wherein the phase detector sets a value of the second up signal to a second logic when the data signal transitions between a falling edge and a rising edge of the clock signal, And sets the value of the second down signal to a second logic when the data signal transitions.

Images