KR20120051807A - Metal wrap through type solar cell and method for fabricating the same - Google Patents

Abstract

PURPOSE: A metal-wrap-through type solar cell and a manufacturing method thereof are provided to minimize deformation of a substrate by forming an electrode through a low temperature plasticity process. CONSTITUTION: A via hole is formed on once side of a first conductivity type crystalline silicon substrate(301). A via electrode(311) is formed within the via hole. A reflection prevention film(305) and a grid line(312) are formed on the substrate. The via electrode is connected to an n-type electrode(310) arranged on the rear side of the substrate. An intrinsic layer(306), an amorphous semiconductor layer(307), and a transparent conductive oxide film(308) are formed on the rear side of the substrate.

Description

MWT type solar cell and manufacturing method thereof {Metal Wrap Through type solar cell and method for fabricating the same}

The present invention relates to a MWT-type solar cell and a method for manufacturing the same, more specifically, MWT-type solar which can improve the photoelectric conversion efficiency of the solar cell by minimizing the recombination rate of the carrier by applying an amorphous silicon thin film having excellent passivation characteristics A battery and a method of manufacturing the same.

A solar cell is a key element of photovoltaic power generation that converts sunlight directly into electricity, and is basically a diode composed of a p-n junction. In the process of converting sunlight into electricity by solar cells, when solar light is incident on the solar cell, electron-holes (pairs) are generated, and the generated electrons and holes diffuse and electrons are generated by the electric field formed at the pn junction. Is n-layer, the hole is moved to the p-layer to generate photovoltaic power between the pn junction, and when the load or system is connected to both ends of the solar cell, the current flows to produce power.

On the other hand, the structure of the general solar cell has a structure in which the front electrode and the rear electrode is provided on the front and rear, respectively, as the front electrode is provided on the front of the light receiving surface, the light receiving area is reduced by the area of the front electrode. In order to solve the problem that the light receiving area is reduced, a back electrode solar cell has been proposed. The back electrode solar cell is characterized by maximizing the light receiving area of the solar cell by providing a (+) electrode and a (-) electrode on the back of the solar cell.

Such back-electrode type solar cells are classified into interdigitated back contact (IBC), point contact type, emitter wrap through (EWT), metal wrap through (MWT), and the like according to the type. The MWT type solar cell is a structure in which the front of the grid fingers and the bus bars of the bus bar are left in front and the bus bars are moved to the rear. It is connected by penetrating via holes.

Looking at the structure of the MWT type solar cell, as shown in Figure 1, the emitter layer 102 is provided on the entire surface of the substrate 101, the anti-reflection film 103 and the front grid electrode 104 on the entire surface of the substrate 101 ) Is provided. In addition, an n electrode 105 and a p electrode 106 are provided on a rear surface of the substrate 101, and the n electrode 105 and the front grid electrode 104 are provided via via holes 108 penetrating through the substrate 101. ) Is electrically connected.

In addition, the substrate 101 is prevented to prevent electrical shorts in the emitter layer 102 in front of the substrate 101 and p + regions in the back of the substrate 101 and short circuits in the n electrode 105 and the p electrode 106. In each case, an isolation trench 107 is provided on the front and rear surfaces of the backplane.

On the other hand, the n electrode 105 and the p electrode 106 is formed by firing at a high temperature of about 1000 ℃ after the application of the conductive paste, there is a problem that the substrate is physically deformed by firing at a high temperature. In addition, the p-electrode 105 is usually made of aluminum (Al) and the back field (BSF, p ++) is formed by firing, the back field (BSF) basically serves to improve the carrier collection rate, There are a lot of defects (defect) on its own to act as a recombination factor has a disadvantage of lowering the passivation (passivation) characteristics.

The present invention has been made to solve the above problems, by applying an amorphous silicon thin film excellent in passivation characteristics to minimize the recombination rate of the carrier to improve the photoelectric conversion efficiency of the solar cell and its manufacturing MWT The purpose is to provide a method.

MWT solar cell according to the present invention for achieving the above object is a first conductive crystalline silicon substrate having a via hole, a via electrode provided in the via hole, and an intrinsic layer sequentially stacked on the back of the substrate And an amorphous semiconductor layer, a transparent conductive oxide film provided on the amorphous semiconductor layer, a p electrode provided on the transparent conductive oxide film, and an n electrode electrically connected to the via electrode.

An anti-reflection film and a grid line are provided on the entire surface of the substrate, and the grid line is connected to the via electrode.

Method of manufacturing a MWT solar cell according to the present invention comprises the steps of preparing a p-type silicon substrate with a via hole, performing a diffusion process to form an emitter layer on the front of the substrate, an intrinsic layer on the back of the substrate, And sequentially forming an amorphous semiconductor layer and a transparent conductive oxide film and forming an n electrode, a p electrode, a via electrode, and a grid line.

The forming of the n electrode, the p electrode, the via electrode, and the grid line may be performed by applying a conductive paste to a portion where the n electrode is to be formed, a portion where the p electrode is to be formed, and a via hole, and then curing at a low temperature of 50 to 300 ° C. Forming an n electrode, a p electrode and a via electrode, and selectively removing an anti-reflection film at a portion where the grid line is to be formed, and then applying a conductive paste and curing at a low temperature of 50 to 300 ° C. to form a grid line. It is configured to include.

MWT solar cell according to the present invention has the following effects.

As the amorphous silicon thin film is provided on the back side of the substrate, the recombination rate of the carrier can be lowered, thereby improving the photoelectric conversion efficiency of the solar cell. In addition, deformation of the substrate may be minimized as the electrode is formed through low temperature baking.

1 is a configuration diagram of a MWT type solar cell according to the prior art.
2 is a block diagram of an MWT solar cell according to an embodiment of the present invention.
Figure 3 is a flow chart for explaining a manufacturing method of the MWT solar cell according to an embodiment of the present invention.
4A to 4F are cross-sectional views illustrating a method of manufacturing an MWT solar cell according to an embodiment of the present invention.

Hereinafter, an MWT solar cell and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to an MWT solar cell according to an embodiment of the present invention, as shown in FIG. 2, a crystalline silicon substrate 301 of a first conductivity type is provided, and on one side of the substrate 301, a substrate 301 is provided. The via hole 302 penetrates through the via hole, and a via electrode 311 is provided in the via hole 302. In addition, an anti-reflection film 305 and a grid line 312 are provided on the substrate 301. Here, the first conductivity type is p-type or n-type, the second conductivity type described later is the opposite of the first conductivity type, in the following description it is based on the first conductivity type is p-type.

The via electrode 311 is connected to the second conductivity type electrode, that is, the n electrode 310 on the rear surface of the substrate 301. In addition, an intrinsic layer 306, an amorphous semiconductor layer 307 (a-Si: H), and a transparent conductive oxide film 308 are sequentially stacked on the back surface of the substrate 301. Like the amorphous semiconductor layer 307, the intrinsic layer 306 is formed of an amorphous silicon thin film, and the amorphous semiconductor layer 307 is doped with p-type impurity ions. The intrinsic layer 306 and the amorphous semiconductor layer 307 serve to reduce the recombination rate of the carrier, and the transparent conductive oxide film 308 serves to compensate for the low electrical conductivity of the amorphous semiconductor layer 307. . On the other hand, the p-electrode 309 is provided on the transparent conductive oxide film 308.

Next, a method of manufacturing an MWT solar cell according to an embodiment of the present invention will be described.

As shown in FIGS. 3 and 4A, a crystalline silicon substrate 301 of the first conductivity type is prepared, and via holes 302 vertically penetrating the substrate 301 are formed at predetermined intervals (S301). Then, a texturing process is performed such that the unevenness 303 is formed on the surface of the first conductive silicon substrate 301 (S302). The texturing process is for reducing light reflection on the surface of the substrate 301 and may be performed using a dry etching method such as a wet etching method or a reactive ion etching method.

In the state where the texturing process is completed, as shown in FIG. 4B, a diffusion process is performed to form an emitter layer 304 (n +) (S303). Specifically, the silicon substrate 301 is provided in a chamber, and a gas (for example, POCl ₃ ) containing a second conductivity type impurity ion, that is, an n-type impurity ion, is supplied into the chamber to form phosphorus (P) ions. Diffusion is allowed into the substrate 301. Accordingly, the emitter layer 304 is formed at a predetermined depth along the circumference of the substrate 301, and the emitter layer 304 is similarly formed inside the substrate 301 around the via hole 302.

On the other hand, the diffusion process of the n-type impurity ions, in addition to the method using a gaseous gas as described above, the silicon substrate 301 in a solution containing n-type impurity ions, for example, a phosphoric acid (H ₃ PO ₄ ) solution May be used to form the emitter layer 304 by depositing and allowing phosphorus (P) ions to diffuse into the substrate 301 through subsequent heat treatment. In addition, the emitter layer may be selectively formed only on the entire surface of the substrate using a doping paste, an ion implantation, or the like, and the emitter layer may be configured as a selective emitter structure. In addition, when the second conductivity type impurity ions are p-type, the impurity ions forming the emitter layer 304 may be boron (B).

Due to the diffusion process, in the state where the emitter layer 304 is formed on the entire surface of the substrate 301 at a predetermined depth, as shown in FIG. 4C, a predetermined thickness of the lower portion of the substrate 301 is etched and removed to form the substrate 301. The emitter layer 304 on the back side is removed (S304). Then, the anti-reflection film 305 is formed of a material such as silicon nitride film (SiN _x ) on the entire surface of the substrate 301 (S305).

In the state in which the anti-reflection film 305 is formed, an intrinsic layer 306 and an amorphous semiconductor layer (a-Si: H) 307 are sequentially stacked as shown in FIG. 4D (S306). Like the amorphous semiconductor layer 307, the intrinsic layer 306 is formed of an amorphous silicon thin film, and the amorphous semiconductor layer 307 is doped with p-type impurity ions. The intrinsic layer 306 and the amorphous semiconductor layer 307 serve to reduce the recombination rate of the carrier. In this case, when the substrate is n-type, the amorphous semiconductor layer 307 is doped with n-type impurity ions.

Subsequently, a transparent conductive oxide film 308 is stacked on the amorphous semiconductor layer 307. The transparent conductive oxide film 308 serves to complement the low electrical conductivity of the amorphous semiconductor layer 307, and in detail, ZnO, indium tin oxide (ITO), gallium zinc oxide (GZO), and indium gallium zinc oxide (IGZO). ), Indium Gallium Oxide (IGO), Indium Zinc Oxide (IZO), and In2O3. In addition, isolation trenches 313 are formed on the front and rear surfaces of the substrate 301 through laser irradiation.

In this state, silver paste is applied to a portion where the n electrode 310 is to be formed through a screen printing method or the like. In this case, screen printing is performed in the rear direction of the substrate 301, so that the silver paste is also filled in the via hole 302. Subsequently, an aluminum paste is applied to a portion where the p electrode 309 on the rear surface of the substrate 301 is to be formed, and then cured at a low temperature of 50 ° C. to 300 ° C. to form the n electrode 310, the p electrode 309, and the like. The via electrode 311 is completed (S307) (see FIG. 4E).

In the state where the n electrode 310 and the p electrode 309 are formed, the anti-reflection film 305 of the portion where the grid line 312 is to be formed is selectively removed, and then a silver paste is applied and at a low temperature of 50 to 300 ° C. When the cured grid line 312 is formed (S308), the manufacturing method of the MWT solar cell according to the embodiment of the present invention is completed (see FIG. 4F).

Meanwhile, the n electrode 310 and the p electrode may be formed through a plating process. In this case, each of the n electrode 310 and the p electrode has a structure in which the first plating layer, the silicide layer, and the second plating layer are sequentially stacked, and the plating method is electroless-plating or electroplating. Electro-plating can be used.

301: crystalline silicon substrate of the first conductivity type
302: via hole 303: irregularities
304: emitter layer 305: antireflection film
306: intrinsic layer 307: amorphous semiconductor layer
308: transparent conductive oxide film 309: p electrode
310: n electrode 311: via electrode
312 grid line 313 isolation trench

Claims (5)

A first conductivity type crystalline silicon substrate having via holes;
A via electrode provided in the via hole;
An intrinsic layer and an amorphous semiconductor layer sequentially stacked on the back surface of the substrate;
A transparent conductive oxide film provided on the amorphous semiconductor layer;
A p electrode provided on the transparent conductive oxide film; And
MWT-type solar cell comprising the n electrode electrically connected to the via electrode.
The MWT solar cell of claim 1, wherein an anti-reflection film and a grid line are provided on the entire surface of the substrate, and the grid line is connected to the via electrode.
Preparing a p-type silicon substrate having via holes;
Performing a diffusion process to form an emitter layer on the entire surface of the substrate;
Sequentially stacking an intrinsic layer, an amorphous semiconductor layer, and a transparent conductive oxide film on the back surface of the substrate; And
MWT type solar cell comprising the step of forming an n electrode, p electrode, via electrode and grid lines.
The method of claim 3, wherein the forming of the n electrode, the p electrode, the via electrode and the grid line comprises:
applying a conductive paste to a portion where an n electrode is to be formed, a portion where a p electrode is to be formed, and a via hole, and then curing at a low temperature of 50 to 300 ° C. to form an n electrode, a p electrode and a via electrode;
MWT-type solar cell comprising a step of selectively removing the anti-reflection film of the portion where the grid line is to be formed, and then applying a conductive paste and curing at a low temperature of 50 ~ 300 ℃ to form a grid line.
The method of claim 3, wherein each of the n electrode and p electrode,
Forming a first plating layer,
Forming a silicide layer on the first plating layer;
It is formed through the process of forming a second plating layer on the silicide layer,
The first plating layer and the second plating layer is MWT type solar cell, characterized in that formed by electroless plating (electroless-plating) or electro-plating (electro-plating) method.

Images