KR20120037847A - Liquid crystal display device and fabricating method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a manufacturing method thereof are provided to form a pixel electrode on a gate insulating film, thereby minimizing bad short between electrodes of the pixel electrode and a thin film transistor. CONSTITUTION: A protective film(140) comprises a contact hole. The contact hole exposes a portion of a drain electrode and a portion of a pixel electrode. A common electrode(130) is formed on the protective film. The common electrode forms an electric field with the pixel electrode. A second substrate(200) faces a first substrate. A liquid crystal layer is formed between the first and second substrates.

Description

Liquid crystal display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a manufacturing method thereof capable of minimizing short defects between electrodes.

In general, the CRT (CRT) has been used most of the display devices for displaying image information on the screen, which has been inconvenient to use because it is bulky and heavy compared to the display area.

In addition, with the development of the electronics industry, display devices, which have been limitedly used for TV CRTs, have been widely used in personal computers, notebooks, wireless terminals, automobile dashboards, electronic displays, and the like, and transmit large amounts of image information with the development of information and communication technology. As it becomes possible, the importance of next-generation display devices that can process and implement them is increasing.

Such next-generation display devices should be able to realize light and small, large screen, low power consumption and low price, and one of them has recently attracted attention.

The liquid crystal display device (LCD) has superior display resolution than other flat panel display devices, and exhibits a fast response speed as compared to CRTs when a moving image is realized.

One of the liquid crystal display devices which are mainly used is a liquid crystal display device of a twisted nematic (TN) method. The twisted nematic method is a method of driving the liquid crystal cell by installing electrodes on two substrates, arranging the liquid crystal cells to be twisted by 90 °, and then applying a voltage to the electrodes. However, the TN type liquid crystal display device has a disadvantage that the viewing angle is narrow.

Recently, researches on liquid crystal displays employing various new methods have been actively conducted to solve the narrow viewing angle problem. In this scheme, an in-plane switching mode (IPS) or an OCB method is used. (Optically Compensated birefrigence mode).

Among these, the transverse electric field type liquid crystal display device forms two electrodes on the same substrate in order to drive the liquid crystal cell in a horizontal state with respect to the substrate, and applies a voltage between the two electrodes to the substrate. Generates an electric field in the horizontal direction. For this reason, the change in the birefringence of the liquid crystal in the visual direction is small, and the viewing angle characteristic is much superior to the conventional TN type liquid crystal display device.

In the transverse electric field type liquid crystal display, the two electrodes mean a pixel electrode to which a data voltage is applied and a common electrode to which a common voltage is applied. The pixel electrode and the common electrode are formed on a thin film transistor array substrate on which a thin film transistor is formed.

In this case, the pixel electrode may be formed on the same layer as the source and drain electrodes. As the source and drain electrodes and the pixel electrode are formed on the same layer, short defects between the source and drain electrodes and the pixel electrode are prevented. May occur.

In order to prevent such short defects, a constant distance between the source and drain electrodes and the pixel electrode must be secured, which causes a problem of decreasing transmittance.

The present invention minimizes short defects that may occur between the pixel electrode and the thin film transistor by forming the pixel electrode on the gate insulating film, and forms the pixel electrode on an independent layer of electrode tubes of the thin film transistor to gate the pixel electrode. SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can extend the line area to increase the aperture ratio.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a gate line and a gate electrode formed on a first substrate, a first gate insulating film formed on a first substrate on which the gate line and the gate electrode are formed, and an upper portion of the first gate insulating film. A pixel electrode formed on the second electrode; a second gate insulating film formed on the first substrate on which the pixel electrode is formed; a semiconductor layer, a source electrode, a drain electrode, and a data line formed on the second gate insulating film; A protective film formed on the first substrate having the drain electrode formed thereon and including a contact hole exposing a portion of the drain electrode and a portion of the pixel electrode; And a second substrate facing the first substrate and a liquid crystal layer formed between the first and second substrates.

A method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention includes forming a gate line and a gate electrode on a first substrate defining a plurality of pixel regions, and on the first substrate on which the gate line and the gate electrode are formed. Forming a first gate insulating layer, forming a transparent conductive metal material on the first substrate on which the first gate insulating layer is formed, and patterning the pixel electrode through a photo process to form a pixel electrode; and a first forming the pixel electrode Forming a second gate insulating film on the substrate, sequentially forming an amorphous silicon layer and an amorphous silicon layer including impurities on the first substrate on which the second gate insulating film is formed, and forming a conductive metal layer thereon; The active silicon layer and the ohmic contact layer are patterned by patterning the amorphous silicon layer including the amorphous silicon layer and impurities through a photo process. And simultaneously patterning the conductive metal layer to form a data line and a source and a drain electrode crossing the gate line, and forming a passivation layer on the first substrate on which the source and drain electrodes are formed. Forming a contact hole exposing a part of the drain electrode and a part of the pixel electrode, and forming a transparent conductive metal material on the passivation layer including the contact hole and patterning the same through a casing process to form an electric field with the pixel electrode Forming a common electrode; providing a second substrate facing the first substrate; and forming a liquid crystal layer between the first and second substrates.

According to an exemplary embodiment of the present invention, a liquid crystal display and a method of manufacturing the same may minimize short defects between the pixel electrode and the thin film transistor electrode by forming the pixel electrode on a separate layer from the thin film transistor electrodes.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention and a method of manufacturing the same may increase the aperture ratio by extending the pixel electrode to the gate line region.

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a cross-sectional view taken along the line II ′ of FIG. 1.
3A through 3E are plan views sequentially illustrating a manufacturing process of the liquid crystal display of FIG. 1.
4A through 4E are cross-sectional views sequentially illustrating a manufacturing process of the liquid crystal display of FIG. 2.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line I ′ to I ′.

1 and 2, the liquid crystal display according to the exemplary embodiment of the present invention has a plurality of gate lines GL formed in one direction in parallel and a plurality of gate lines GL crossing the gate lines GL and defining pixel regions. A first substrate 100 having a data line DL formed thereon, a second substrate 200 facing the first substrate 100, and a liquid crystal layer formed between the two substrates 100 and 200 (not shown). It includes.

In the pixel area of the liquid crystal display, the gate electrode 102 extending from the gate line GL, the source electrode 104 extending from the data line DL, and the source electrode 104 are spaced apart from each other. And a thin film transistor (TFT) including a semiconductor layer 103 formed between the drain electrode 105 and the source and drain electrodes 104 and 105.

In addition, the pixel region 120 and the common electrode 130 formed on the pixel electrode 120 are electrically connected to the drain electrode 105 and the contact electrode 110 of the thin film transistor TFT in the pixel region. It includes more.

A gate line GL and a gate electrode 102 are formed by depositing and patterning a metal such as Al, Cu, Ta, Ti, Mo, Mo alloy, Al alloy, and the like on the first substrate 100. . Subsequently, a first gate insulating layer 101 is formed on the first substrate 100 on which the gate line GL and the gate electrode 102 are formed.

The pixel electrode 120 made of a transparent conductive metal is formed on the first substrate 100 on which the first gate insulating layer 101 is formed. A second gate insulating layer 106 is formed on the first substrate 100 on which the pixel electrode 120 is formed. The second gate insulating layer 106 is not formed in a portion corresponding to the pixel electrode 120. .

The ohmic contact layer including an active layer and an impurity is sequentially deposited on the first substrate 100 on which the second gate insulating layer 106 is formed, and the data line DL and the source and drain electrodes 104 and 105 are disposed. After depositing and patterning a metal layer constituting the semiconductor layer 103 and the source and drain electrodes 104, 105 are formed.

A protective layer including a contact hole H exposing a part of the drain electrode 105 and a part of the pixel electrode 120 on the first substrate 100 on which the source and drain electrodes 104 and 105 are formed ( 140). In this case, the data line DL and the source and drain electrodes 104 and 105 are formed by depositing a metal layer such as Al, Cu, Ta, Ti, Mo, Mo alloy, or Al alloy on the semiconductor layer 103. It is then formed by patterning.

The common electrode 130 and the contact electrode 110 made of a transparent conductive metal material are formed on the protective layer 140. The contact electrode 110 electrically connects the drain electrode 105 and the pixel electrode 120 through the contact hole H included in the protective layer 140. The contact electrode 110 is formed simultaneously with the common electrode 130 to electrically connect the pixel electrode 120 and the drain electrode 105 formed on different layers.

The common electrode 130 may include a second common electrode 130b overlapping the data line DL, a plurality of third common electrodes 130c overlapping the pixel electrode 120, and the gate line GL. The first common electrode 130a may be parallel to and branched from the plurality of third common electrodes 130c.

The second substrate 200 includes a black matrix 210 that prevents leakage of light, and a color filter layer 220 and a color filter layer formed of red, green, and blue color filter patterns between the black matrix 210. An overcoat layer 230 is formed to planarize the surface of the 220 and to protect the color filter layer 220.

3A through 3E are plan views sequentially illustrating a manufacturing process of the liquid crystal display of FIG. 1.

As shown in FIG. 3A, a metal layer of Al, Cu, Ta, Ti, Mo, Mo alloy, Al alloy, etc. is deposited on the first substrate 100 in FIG. 2 and then gate line is formed through a photo process. GL and a gate electrode 102 extending from the gate line GL are formed.

Next, as shown in FIG. 3B, a first gate insulating film (101 in FIG. 2) made of silicon nitride, silicon oxide, or the like is deposited on the gate electrode 102. After depositing the first gate insulating layer 101, a transparent conductive metal material including indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited, and then a pixel electrode through a photo process, an etching process, and a strip process. 120 is formed.

Subsequently, as shown in FIG. 3C, a second gate insulating layer 106 made of silicon nitride, silicon oxide, or the like is deposited, an active layer material and an ohmic contact layer material are deposited, and Al, Cu, Ta, Ti, Mo After depositing a metal layer such as Mo alloy, Al alloy and Al alloy, the semiconductor layer 103 and the source and drain electrodes 104 and 105 are formed through a photo process, an etching process and a strip process.

Next, as shown in FIG. 3D, a protective layer (140 in FIG. 2) is formed, and a contact hole H exposing a part of the drain electrode 105 is formed through a photo process, an etching process, and a strip process. do.

Subsequently, as illustrated in FIG. 3E, a transparent conductive metal material including indium tin oxide (ITO) or indium zinc oxide (IZO), etc. is deposited on the passivation layer, and then a photo process and an etching and strip process are performed. The common electrode 130 including the first to third common electrodes 130a to 103c is formed. At the same time, a contact electrode 110 is formed to electrically connect the drain electrode 105 and the pixel electrode 120 through the contact hole H.

4A through 4E are cross-sectional views sequentially illustrating a manufacturing process of the liquid crystal display of FIG. 2.

As shown in FIG. 4A, the first substrate 100 is prepared, a metal layer is deposited on the first substrate 100, and then the gate line GL and the gate line GL are formed through a photo process, an etching process, and a strip process. The gate electrode 102 extending from the gate line GL is formed.

Subsequently, a first gate insulating layer 101 made of silicon nitride, silicon oxide, or the like is formed on the gate line GL and the gate electrode 102.

After depositing a transparent conductive metal material including ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) on the first substrate 100 on which the first gate insulating film 101 is formed, the photo process, the etching and the strip ( The pixel electrode 120 is formed through a strip process.

Subsequently, a second gate insulating layer 106 made of silicon nitride, silicon oxide, or the like is deposited on the first substrate 100 on which the pixel electrode 120 is formed. Subsequently, an active layer material made of amorphous silicon and an ohmic contact layer material made of amorphous silicon including impurities are deposited on the second gate insulating layer 106.

Subsequently, on the first substrate 100 on which the second gate insulating layer 106 and the active layer material and the ohmic contact layer material are deposited, Al, Cu, Ta, Ti, Mo, Mo alloy, Al alloy, etc. Deposit a metal layer.

As shown in FIG. 4C, the semiconductor layer 103 and the source and drain electrodes 104 and 105 are formed on the first substrate 100 through a photo process using an diffraction mask and an etching and strip process. do.

In this case, the second gate insulating layer 106 may be formed on the pixel electrode 120, but the pixel electrode 120 may be uniformly spaced between the pixel electrode 120 and the common electrode 130 of FIG. 2. May be removed at a portion corresponding to 120.

That is, the second gate insulating layer 106 is formed under the source and drain electrodes 104 and 105 and under the data line DL except for a portion corresponding to the pixel electrode 120.

Subsequently, on the first substrate 100 on which the semiconductor layer 103 and the source and drain electrodes 104 and 105 are formed, an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics, and photosensitivity may be formed. Deposit. A passivation layer including a contact hole H exposing a part of the drain electrode 105 and a part of the pixel electrode 120 as shown in FIG. 4D through a photo process using a mask and an etching and strip process. 140 is formed.

Subsequently, a transparent conductive metal material including indium tin oxide (ITO), indium zinc oxide (IZO), or the like is entirely deposited on the first substrate 100 on which the passivation layer 140 is formed. Subsequently, as shown in FIG. 4E, the contact electrode 110 and the second and third common electrodes are formed on the contact hole H of the passivation layer 140 through a photo process using an mask and an etching and strip process. The common electrode 130 including the 130b and 130c is formed.

The contact electrode 110 is for electrically connecting the pixel electrode 120 and the drain electrode 105 formed on different layers. The second common electrode 130b overlaps the data line DL and the third common electrode 130c overlaps the pixel electrode 120.

The data voltage is supplied to the pixel electrode 120 through the data line DL and the thin film transistor TFT, and the common voltage Vcom is applied to the common electrode 130. The pixel electrode 120 is formed on the first gate insulating layer 101, and the common electrode 130 is formed on the passivation layer 140 to be perpendicular to the pixel electrode 120 and the common electrode 130. An electric field can be formed.

As the pixel electrode 120 is formed on the first gate insulating layer 101, the gate electrode 102 of the thin film transistor TFT is disposed between the pixel electrode 120 and the first gate insulating layer 101. The source and drain electrodes 104 and 105 are spaced apart from the pixel electrode 120 with the second gate insulating layer 106 interposed therebetween. Similarly, the data line DL is spaced apart from the pixel electrode 120 with the second gate insulating layer 106 interposed therebetween.

Accordingly, a defect in which the pixel electrode 120 is shorted with the electrodes of the thin film transistor TFT may be minimized. Further, since the pixel electrode 120 is spaced apart from the gate line GL and the data line DL through the first and second gate insulating layers 101 and 106, the gate line GL or the data line ( It is possible to extend the design to the DL) area to improve the transmittance of the liquid crystal display.

100: first substrate 101: first gate insulating film
102 gate electrode 103 semiconductor layer
104: source electrode 105: drain electrode
106: second gate insulating film 110: contact electrode
120: pixel electrode 130: common electrode
130a to 103c: first to third common electrodes 140: protective film
200: second substrate 210: black matrix
220: color filter layer 230: overcoat layer

Claims (11)

A gate line and a gate electrode formed on the first substrate;
A first gate insulating layer formed on the first substrate on which the gate line and the gate electrode are formed;
A pixel electrode formed on the first gate insulating film;
A second gate insulating layer formed on the first substrate on which the pixel electrode is formed;
A semiconductor layer, a source electrode, a drain electrode, and a data line formed on the second gate insulating layer;
A passivation layer formed on the first substrate on which the semiconductor layer, the source and the drain electrodes are formed, and including a contact hole exposing a part of the drain electrode and a part of the pixel electrode;
A common electrode formed on the passivation layer to form an electric field together with the pixel electrode;
A second substrate facing the first substrate; And
And a liquid crystal layer formed between the first and second substrates. The method of claim 1,
And the gate electrode is insulated from the pixel electrode with the first gate insulating layer interposed therebetween, and the source and drain electrodes are insulated from the pixel electrode with the second gate insulating layer interposed therebetween. The method according to claim 1,
The second gate insulating film is formed on the first gate insulating film except for a portion corresponding to the pixel electrode. The method according to claim 1,
And the first and second gate insulating layers are made of the same material. The method according to claim 1,
And the first substrate includes a contact electrode formed on the passivation layer to electrically connect the pixel electrode and the drain electrode through the contact hole. The method of claim 5,
The contact electrode is formed of a transparent conductive metal material. Forming a gate line and a gate electrode on a first substrate defining a plurality of pixel regions;
Forming a first gate insulating film on a first substrate on which the gate line and the gate electrode are formed;
Forming a pixel electrode by forming a transparent conductive metal material on the first substrate on which the first gate insulating layer is formed and patterning the same by a photo process;
Forming a second gate insulating film on the first substrate on which the pixel electrode is formed;
Sequentially forming an amorphous silicon layer and an amorphous silicon layer including impurities on the first substrate on which the second gate insulating layer is formed, and forming a conductive metal layer thereon;
Patterning the amorphous silicon layer and the amorphous silicon layer including impurities through a photo process to form an active layer and an ohmic contact layer, and simultaneously patterning the conductive metal layer to form a data line, a source and a drain electrode crossing the gate line. Doing;
Forming a protective layer on the first substrate on which the source and drain electrodes are formed and forming a contact hole exposing a part of the drain electrode and a part of the pixel electrode through a photo process;
Forming a common electrode for forming an electric field together with the pixel electrode by forming a transparent conductive metal material on the passivation layer including the contact hole and patterning the same through a casing process;
Providing a second substrate facing the first substrate; And
Forming a liquid crystal layer between the first and second substrates. The method of claim 7, wherein
The second gate insulating layer is patterned except for a portion corresponding to the pixel electrode. The method of claim 7, wherein
Wherein the gate electrode is insulated from the pixel electrode with the first gate insulating film interposed therebetween, and the source and drain electrodes are insulated from the pixel electrode with the second gate insulating film interposed therebetween. . The method of claim 7, wherein
Forming the common electrode,
And forming a contact electrode electrically connecting the pixel electrode and the drain electrode through the contact hole. The method of claim 7, wherein
And the first and second gate insulating layers are made of the same material.

Images