KR20120023547A - Solid-state imaging element and camera system - Google Patents

Abstract

PURPOSE: A solid-state imaging device and a camera system are provided to arrange a separation part for separating each branch wiring of a node, thereby reducing actual load capacity when a signal of each pixel is read through an amplification circuit. CONSTITUTION: A pixel cell(110A-1) comprises a photoelectric conversion part(111) which is comprised of a photo diode(PD). A transmission transistor(112) transmits an electron which is photo-electrically converted in the photoelectric conversion part to a floating diffusion part(FD). A reset transistor(113) resets electric potential of the floating diffusion part into electric potential of a power line. An amplification transistor(114) is connected to an output signal line(116-1) through a selection transistor(115). A row selection circuit operates a reset control line, a transmission control line, and a selection control line.

Description

Solid-state imaging device and camera system {SOLID-STATE IMAGING ELEMENT AND CAMERA SYSTEM}

The present invention relates to a solid-state imaging device and a camera system represented by a CMOS image sensor.

This solid-state image sensor is comprised by the unit pixel which has a photoelectric conversion part, the charge voltage conversion part which converts the accumulated charge into voltage, and the amplification circuit for reading the voltage of the charge voltage conversion part.

In such a solid-state imaging device, a technique of improving the degree of integration or parallelism by setting the irradiation surface of light to the opposite side (= back side) of the surface on which the transistor is arranged and stacking a plurality of semiconductor layers to read the output signal of the pixel. Is proposed.

This technique is disclosed, for example, in Japanese Patent Laid-Open No. 2006-049361.

1 is a diagram illustrating a basic configuration of a solid-state imaging device disclosed in Japanese Patent Laid-Open No. 2006-049361.

In Fig. 1, the pixel cells 2 are arranged in an array in the first semiconductor layer 1-1 on the light receiving side, and the row scanning circuits 3-1 and 3-2 are arranged on both sides of the array portion. In addition, the pixel driving circuits 4-1 and 4-2 are disposed corresponding to the row arrangement of the pixel cells 2.

2 is a diagram illustrating an example of a pixel of a CMOS image sensor composed of four transistors.

This pixel cell 2 has a photoelectric conversion part (photoelectric conversion element) 21 which consists of photodiode PD, for example.

The pixel cell 2 supplies four transistors of the transfer transistor 22, the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 to this one photoelectric conversion unit 21. It has as an active element.

The photoelectric conversion unit 21 photoelectrically converts incident light into charges (here, electrons) in an amount corresponding to the amount of light.

The transfer transistor 22 is connected between the photoelectric conversion unit 21 and the floating diffusion FD as an output node, and is a transfer signal TRG which is a control signal to its gate (transmission gate) via the transfer control line LSEL. ) Is given.

As a result, the transfer transistor 22 transfers the electrons photoelectrically converted by the photoelectric conversion unit 21 to the floating diffusion FD.

The reset transistor 23 is connected between the power supply line LVDD and the floating diffusion FD, and a reset signal RST, which is a control signal, is given to its gate through the reset control line LRST.

As a result, the reset transistor 23 resets the potential of the floating diffusion FD to the potential of the power supply line LVDD.

The gate of the amplifying transistor 24 is connected to the floating diffusion FD. The amplifying transistor 24 is connected to the output signal line 6 via the selection transistor 25 and constitutes a constant current source and a source follower other than the pixel portion.

The amplifying circuit 24 is formed by the amplifying transistor 24 and the selection transistor 25.

Then, the selection signal SEL, which is a control signal corresponding to the address signal via the selection control line LSEL, is given to the gate of the selection transistor 25, and the selection transistor 25 is turned on.

When the selection transistor 25 is turned on, the amplifying transistor 24 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the output signal line 6.

3 is a diagram illustrating an example of pixel sharing of a CMOS image sensor.

In this configuration, the four pixel cells 2-1 to 2-4 each having the photoelectric conversion elements 21-1 to 21-4 and the transfer transistors 22-1 to 22-4 are floating diffusions FD. The reset transistor 23 and the amplifier circuit 7 are shared.

In the solid-state imaging device, as shown in FIG. 1, the pixel cells of FIG. 2 or a plurality of pixel cells having one amplification circuit 7 in one photoelectric conversion section 21 formed in the first semiconductor layer 1-1. The pixel cell of FIG. 2 having one amplification circuit 7 is applied to the photoelectric conversion section 21.

In the solid-state imaging device of JP-A-2006-049361, a laminated connection terminal (micro bump or through hole via) for propagating a signal to another second semiconductor layer 1-2 stacked on the pixel cell 2 is provided. (8) is connected.

That is, each laminated connection terminal 8 is connected to the amplifying circuit 7 for signal reading.

In the example of FIG. 2 and FIG. 3, the bias transistor (load MOS) 9 which functions as a constant current source of a source follower is formed in the 2nd semiconductor layer 1-2.

In any of the foregoing prior arts, when the size of the unit pixel is smaller than that of the multilayer connection terminal 8, it is difficult to arrange the multilayer connection terminal 8 for each unit pixel.

For this reason, as shown in FIG. 4, it is thought that the output of the amplification circuit of a some pixel cell shares the output signal line connected to the laminated connection terminal.

FIG. 5 is a diagram illustrating an example of main circuits of the solid-state imaging device of FIG. 4.

In this example, the output terminals of the read-amplification circuits 7 of the plurality of pixel cells 2 are connected to the same output signal line 6, and the connection node is connected to the second semiconductor layer (through the multilayer connection terminal 8). 1-2).

The pixel cell 2 has the some photoelectric conversion part PD as shown in FIG. 2, and may share the amplifier circuit 7. As shown in FIG.

As described above, the amplifier circuit 7 includes a selection transistor 25 in addition to the amplifier transistor 24, and is connected to the output signal line 6 through the selection transistor 25.

However, it is also possible to set the voltage of the FD of the unselected pixels low by the reset transistor 23 and to omit the selection transistor 25 by driving the amplifier transistor 24 to be in an OFF state.

By the way, in the structure similar to FIG. 4 and FIG. 5, when one pixel is selected by the row scanning circuit 3 and outputs a signal via the laminated connection terminal 8, it connects to the same laminated connection terminal 8 It is also necessary to drive the parasitic capacitance of the output terminal of the amplifying circuit 7 of the other pixels.

That is, the parasitic capacitance of the source terminal of the amplifying transistor 24, the parasitic capacitance of the source terminal of the selection transistor 25, and the parasitic capacitance of the wiring are added as the load capacitance.

By increasing the parasitic capacitance of the output signal line 6 including the multilayer connection terminal 8, the time until the output signal converges to a desired value after the selection of the pixel becomes long, which impedes an increase in speed.

When a higher speed read operation is required, for example, it is thought to change the bias voltage Vb applied to the gate of the bias transistor 9 to increase the current flowing through the amplifying circuit 7, but is proportional to the increase in current. As a result, the power consumption increases.

The present invention is to provide a solid-state imaging device and a camera system capable of achieving high speed and low power consumption of driving of an output signal line of a pixel in a laminated structure.

According to an embodiment of the present invention, there is provided a solid-state imaging device, the solid-state imaging device comprising: a plurality of stacked semiconductor layers; A plurality of laminated connection portions for electrically connecting the plurality of semiconductor layers; A pixel array unit in which pixel cells having a photoelectric conversion unit and a signal output unit are arranged in a two-dimensional shape; And an output signal line through which a signal by the signal output unit of the pixel cell propagates, wherein the plurality of semiconductor layers include at least a first semiconductor layer and a second semiconductor layer, wherein in the first semiconductor layer, The plurality of pixel cells are arranged in a two-dimensional shape, and a signal output portion of the pixel group formed of the plurality of pixel cells shares an output signal line wired from the laminated connection portion, and the output signal line is a branch branched from the laminated connection portion. In all or part of, characterized in that it has a separation unit capable of separating any branched output signal line.

According to another embodiment of the present invention, a camera system is provided, comprising: a solid-state imaging device; An optical system for forming an image of a subject on the imaging device; And a signal processing circuit for processing an output image signal of the imaging device, wherein the solid-state imaging device includes a plurality of stacked semiconductor layers, a plurality of stacked connection portions for electrically connecting the plurality of semiconductor layers, and photoelectricity. And a pixel array section in which pixel cells having a converter section and a signal output section are arranged in a two-dimensional shape, and an output signal line through which signals from the signal output section of the pixel cell are propagated, wherein the plurality of semiconductor layers include at least a first And a signal output portion of the pixel group formed of the plurality of pixel cells in the first semiconductor layer, wherein the plurality of pixel cells are arranged in a two-dimensional shape and are formed of the plurality of pixel cells. Output signal lines to be wired from each other, and the output signal lines are each branched out at any or all of a portion branched from the laminated connection portion. It characterized in that it has a separation unit capable of separating the output signal line.

According to the present invention, it is possible to speed up the driving of the output signal lines of the pixels in the stacked structure and to reduce the power consumption.

1 is a diagram showing a basic configuration of a solid-state imaging device disclosed in Japanese Patent Laid-Open No. 2006-049361.
2 shows an example of a pixel of a CMOS image sensor composed of four transistors.
3 is a diagram illustrating an example of pixel sharing of a CMOS image sensor.
4 is a diagram illustrating a configuration example of a solid-state imaging device in which outputs of amplification circuits of a plurality of pixel cells share an output signal line connected to a multilayer connection terminal.
FIG. 5 is a diagram illustrating an example of a main part circuit of the solid-state imaging device of FIG. 4. FIG.
6 is a diagram showing an example of the configuration of a CMOS image sensor (solid-state image sensor) according to the embodiment of the present invention.
7 is a diagram illustrating an example of a pixel of a CMOS image sensor composed of four transistors according to the present embodiment.
FIG. 8 is a diagram showing an arrangement example of pixels, stacked connection terminals, and separators in a first semiconductor layer of a CMOS image sensor (solid-state image sensor) according to the first embodiment of the present invention. FIG.
FIG. 9 is a diagram illustrating an example of a main part circuit of the CMOS image sensor (solid-state image sensor) in FIG. 8. FIG.
FIG. 10 is a diagram showing an example of a main part circuit of a CMOS image sensor (solid-state image sensor) according to the second embodiment. FIG.
FIG. 11 is a diagram showing an arrangement example of pixels, stacked connection terminals, and separators in the first semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the third embodiment of the present invention. FIG.
FIG. 12 is a diagram illustrating an example of a main part circuit of the CMOS image sensor (solid-state image sensor) in FIG. 11.
Fig. 13 is a diagram showing an arrangement example of pixels, stacked connection terminals, and separators in the first semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the fourth embodiment of the present invention.
FIG. 14 is a diagram for specifically describing an arrangement example of a pixel, a multilayer connection terminal, and a separation unit according to the fourth embodiment. FIG.
Fig. 15 is a diagram showing an example in which elements are arranged so that a switch and a dummy transistor of a separation part of a branch point maintain periodicity;
Fig. 16 is a diagram showing an example in which elements are arranged such that the switch and the dummy transistor of the separation portion of the branch point maintain periodicity, and the dummy transistor has a predetermined function.
Fig. 17 is a diagram showing a layout example in the case of sharing a laminated connection terminal with 4x4 pixel cells.
Fig. 18 is a diagram showing a laminated structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state image sensor) according to the fifth embodiment of the present invention.
Fig. 19 is a diagram showing a laminated structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state image sensor) according to the sixth embodiment of the present invention.
Fig. 20 is a diagram showing an example of the lamination structure of the first semiconductor layer and the second semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the seventh embodiment of the present invention.
Fig. 21 is a diagram showing a laminated structure example of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the eighth embodiment of the present invention.
Fig. 22 is a diagram showing a laminated structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state image sensor) according to the ninth embodiment of the present invention.
23 is a diagram illustrating an example of a configuration of a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in connection with drawing.

In addition, description is given in the following order.

1. Overall structure example of a solid-state image sensor

2. Basic Concept of Characteristic Configurations Employing Laminated Structures

3. First embodiment

4. Second Embodiment

5. Third embodiment

6. Fourth embodiment

7. Fifth embodiment

8. Sixth embodiment

9. Seventh embodiment

10. Eighth Embodiment

11. Ninth Embodiment

12. Tenth embodiment (Configuration example of camera system)

<1. Example of Overall Configuration of Solid-State Imaging Device>

6 is a diagram illustrating a configuration example of a CMOS image sensor (solid-state image sensor) according to the embodiment of the present invention.

The CMOS image sensor 100 includes a pixel array unit 110, a row selection circuit (Vdec) 120 as a pixel driver, and a read circuit (AFE) 130.

In this embodiment, as an example, the light irradiation surface is formed on the opposite side (= back side) of the surface on which the transistor is disposed, and a plurality of semiconductor layers are stacked to read out the output signal of the pixel.

The characteristic structure corresponding to the laminated structure of this semiconductor layer is explained in full detail later.

In the pixel array unit 110, a plurality of pixel cells 110A are arranged in a two-dimensional shape (matrix shape) of M rows x N columns.

7 is a diagram illustrating an example of a pixel of a CMOS image sensor composed of four transistors according to the present embodiment.

This pixel cell 110A has a photoelectric conversion part (photoelectric conversion element) 111 which consists of photodiode PD, for example.

The pixel cell 110A includes four transistors of the transfer transistor 112, the reset transistor 113, the amplifying transistor 114, and the selection transistor 115 with respect to this one photoelectric conversion unit 111. It has as an active element.

The photoelectric conversion part 111 photoelectrically converts incident light into the electric charge (here, electron) of the quantity corresponding to the light quantity.

The transfer transistor 112 is connected between the photoelectric conversion unit 111 and the floating diffusion FD as an output node, and transfer signal TRG which is a control signal to its gate (transmission gate) via the transfer control line LSEL. ) Is given.

As a result, the transfer transistor 112 transfers the electrons photoelectrically converted by the photoelectric conversion unit 111 to the floating diffusion FD.

The reset transistor 113 is connected between the power supply line LVREF and the floating diffusion FD, and a reset signal RST, which is a control signal, is given to its gate through the reset control line LRST.

As a result, the reset transistor 113 resets the potential of the floating diffusion FD to the potential of the power supply line LVREF.

The gate of the amplifying transistor 114 is connected to the floating diffusion FD. The amplifying transistor 114 is connected to the output signal line 116 via the selection transistor 115 and constitutes a constant current source and a source follower other than the pixel portion.

The amplifying transistor 114 and the selection transistor 115 form an amplifying circuit 117 as a signal output section.

Then, the selection signal SEL, which is a control signal corresponding to the address signal via the selection control line LSEL, is given to the gate of the selection transistor 115, and the selection transistor 115 is turned on.

When the selection transistor 115 is turned on, the amplifying transistor 114 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the output signal line 116.

The voltage output from each pixel via the output signal line 116 is output to the read circuit 130.

These operations are performed simultaneously with respect to each pixel for one row because the gates of the transfer transistor 112, the reset transistor 113, and the selection transistor 115 are connected in units of rows, for example.

As described above, the amplifier circuit 117 includes a selection transistor 115 in addition to the amplifier transistor 114, and is connected to the output signal line 116 via the selection transistor 115.

However, it is also possible to set the voltage of the FD of the unselected pixel low by the reset transistor 113 and to omit the selection transistor 115 by driving the amplifier transistor 114 to be in an OFF state.

The reset control line LRST, the transmission control line LSEL, and the selection control line LSEL, which are wired to the pixel array unit 110, are wired in units of rows of the pixel array as one set.

The reset control line LRST, the transmission control line LSEL, and the selection control line LSEL are driven by the row select circuit 120.

The row selection circuit 120 controls the operation of the pixels arranged in any row in the pixel array unit 110. The row selection circuit 120 functions as a pixel driver for driving control of the pixel through the control lines LSEL, LRST, and LTRG.

The read circuit 130 is predetermined with respect to the signal VSL selected by the drive of the row select circuit 120 or outputted through the output signal line 116 from each pixel cell 110A of the previously selected read row. The processing is performed, for example, temporarily storing the pixel signal after the signal processing.

The read circuit 130 is applicable to a circuit configuration including a sample hold circuit for sample holding a signal output through the output signal line 116.

Alternatively, the readout circuit 130 includes a sample hold circuit, and includes a function of removing pixel-specific fixed pattern noise such as reset noise and threshold deviation of the amplifying transistor 114 by CDS (correlation double sampling) processing. A circuit configuration can be applied.

In addition, the read circuit 130 has an analog-to-digital (AD) conversion function, and a configuration in which the signal level is a digital signal can be applied.

Below, the characteristic structure corresponding to the laminated structure of the semiconductor layer in the CMOS image sensor 100 which concerns on this embodiment is demonstrated in detail.

<2. Basic Concept of Characteristic Configurations Employing Laminated Structures>

First, the basic concept of the characteristic structure which adopts a laminated structure is demonstrated.

In the CMOS image sensor (solid-state imaging device) 100, a plurality of stacked semiconductor layers is basically electrically connected to a plurality of stacked connection terminals (stacked connections).

In the first semiconductor layer, the unit pixel cells 110A including the photoelectric conversion section 111 and the signal output section are two-dimensionally arranged.

The signal output section of the pixel group composed of the plurality of pixel cells shares the output signal line 116 wired from the stacked connection terminals.

And the output signal line 116 has the isolation | separation part which can isolate | separate each arbitrary branched output signal line 116 in all or some part branched from a laminated connection terminal.

More specifically, the output of the amplifying circuit 117 including a plurality of amplifying transistors is connected to the multilayer connection terminal, and the output signal line 116 is part or all of the branch point between the multilayer connection terminal and the amplifier circuit 117. ) Has a separator to separate.

The CMOS image sensor (solid-state image sensor) 100 has a light irradiation surface on the opposite side to the surface where transistors and wirings are arranged, for example.

When the CMOS image sensor 100 propagates an output signal to a stacked first semiconductor layer and another semiconductor layer through a laminated connection terminal, the CMOS image sensor 100 has a high degree of freedom in the arrangement of the laminated connection terminals, and if it is a small number, The transistor may be further disposed in the pixel array without shrinking the converter.

Taking advantage of the above advantages, at a node where the wiring from the stacked connection terminals to each unit pixel is divided, a separation unit such as a switch capable of separating the respective branch wirings can be used to provide a signal for each pixel. Through this, it is possible to reduce the actual load capacity at the time of reading.

In this embodiment, the laminated connection terminal is disposed near the center of the pixel group connected to the laminated connection terminal.

In addition, the multilayer connection terminals are arranged in the vicinity of the center of the pixel group connected to the multilayer connection terminals in a range that satisfies the distance between the stackable connection terminals, thereby evenly dividing the parasitic capacitances of the respective wirings separated by the separation unit. It is possible.

Thereby, it becomes possible to minimize the substantial load capacity at the time of reading the signal of each pixel via the amplifier circuit 117.

In the present embodiment, the branch point is arranged near the center of the pixel group connected after the branch point.

In addition, by arranging the branching point in the vicinity of the center of the pixel group connected after the branching point, it is possible to divide the parasitic capacitance of each wiring separated by the separating section more evenly.

Thereby, it becomes possible to minimize the substantial load capacity at the time of reading the signal of each pixel via the amplifier circuit 117. As shown in FIG.

In the present embodiment, it is characterized in that the separator disposed at the branch point dummyly arranges an element such as the separator in a region where the separator is not arranged so as to have a batch periodicity.

As a result, it is possible to maintain the layout periodicity of the pixels and the circuit, to uniformize the imaging characteristics and the operating characteristics of the transistors, and to avoid deterioration in image quality such as fixed pattern noise.

In this embodiment, the pixel group arranged in two dimensions is connected to the same laminated connection terminal.

By connecting not only the column and row directions but also two-dimensionally arranged pixel groups to the same stacked connection terminals, even if the number of pixels connected to the stacked connection terminals is the same, the distance from the stacked connection terminals to the farthest pixel is minimized.

As a result, in this embodiment, it is possible to equalize the voltage drop of the read voltage due to the parasitic resistance for each pixel.

As a reading circuit of the output signal of a general pixel, the source follower circuit comprised from the amplifying transistor 114 in a pixel, and the constant current source by the bias transistor connected to the output signal line 116 is mentioned as an example.

Since the parasitic capacitance of the output signal line 116 is discharged at a constant current, in particular, since the capacitance component is dominant in the output convergence time, it is possible to proportionally increase the speed or lower the power by separating the capacitance.

On the other hand, since the capacitor discharge, rather than the time constant of the wiring, is dominant, there is no dominant deterioration of the convergence time due to the resistance component, and there is also a feature that there is little overhead due to the addition of a switch as a separation part.

On the other hand, the uniformity is important in the resistance component of the output signal line 116. In the source follower circuit, an input voltage is output to the source terminal of the amplifying transistor 114.

Therefore, the output voltage at the multilayer connection terminal is multiplied by the product of the wiring resistance from the amplifying transistor 114 to the multilayer connection terminal as the output terminal and the constant current generated by the load MOS (bias transistor) as the current source. It takes an offset.

The offset voltage can be easily canceled by a CDS unit such as correlated double sampling, but if it differs greatly from pixel to pixel, a sufficient margin is required for an input voltage range in an analog signal processing circuit such as an analog-to-digital conversion circuit after the output terminal.

In this embodiment, since the switch which is a separating part means is added to each output signal line 116 isolate | separated at a branching point, it is a characteristic that the uniformity of the resistance component of the output signal line 116 is not impaired.

Next, a specific structural example is demonstrated.

<3. First embodiment>

FIG. 8 is a diagram showing an arrangement example of pixels, stacked connection terminals, and separation units in the first semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the first embodiment of the present invention.

9 is a diagram illustrating an example of a main part circuit of the CMOS image sensor (solid-state image sensor) in FIG. 8.

In the CMOS image sensor 100A of the first embodiment, the pixel cells 110A are arranged in an array in the first semiconductor layer 200. Row scanning circuits 121-1 and 121-2 are disposed on both sides of the pixel array unit 110, and the pixel driving circuits 122-1 and 122-2 correspond to the row arrangement of the pixel cells 110A. Is arranged.

In the first embodiment, the amplifier circuit 117 of the pixel cell 110A shares the output signal line 116 in the column direction and is connected to the stacked connection terminals 118.

The separation unit 140 of the output signal line 116 is provided at a position where the output signal line 116 is branched from the stacked connection terminal 118 to the amplifying circuit 117 of each pixel cell.

In the pixel array unit 110 of FIG. 8, pixel cells are arranged in a matrix of 6 × 6.

In this 1st Embodiment, the arrangement position of the laminated connection terminal 118 is arrange | positioned in the pixel group center of the some pixel cell 110A to be connected in the range which meets the minimum distance between manufactureable laminated connection terminals. It is preferable.

In this case, ideally in the pixel array of Fig. 8, in each column CL0 to CL5, the stacked connection terminals 118 are disposed between the formation positions of the pixel cells in the third row and the fourth row, that is, in the center of each column. It is preferable.

When arrangement | positioning in the center is not possible, it is preferable to arrange | position in the vicinity of center in the range which can be arrange | positioned like FIG.

In Fig. 8, in the even columns LC0, LC2, LC4, the stacked connection terminals 118 are disposed between the formation positions of the pixel cells in the fourth row and the fifth row, that is, near the center in the range where they can be arranged.

In the odd-numbered columns CL1, CL3, CL5, the laminated connection terminals 118 are disposed between the formation positions of the pixel cells in the second row and the third row, that is, near the center in the range where they can be arranged.

In the example of FIG. 8 and FIG. 9, the separating part 140 is arrange | positioned so that it may overlap with the laminated connection terminal 118 at intervals in a lamination direction.

In addition, in FIG. 9, for the sake of simplicity, four pixel cells 110A-1 to 110A-4 are included, and the stacked connection terminals 118 and the separating unit 140 are disposed almost in the center of the pixel group. An example is shown.

As shown in FIG. 9, the separating part 140 at the branch point is comprised by the switch 141, and isolate | separates the output signal line 116 into two output signal lines 116-1 and 116-2. .

The output signal line 116-1 is connected to the amplifying circuit 117 of the pixel cells 110A-1 and 110A-2, and the output signal line 116-2 is amplifying the pixel cells 110A-3 and 110A-4. It is connected to the circuit 117.

In the switch 141 constituting the separating unit 140, the terminal a and the terminal b are paired, and the terminal c and the terminal d are paired.

Terminal a is connected to laminated connection terminal 118, and terminal b is connected to one output signal line 116-1.

The terminal c is connected to the multilayer connection terminal 118, and the terminal d is connected to the other output signal line 116-2.

The switch 141 having such a configuration is connected between the terminal a and the terminal b, the non-connected state, and the terminal c and the terminal d by the switching signal SSW by a control system (not shown). The connected and disconnected states of are switched.

The switch 141 can be realized by a simple circuit such as connecting one or both of the NMOS transistor and the PMOS transistor in parallel.

In the example of FIG. 9, a bias transistor (load MOS) 119 that functions as a constant current source of a source follower is formed in the second semiconductor layer 210.

The bias transistor 119 has a function of inputting a bias voltage Vb to the gate to flow a constant current from the output signal line 116.

The bias transistor 119 may be disposed on the first semiconductor layer 200 side.

<4. Second Embodiment>

FIG. 10: is a figure which shows an example of the principal part circuit of the CMOS image sensor (solid-state image sensor) which concerns on this 2nd Embodiment.

The CMOS image sensor 100B according to the second embodiment differs from the CMOS image sensor 100A according to the first embodiment in that the number of branches of the output signal line 116 is two by the separation unit 140. It's more than that, in the third quarter.

In the CMOS image sensor 100B, the output signal line 116 is branched into three divided output signal lines 116-1, 116-2, and 116-3.

The amplifier circuits 117 of the pixel cells 110A-5 and 110A-6 are connected to the output signal line 116-3.

In addition to the configuration of FIG. 9, the switch 140B also includes a pair of terminals e and terminals f.

The terminal e is connected to the multilayer connection terminal 118, and the terminal f is connected to the output signal line 116-3.

The switch 141B having such a configuration is connected between the terminal a and the terminal b, the non-connected state, and the terminal c and the terminal d by the switching signal SSW by a control system (not shown). The connected and unconnected states of, and the connected and unconnected states of the terminal e and the terminal f are switched.

<5. Third Embodiment>

FIG. 11 is a diagram showing an arrangement example of pixels, stacked connection terminals, and separation units in the first semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the third embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a main part circuit of the CMOS image sensor (solid-state image sensor) in FIG. 11.

The CMOS image sensor 100C according to the third embodiment also includes the pixels in the arrangement (lateral direction in FIG. 11) perpendicular to the read scanning direction (the longitudinal direction in FIG. 11) of the pixels. To constitute a group of pixels.

In the example of FIG. 11, one laminated connection terminal 118 is shared in each of the second columns of the 0th row, the first row, the second row and the third row, the fourth row and the fifth row.

And it is wired so that it may return to the even column side from the output line L141 provided extending from the output of the even side separation part 140-1 arrange | positioned between the columns, and the output of the separation part 140-2 of the odd column side. The output line L142 is connected to the separating part 140-3 disposed at the first branch point.

Separation parts 140-0 and 140-1 form a second branching point, and basically have the same configuration as in the first embodiment.

In the switch 141-3 constituting the separation section 140-3 of the first branch point, the terminal g and the terminal h are paired, and the terminal i and the terminal j are paired. .

The terminal g is connected to the laminated connection terminal 118, and the terminal h is connected to one output line L141.

The terminal i is connected to the laminated connection terminal 118, and the terminal j is connected to the other output line L142.

The switch 141-3 having such a configuration is connected to the terminal g and the terminal h by a switching signal SSW3 by a control system (not shown), the non-connected state, and the terminal i and the terminal ( j) connected and disconnected states are switched.

In the third embodiment, the second separation point has the first separation part 140-3 at the first branch point first branched from the laminated connection terminal 118, and the second separation point is also separated from the second branch point branched next. It has the parts 140-1 and 140-2.

Although a plurality of pixels of the same pixel group are selected at the same time by read scanning, either one of the pixels simultaneously selected by the first separating unit or the second separating unit is connected to the stacked connection terminal 118.

In the example of FIG. 12, the number of pixel cells connected to the stacked connection terminals 118 when the pixels are read is reduced to one quarter compared to the case where there is no separation unit, and the speed is increased by the reduction of parasitic capacitance or low power. I am angry.

In the example of FIG. 12, although it has a separation part with a 1st branch point and a 2nd branch point, either may be sufficient.

For example, when the separation part is provided only by the first branch point, the total parasitic capacitance of the output signal line 116 can be reduced to 1/2.

When the separation unit is arranged only by the second branch point, the number of connected pixel cells can be reduced to one quarter by connecting one of four switches arranged at two second branch points.

When the parasitic capacitance of the wiring from the first branch point to the second branch point is sufficiently small with respect to the parasitic capacitance after the second branch point, even if the separation part 140-3 of the first branch point is omitted, Equivalent effect can be obtained.

Conversely, when the parasitic capacitance of the wiring from the first branch point to the second branch point is large, it is preferable that the first branch point also has a separation portion.

<6. Fourth embodiment>

FIG. 13 is a diagram showing an arrangement example of pixels, stacked connection terminals, and separation units in the first semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the fourth embodiment of the present invention.

14A to 14D are diagrams for specifically describing arrangement examples of the pixel, the laminated connection terminal, and the separation unit according to the fourth embodiment.

In the pixel array unit 110D of FIG. 13, pixel cells are arranged in a 6 × 6 matrix.

In FIG. 13, an example of arrangement in the case where the 4x4 pixel cell group GRP shares one stacked connection terminal 118 is shown as an example.

In order to minimize the wiring length to the furthest pixel, the stacked connection terminals 118 are preferably arranged near the center of the pixel group GRP of 4x4 pixel cells.

In addition, it is preferable to arrange | position the 1st branching point in which the 1st isolation | separation part 140-3 is arrange | positioned near the center of the pixel group GRP as shown to A of FIG.

As shown in FIG. 14B, for each pixel group GRP separated by the first branch point, the second separation parts 140-1 and 140-of the second branch point near its center. 2) is arranged.

Similarly, as shown in FIG. 14C, the third separation of the third branch point is near the center of each pixel group GRP separated by the second separation units 140-1 and 140-2. Part 140-4 is disposed.

As a result, the arrangement as shown in D of FIG. 14 and the configuration serving as the output signal line 116 are preferable for minimizing wiring capacitance and wiring resistance.

However, it is not limited to the center strictly by the arrangement of transistors and the congestion degree of wiring, and sufficient effect can be acquired by arrange | positioning in the vicinity of center as much as possible.

As shown in D-2 of FIG. 14, it is preferable to arrange the dummy transistor DMT as a dummy element in a portion where the separation means is not disposed in consideration of the periodicity with respect to the arrangement of the separation means.

In transistor formation of each pixel cell, by maintaining the periodicity, the characteristics of the light receiving element and the transistor are made uniform, and generation of fixed pattern noise is suppressed.

In addition, as shown to D-3 of FIG. 14, you may abbreviate | omit the isolation | separation part in some branching point, and may replace with the dummy transistor DMT.

In this example, dummy transistors DMT are disposed in place of the second separation units 140-1 and 140-2.

FIG. 15 is a diagram showing an example in which elements are arranged so that the switch and the dummy transistor of the separation portion of the branch point maintain periodicity.

A and B in FIG. 15 are circuit diagrams corresponding to D-3 in FIG. 14, and the elements are arranged so that the switch and the dummy transistor of the separation portion at the branch point maintain periodicity.

The dummy transistor DMT of FIG. 15B is constructed by grounding the gates, the drains, and the sources of two cascaded NMOS transistors NT1 and NT2 which form a switch of a separation section as an example.

FIG. 16 is a diagram showing an example in which elements are arranged so that the switch and the dummy transistor of the separation portion of the branch point maintain periodicity, and the dummy transistor has a predetermined function.

As shown in Fig. 16, the dummy transistor DMT can be configured to have any function.

In the example of FIG. 16, the dummy transistor DMT functions as the constant current source I1 of the source follower.

Specifically, the source of the NMOS transistor NT1 is grounded, the drain of the NMOS transistor NT2 is connected to the output signal line 116, and the gates of both NMOS transistors NT1, NT2 are the power supply for the bias voltage Vb. Is connected to the constant current source I1.

17 is a diagram illustrating a layout example in the case of sharing the laminated connection terminals with 4x4 pixel cells.

In the case where the stacked connection terminals 118 are shared by 4x4 pixel cells, for example, as shown in FIG. 17, the separation unit 140 can be disposed in the gap between the pixel cells 110A.

In particular, in the back-illumination type image sensor which irradiates light from the surface opposite to the transistor arrangement surface and performs photoelectric conversion, or in the image sensor which forms the photoelectric conversion film on the wiring layer, the separation part is arranged without reducing the area of the light receiving portion. It is possible.

<7. Fifth Embodiment>

FIG. 18 is a diagram showing an example of the laminated structure of the first semiconductor layer and the second semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the fifth embodiment of the present invention.

In the first semiconductor layer 200, a wiring layer 202 is formed on a silicon (Si) substrate (p type well) 201.

An n-type diffusion region 2011 as the photoelectric conversion unit (PD) 111 is formed in the Si substrate 201, and a p + diffusion region is formed in the surface portion (the boundary with the wiring layer 202) of the photoelectric conversion unit 111. (2012) is formed.

In the Si substrate 201, a plurality of n + diffusion regions 2013 of FD and n + diffusion regions 2014 of the switching transistors of the separation unit 140 are formed in the surface portion thereof.

In the wiring layer 202, a gate wiring 2021 and a signal propagation wiring 2022 of each transistor are formed in an insulating layer such as SiO ₂ , and a micro pad 2023 formed of Cu or the like is formed on the surface portion thereof. Formed.

In the wiring layer 202, a via (VIA) 2024 for connecting the n + diffusion region 2014 of the separation unit 140 with the micro pad 2023 is formed.

In the second semiconductor layer 210, a wiring layer 212 is formed on a Si substrate 211.

In the Si substrate 211, diffusion regions 2111 and 2112 of the transistor are formed in the surface portion.

In the wiring layer 212, a gate wiring 2121 and a signal propagation wiring 2122 of each transistor are formed in an insulating layer such as SiO ₂ , and a micro pad 2123 formed of Cu or the like is formed on the surface portion thereof. Formed.

In the wiring layer 202, a via (VIA) 2124 for connecting the diffusion region 2111 and the like with the micro pad 2123 is formed.

The CMOS image sensor (solid-state image sensor) 100E of FIG. 18 is an image sensor which forms the photoelectric conversion part 111 on the semiconductor surface opposite to a transistor and a wiring layer, and irradiates light from the back surface, 118) is an example using micro bumps (BMP).

The image sensor 100E faces the surface portion of the wiring layer 202 of the first semiconductor layer 200 and the surface portion of the wiring layer 212 of the second semiconductor layer 210 so as to face the micro pad 2023 and the micro pad. 2123 is connected to the micro bumps (MBP).

<8. Sixth embodiment>

FIG. 19 is a diagram showing an example of the laminated structure of the first semiconductor layer and the second semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the sixth embodiment of the present invention.

The difference between the image sensor 100F according to the sixth embodiment and the image sensor 100E according to the fifth embodiment is that the micro pad 2023 and the micro pad as the uppermost wiring are not used with the micro bumps. 2123 is directly connected.

<9. Seventh embodiment>

FIG. 20 is a diagram showing an example of the laminated structure of the first semiconductor layer and the second semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the seventh embodiment of the present invention.

The difference between the image sensor 100G according to the seventh embodiment and the image sensor 100F according to the sixth embodiment is as follows.

In this image sensor 100G, the Si substrate 211 of the second semiconductor layer 210 is disposed on the surface side of the wiring layer 202 of the first semiconductor layer 200.

The micro pad 2123 of the wiring layer 212 of the second semiconductor layer 210 and the micro pad 2023 of the wiring layer 202 of the first semiconductor layer 200 are the second semiconductor layer 210. It is connected by the through-hole via electrode 213 which penetrates through.

In addition, the wiring 2122 of the wiring layer 212 of the second semiconductor layer 210 and the wiring 2022 of the wiring layer 202 of the first semiconductor layer 200 penetrate the second semiconductor layer 210. The through hole via electrode 214 is connected.

<10. 8th Embodiment>

FIG. 21 is a diagram showing an example of the laminated structure of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the eighth embodiment of the present invention.

The CMOS image sensor 100H according to the third embodiment has a laminated structure of the first semiconductor layer 200, the second semiconductor layer 210, and the third semiconductor layer 230.

In the third semiconductor layer 220, a wiring layer 222 is formed on the Si substrate 221.

In the Si substrate 221, diffusion regions 2211 and 2212 of the transistor are formed in the surface portion.

In the wiring layer 222, a gate wiring 2221 and signal propagation wiring 2222 of each transistor are formed in an insulating layer such as SiO ₂ , and a micro pad 2223 formed of Cu or the like is formed on the surface portion thereof. It is.

In the wiring layer 222, a via (VIA) 2224 for connecting the diffusion region 2211 and the wiring 2222 or the wiring 2222 and the micro pad 2223 is formed.

In the image sensor 100H, the photoelectric conversion film 240 is formed on the wiring layer 202 of the first semiconductor layer 200, and the wiring 2022 and the second of the first semiconductor layer 200 are formed. The wiring 21222 of the semiconductor layer 210 is connected to the through hole via 203 penetrating through the first semiconductor layer 200.

The micro pad 2123 of the wiring layer 212 of the second semiconductor layer 210 and the micro pad 2223 of the wiring layer 222 of the third semiconductor layer 220 are formed of the second semiconductor layer 210. It is connected by the through-hole via electrode 213H which penetrates through.

As the photoelectric conversion film on the wiring layer, an organic photoelectric conversion film is well known. The number of stacked semiconductor layers may be any number.

As described above, if the photoelectric conversion layer is formed in a layer different from the transistor in the first semiconductor layer 200, the separation means or the laminated connection terminal can be arranged with high freedom without reducing the area of the light receiving element. Can be.

It is also possible to configure the signal processing circuit and the memory circuit to be stacked as the semiconductor layer of the third semiconductor layer and to be connected by the stacked connection terminals 118.

<11. 9th Embodiment>

Fig. 22 is a diagram showing an example of the lamination structure of the first semiconductor layer and the second semiconductor layer of the CMOS image sensor (solid-state image sensor) according to the ninth embodiment of the present invention.

In the CMOS image sensor 100I according to the ninth embodiment, the first semiconductor layer 200 is formed in the layout as shown in FIG. 13, and the AD converter 150 and the second semiconductor layer 210 are formed in the layout shown in FIG. The signal processor 160 is formed.

In the example of FIG. 22, one signal processing unit 160 is disposed in the center portion, and two AD converters 150 are disposed on both sides of the long edge parts.

In the CMOS image sensor 100I, the AD conversion circuits 151, 152, 153, and 154 are disposed so as to be parallel to each of the multilayer connection terminals 118. FIG.

In addition, as long as the pixel cell has an amplifying circuit for signal output, it may be a pixel sharing type in which a plurality of light receiving elements share an amplifying circuit, or a pixel configuration having a charge storage region for realizing collective exposure in a pixel.

As described above, according to the present embodiment, the following effects can be obtained.

In an image sensor in which a plurality of pixel cells share a connection terminal connected to a stacked (three-dimensionally mounted) semiconductor layer, the parasitic capacitance of the output signal line can be reduced, and the output signal of the pixel can be read. High speed and low power consumption can be realized.

In addition, since it can be realized only by adding a simple switch circuit and wiring, in the image sensor using the backside irradiation image sensor or the organic photoelectric conversion film, it hardly affects the reduction of the light receiving element and the reduction of the resolution.

By arranging the separation section at the multilayer connection terminal and the branch point near the center of the pixel group to be connected, the required input voltage range of the rear-end analog signal processing circuit due to the effect of high speed and low power by minimizing parasitic capacitance and uniformity of wiring resistance There is a reduction effect of.

The solid-state image sensor which has such an effect can be applied as an imaging device of a digital camera or a video camera.

<12. 10th Embodiment>

It is a figure which shows an example of the structure of the camera system to which the solid-state image sensor which concerns on embodiment of this invention is applied.

As shown in FIG. 23, the camera system 300 includes an imaging device 310 to which the CMOS image sensors (solid-state imaging elements) 100 and 100A to 100I according to the present embodiment are applicable.

Further, the camera system 300 includes an optical system for inducing incident light (image forming a subject image) in the pixel region of the imaging device 310, for example, a lens 320 for forming incident light (image light) on an imaging surface. Have

The camera system 300 has a drive circuit (DRV) 330 which drives the imaging device 310, and a signal processing circuit (PRC) 340 which processes the output signal of the imaging device 310.

The driving circuit 330 has a timing generator (not shown) for generating various timing signals including start pulses and clock pulses for driving the circuits in the imaging device 310, and the imaging device 310 is provided with a predetermined timing signal. ).

In addition, the signal processing circuit 340 performs predetermined signal processing on the output signal of the imaging device 310.

The image signal processed by the signal processing circuit 340 is recorded in a recording medium such as a memory. Image information recorded on the recording medium is hard copied by a printer or the like. The image signal processed by the signal processing circuit 340 is projected as a moving picture on a monitor made of a liquid crystal display or the like.

As described above, in an imaging device such as a digital camera, by mounting the above-described imaging elements 100, 100A to 100I as the imaging device 310, a high precision camera can be realized with low power consumption.

The present invention claims priority of Japanese Patent Application No. 2010-197734 filed with the Japan Patent Office on September 3, 2010.

Those skilled in the art can carry out various modifications, combinations, partial combinations, and modifications to the above embodiments, depending on design needs or other factors, within the scope of the following claims or equivalents thereof. There will be.

100, 200: solid-state imaging device 110: pixel array portion
110A: pixel circuit 120: row selection circuit (pixel driver)
130: readout circuit 140, 140-1 to 140-3: separator
150: AD converter 160: signal processor
111: photoelectric conversion element 112: transfer transistor
113: reset transistor 114: amplifying transistor
115: selection transistor 116, 116-1, 116-2: output signal line
117 amplification circuit 118 multilayer connection terminal
119: current source (bias transistor, load MOS)
200: first semiconductor layer 210: second semiconductor layer
220: third semiconductor layer 300: camera system
310: imaging device 320: drive circuit
330 lens 340 signal processing circuit

Claims (18)

A plurality of stacked semiconductor layers;
A plurality of laminated connection portions for electrically connecting the plurality of semiconductor layers;
A pixel array unit in which pixel cells having a photoelectric conversion unit and a signal output unit are arranged in a two-dimensional shape; And
An output signal line propagated by a signal output unit of the pixel cell;
The plurality of semiconductor layers include at least a first semiconductor layer and a second semiconductor layer,
In the first semiconductor layer, the plurality of pixel cells are arranged in a two-dimensional shape, and the signal output portion of the pixel group formed of the plurality of pixel cells shares an output signal line wired from the stacked connection portion, and the output signal line is And a separation part capable of separating any branched output signal lines at all or a part of the branch branched from the laminated connection part. The method of claim 1,
And the laminated connecting portion is disposed near the center of the pixel group sharing the output signal line connected to the laminated connecting portion. The method of claim 1,
And the separating portion is disposed near the center of the pixel group having the signal output portion connected to the output signal line after the branch point. The method of claim 1,
And a dummy element arranged in the two-dimensional array of the pixel cells of the pixel array unit and having a configuration similar to that of the separation unit and not connected to an output signal line. The method of claim 4, wherein
And the dummy element is arranged such that the two-dimensional arrangement of the separator is periodic. The method of claim 1,
In the first semiconductor layer, a pixel driver that drives pixel cells of the pixel array unit is disposed,
The pixel group sharing the stacked connection portion is a two-dimensional array of two or more pixels in a matrix, and an output signal line to which the signal output portion of the pixel cell selected simultaneously and in parallel in the pixel driver is connected to the stacked portion through the separation portion. It is connected to a connection part, The solid-state image sensor characterized by the above-mentioned. The method of claim 1,
And said photoelectric conversion section is connected to one voltage signal output section in said pixel cell. The method of claim 7, wherein
The voltage signal output unit,
A signal transistor obtained from a photoelectric conversion section is input to a gate terminal, and an amplifying transistor connected to a power source and a source signal terminal to a drain terminal;
A constant current source arranged on the side of the first semiconductor layer or on the side of the second semiconductor layer is connected to an output signal line. The method of claim 8,
A source terminal of the amplifying transistor is connected to the output signal line via a selection transistor. The method of claim 1,
The said 1st semiconductor layer has the light-receiving element which can receive the light irradiated from the opposite surface of the side in which a transistor and a wiring layer are formed, The solid-state image sensor characterized by the above-mentioned. The method of claim 1,
The first semiconductor layer includes a wiring layer and a photoelectric conversion film as a light receiving element formed on the wiring layer. The method of claim 1,
The laminated connection portion includes a micro pad disposed at the outermost layer of the first semiconductor layer and a micro pad disposed at the outermost layer at a position corresponding to the micro pad in the second semiconductor layer via the micro bumps. And a connected terminal. The method of claim 1,
The laminated connection part may include a terminal in which a micro pad disposed at an outermost layer of the first semiconductor layer and a micro pad disposed at an outermost layer at a position corresponding to the micro pad in the second semiconductor layer are directly bonded to each other. Solid-state imaging device comprising a. The method of claim 1,
The laminated connecting portion includes a contact via formed through the semiconductor layer or the insulating layer in both or one of the first semiconductor layer and the second semiconductor layer. The method of claim 1,
The second semiconductor layer includes a plurality of analog to digital (AD) conversion unit means. 16. The method of claim 15,
A plurality of said AD conversion parts are arrange | positioned so that it may become parallel with each laminated connection part. The solid-state image sensor characterized by the above-mentioned. The method of claim 1,
At least one of the signal processing circuit and the memory circuit is formed in a semiconductor layer laminated as a third semiconductor layer or a subsequent semiconductor layer, and is connected by the laminated connection portion. A solid-state imaging device;
An optical system for forming an image of a subject on the imaging device; And
A signal processing circuit for processing an output image signal of the imaging device,
The solid-state imaging device includes a pixel array in which a plurality of stacked semiconductor layers, a plurality of stacked connection portions for electrically connecting the plurality of semiconductor layers, and pixel cells having a photoelectric conversion section and a signal output section are arranged in a two-dimensional shape. And an output signal line through which a signal propagates by a signal output unit of the pixel cell,
The plurality of semiconductor layers include at least a first semiconductor layer and a second semiconductor layer,
In the first semiconductor layer, the plurality of pixel cells are arranged in a two-dimensional shape, and the signal output portion of the pixel group formed of the plurality of pixel cells shares an output signal line wired from the stacked connection portion, and the output signal line Has a separation part capable of separating any branched output signal lines at all or a part of a branch branched from the laminated connection part.

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