JP6307791B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

There is a semiconductor device provided with the same kind of semiconductor elements arranged periodically (see Patent Document 1).
[Patent Document 1] Japanese Patent Application Laid-Open No. 2006-049361

  In some cases, the characteristics of the semiconductor element vary depending on the distribution of mechanical characteristics or optical characteristics generated in the substrate itself.

In the first aspect of the present invention, a semiconductor device comprising a substrate and a plurality of light receiving elements formed in the surface direction of the substrate, the substrate is undulated due to the lamination of the substrate to another substrate, The optical conditions of the plurality of light receiving elements change due to undulations, and each of the plurality of light receiving elements is disposed at a position where the optical conditions are equal when the undulations occur, and the electrical connection between the substrate and another substrate is made. A plurality of connection portions to be formed, wherein the relative position between at least one of the plurality of light receiving elements and at least one of the plurality of connection portions is at least one other of the plurality of light receiving elements and at least one other of the plurality of connection portions. A plurality of light receiving elements are arranged so as to be the same relative position of each of the plurality of light receiving elements, and each of the plurality of light receiving elements is arranged at the same position with respect to any one of the plurality of connecting portions in the surface direction. Distribution period and multiple The value of the ratio of the arrangement period of the light receiving element, the semiconductor device is an integer excluding 1 is provided.

In the second aspect of the present invention, a semiconductor device comprising a substrate and a plurality of light receiving elements arranged in the surface direction of the substrate, wherein the substrate is stressed by stacking the substrate on another substrate, The optical conditions of the plurality of light receiving elements vary depending on the stress, and each of the plurality of light receiving elements is disposed at a position where the optical conditions are equal when the stress is generated, and the electrical connection between the substrate and another substrate is made. A plurality of connection portions to be formed, wherein the relative position between at least one of the plurality of light receiving elements and at least one of the plurality of connection portions is at least one other of the plurality of light receiving elements and at least one other of the plurality of connection portions. A plurality of light receiving elements are arranged so as to be the same relative position of each of the plurality of light receiving elements, and each of the plurality of light receiving elements is arranged at the same position in the surface direction with any of the plurality of connecting portions, Distribution period and multiple The value of the ratio of the arrangement period of the light receiving element, the semiconductor device is an integer excluding 1 is provided.

According to a third aspect of the present invention, there is provided a semiconductor device comprising a substrate and a plurality of semiconductor elements arranged in a surface direction of the substrate, wherein each of the plurality of semiconductor elements is formed by stacking the substrate on another substrate. And a plurality of connection portions that form electrical connections between the substrate and another substrate, and at least one of the plurality of semiconductor elements and at least one of the plurality of connection portions. The plurality of semiconductor elements are arranged such that the relative position between the semiconductor element and the other semiconductor element is the same as the relative position between the other at least one of the plurality of semiconductor elements and the other at least one of the plurality of connection portions. each with any of the plurality of connection portions, are arranged on the same location on the plane direction, in the planar direction, the value of the ratio of the distribution period and the arrangement period of the plurality of semiconductor elements of stress, is an integer excluding 1 semiconductor Location is provided.

  The above summary of the present invention does not enumerate all necessary features of the present invention. A sub-combination of these feature groups can also be an invention.

2 is a cross-sectional view of a light receiving substrate 100. FIG. It is sectional drawing of the process board | substrate 200. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 4 is a cross-sectional view of a laminated semiconductor device 400. FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the multilayer substrate 300. FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the multilayer substrate 300. FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the multilayer substrate 300. FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the multilayer substrate 300. FIG. 4 is a schematic cross-sectional view of a laminated semiconductor device 400. FIG. 4 is a schematic cross-sectional view of a laminated semiconductor device 400. FIG. 2 is a schematic cross-sectional view of a laminated semiconductor device 401. FIG. 2 is a schematic plan view of a laminated semiconductor device 401. FIG. 2 is a schematic cross-sectional view of a laminated semiconductor device 401. FIG. 2 is a schematic cross-sectional view of a laminated semiconductor device 402. FIG. 2 is a schematic plan view of a stacked semiconductor device 402. FIG. 4 is a schematic cross-sectional view of a stacked semiconductor device 403. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the laminated semiconductor device 403. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the laminated semiconductor device 403. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the laminated semiconductor device 403. FIG. 4 is a schematic cross-sectional view of a stacked semiconductor device 403. FIG. 4 is a schematic cross-sectional view of a laminated semiconductor device 404. FIG. 4 is a schematic cross-sectional view of a stacked semiconductor device 405. FIG. 4 is a schematic cross-sectional view of a laminated semiconductor device 406. FIG. 4 is a schematic cross-sectional view of a laminated semiconductor device 407. FIG.

  Hereinafter, the present invention will be described through embodiments of the invention. The following embodiments do not limit the invention according to the claims. Not all combinations of features described in the embodiments are essential for the solution of the invention.

  FIG. 1 is a cross-sectional view of a light receiving substrate 100 that forms a part of the laminated semiconductor device 400. The light receiving substrate 100 includes a support substrate 110, a semiconductor well 130, and a multilayer wiring layer 150.

  The support substrate 110 has a thickness that provides mechanical strength that can withstand the manufacturing process of the light receiving substrate 100. A semiconductor well 130 is disposed on one surface of the support substrate 110 via an insulating layer 120. A plurality of photodiodes 132 arranged in the surface direction of the support substrate 110 are arranged in the semiconductor well 130. A plurality of field effect transistors are formed in the semiconductor well 130 by the gate electrodes 140 and the like formed adjacent to each other.

  The multilayer wiring layer 150 is formed by interlayer insulating materials 152 and wiring materials 154 that are alternately stacked on the surface of the semiconductor well 130. As the wiring material 154, a metal material such as titanium or tungsten can be used. The interlayer insulating material 152 can be formed of silicon oxide or the like.

  The photodiode 132 and the field effect transistor are connected to each other by the multilayer wiring layer 150 to form the light receiving circuit 111. One end of the wiring member 154 in the multilayer wiring layer 150 is electrically connected to the connection pad 160 exposed to the outside on one surface opposite to the support substrate 110.

  In the light receiving circuit 111, each of the photodiodes 132 corresponds to a pixel, and a field effect transistor performs reset, selection, and amplification for each pixel. The electric charge accumulated by the photodiode 132 upon receiving incident light is output to the outside from the connection pad 160 as a voltage signal through a source follower by a field effect transistor.

  FIG. 2 is a cross-sectional view of the processing substrate 200 that forms part of the stacked semiconductor device 400. The processing substrate 200 includes a support substrate 210, a semiconductor well 230, and a multilayer wiring layer 250.

  The support substrate 210 has a thickness that provides mechanical strength to withstand the manufacturing process of the processing substrate 200. A semiconductor well 230 is disposed on one surface of the support substrate 210. A plurality of field effect transistors are formed in the semiconductor well 230 by the gate electrode 240 formed adjacent to the semiconductor well 230.

  The multilayer wiring layer 250 is formed by interlayer insulating materials 252 and wiring materials 254 that are alternately stacked on the surface of the semiconductor well 230. The plurality of field effect transistors are connected to each other by the multilayer wiring layer 250 to form the processing circuit 211.

  In addition, one end of the wiring member 254 in the multilayer wiring layer 250 is electrically connected to the connection pad 260 exposed to the outside on one surface opposite to the support substrate 210. The connection pads 260 of the processing substrate 200 are connected to the connection pads 160 of the light receiving substrate 100 when stacked with the light receiving substrate 100. Thereby, the processing circuit 211 processes the output signal of the light receiving circuit 111 of the light receiving substrate 100. The processing circuit 211 executes processes such as analog / digital conversion, noise suppression, and file generation.

  Further, the processing substrate 200 has a through electrode 256 fitted into the support substrate 210. One end of the through electrode 256 is electrically connected to the wiring member 254 of the multilayer wiring layer 250. The other end of the through electrode 256 is buried in the support substrate 210 in the illustrated stage.

  FIG. 3 is a cross-sectional view of a multilayer substrate 300 formed in the process of manufacturing a multilayer semiconductor device 400 that can be used as an image sensor. In the laminated substrate 300, the light receiving substrate 100 is laminated on the processing substrate 200 with the front and back reversed with respect to the state shown in FIG. 1. In the multilayer substrate 300, the connection pads 160 of the light receiving substrate 100 and the connection pads 260 of the processing substrate 200 are in contact with each other and are electrically connected.

  When the light receiving substrate 100 and the processing substrate 200 are stacked, the light receiving substrate 100 and the processing substrate 200 are aligned based on the positional deviations of several predetermined alignment indexes on each substrate. In the alignment, for example, the yield of the multilayer substrate 300 can be improved by a global alignment method that calculates a position where the overall positional deviation is minimized. Further, the alignment accuracy can be further improved by adding offset correction, rotation correction, orthogonality correction, scaling correction, and the like based on the position of the alignment index.

  As the alignment index, the connection pads 160 and 260 themselves may be used, or wirings and substrates formed on the light receiving substrate 100 and the processing substrate 200 may be used. Further, alignment marks provided on the light receiving substrate 100 and the processing substrate 200 may be used for the purpose of use in alignment.

  FIG. 4 is a cross-sectional view of a laminated semiconductor device 400 manufactured by further processing the laminated substrate 300. In the laminated semiconductor device 400, the support substrate 210 of the processing substrate 200 is thinned, and the bump 220 is provided at the lower end of the through electrode 256 exposed on the lower surface in the drawing. Thereby, the laminated semiconductor device 400 can be electrically connected to another substrate, a lead frame, or the like.

  In the laminated semiconductor device 400, the support substrate 110 of the light receiving substrate 100 is removed, and the light shielding layer 170, the planarization layer 172, the organic planarization layers 174 and 182, the on-chip color filter 180, and the on-chip color filter 180 are formed on the exposed insulating layer 120. A chip lens 190 and the like are sequentially stacked.

  Thereby, the photodiode 132 of the light receiving substrate 100 receives the light incident through the on-chip lens 190 and the on-chip color filter 180 without passing through the multilayer wiring layer 150. As described above, the stacked semiconductor device 400 forms a back-illuminated image sensor.

  In the laminated semiconductor device 400, the light receiving substrate 100 and the processing substrate 200 are electrically coupled through connection pads 160 and 260. Therefore, the electric charge generated by the light incident on the photodiode 132 in the light receiving substrate 100 is transferred as a voltage signal to the processing circuit 211 on the processing substrate 200 side, and further processed through digital conversion and the like, and then from the bump 220 to the outside. Is output.

  Each of the light receiving substrate 100 and the processing substrate 200 has the structure shown in FIG. 1 or FIG. 2 repeatedly in each plane direction. Therefore, by stacking the light receiving substrate 100 and the processing substrate 200, a large number of stacked semiconductor devices 400 are manufactured at once.

  Therefore, the laminated substrate 300 is cut by dicing into a large number of dies. Each of the dies thus obtained has a high yield and a high integration density by being manufactured by laminating the light receiving substrate 100 and the processing substrate 200.

  5 to 8 are schematic cross-sectional views showing in detail a part of the manufacturing process of the multilayer substrate 300 while paying attention to the bonding stage of the light receiving substrate 100 and the processing substrate 200. FIG. In the drawing, the light receiving substrate 100 and the processing substrate 200 are simplified and shown by interlayer insulating materials 152 and 252 which are insulators and connection pads 160 and 260 which are conductors.

  As shown in FIG. 5, in the manufacturing process of the multilayer substrate 300, the surface 158 where the connection pads 160 are exposed in the interlayer insulating material 152 in the light receiving substrate 100 and the connection pads in the interlayer insulating material 252 in the processing substrate 200. The surface 258 from which 260 is exposed is joined. As will be described subsequently, in joining the light receiving substrate 100 and the processing substrate 200, the interlayer insulating materials 152 and 252 are first joined together, and then the connection pads 160 and 260 are joined together.

  In bonding the light receiving substrate 100 and the processing substrate 200, first, as shown in FIG. 6, the surfaces of the light receiving substrate 100 and the processing substrate 200 are smoothed, and the bonding surfaces 159 and 259 are formed on the surfaces of the interlayer insulating materials 152 and 252. Form. The joint surfaces 159 and 259 can be smoothed by polishing, but etching may be used in combination prior to polishing. The bonding surfaces 159 and 259 are preferably smoothed to less than 1 nm, respectively. The smoothed light-receiving substrate 100 and processed substrate 200 are dried after removing residues generated by polishing by washing.

  Note that, when the bonding surfaces 159 and 259 are polished, the connection pads 160 and 260 are caused by a difference in physical properties between the interlayer insulating materials 152 and 252 that form the bonding surfaces 159 and 259 and the metal that forms the connection pads 160 and 260. The amount of polishing becomes larger than that of the interlayer insulating materials 152 and 252. For this reason, after polishing, the tip surfaces of the connection pads 160 and 260 are submerged in the interlayer insulating materials 152 and 252 than the surfaces of the bonding surfaces 159 and 259.

  Further, the metal connection pads 160 and 260 are inevitably elastically deformed by the pressure when being polished. For this reason, the front end surfaces of the connection pads 160 and 260 after polishing are not flat, and the center is recessed.

Next, the bonding surfaces 159 and 259 of the light receiving substrate 100 and the processing substrate 200 are activated. The bonding surfaces 159 and 259 can be activated by treating the surfaces of the bonding surfaces 159 and 259 with, for example, reactive ion etching or inductively coupled plasma. Further, the activated bonding surfaces 159 and 259 may be immersed in a solution such as NH ₄ OH, NH ₄ F, and HF for a short time.

  As shown in FIG. 7, the light-receiving substrate 100 and the processing substrate 200 that have activated the bonding surfaces 159 and 259 formed on the surfaces of the interlayer insulating materials 152 and 252 that are insulators are brought close to each other. The laminated substrate 300 is formed by being naturally adsorbed and bonded. Further, by allowing the light receiving substrate 100 and the processing substrate 200 to stand for about 24 hours while being adsorbed to each other, the bonding strength between the light receiving substrate 100 and the processing substrate 200 can be applied to processing such as chemical mechanical polishing of the support substrates 110 and 210. It will be tolerable.

  In the stage shown in FIG. 7, a gap remains between the connection pads 160 and 260 that have sunk from the joint surfaces 159 and 259. Further, as described above, the tip surfaces of the connection pads 160 and 260 have a shape in which the center is recessed, so that the gap between the connection pads 160 and 260 is wider at the center. For this reason, sufficient electrical connection is not yet formed between the light receiving substrate 100 and the processing substrate 200.

  Next, by reflowing the multilayer substrate 300, as shown in FIG. 8, the connection pads 160 and 260 are integrated to form the connection portion 360. By forming the connection pads 160 and 260 from a material that melts at a low temperature such as indium or tin-silver alloy, the multilayer substrate 300 can be reflowed at a low temperature of 200 degrees or less. The connection portion 360 thus formed forms an electrical connection between the light receiving substrate 100 and the processing substrate 200 in the thickness direction of these substrates.

  When the connection portion 360 is formed and the reflow process is completed, the laminated substrate 300 is naturally cooled and returned to room temperature. There is a difference in coefficient of thermal expansion between the connection part 360 formed of metal and the interlayer insulating material 152 formed of an insulator. For this reason, in the process of cooling, the connection part 360 contracts more greatly, and thermal stress acts on the laminated substrate 300.

  As shown by the exaggerated shape of the depressed portion 155 in the drawing, the thermal stress of the substrate is greatest at the position where the connecting portion 360 exists. In addition, since the plurality of connection portions 360 are arranged at a constant interval in the plane direction of the multilayer substrate 300, thermal stress acting on the multilayer substrate 300 is also periodically distributed in the plane direction of the multilayer substrate 300.

  Furthermore, as shown in FIG. 4, in the laminated semiconductor device 400 formed using the laminated substrate 300, the support substrate 210 is removed on the light receiving substrate 100 side, but one of the support substrates 210 is removed on the processing substrate 200 side. Department is left. For this reason, the stress generated in the connection part 360 has a stronger influence on the light receiving substrate 100. For this reason, a periodic distribution of optical characteristics according to the arrangement of the connection portions 360 is generated in the light receiving substrate 100.

  In addition, when a stress is applied to the semiconductor, electrical characteristics such as a resistance value change. For this reason, when the stress generated on the light receiving substrate 100 by the connection portion 360 acts, the characteristics of the semiconductor elements such as the photodiode 132 and the field effect transistor also change.

  FIG. 9 is a schematic cross-sectional view of the stacked semiconductor device 400 and is drawn focusing on the relative positions of the connecting portion 360, the photodiode 132, and the gate electrode 140. For the purpose of simplifying the drawing, a part of the cross section of the wiring layer and the like is simplified.

  In the stacked semiconductor device 400, the connecting portion 360 is located at the same position as each of the photodiodes 132 in the plane direction of the stacked semiconductor device 400, in other words, at a position overlapping the photodiode 132 in the thickness direction of the stacked semiconductor device 400. Each is arranged. This means that when the light receiving substrate 100 shown in FIG. 1 is manufactured, the connection pad 160 is formed at the same position as the photodiode 132 in the surface direction of the support substrate 110.

  With such an arrangement, the thermal stress generated in the connection portion 360 acts on the entire light receiving substrate 100 including the photodiode 132 to generate the depressed portion 155 shown in FIG. Variations in the optical characteristics of the light receiving substrate 100 act equally on each photodiode 132. Therefore, in the laminated semiconductor device 400, variation in characteristics of the photodiode 132 due to thermal stress is suppressed.

  Furthermore, in the light receiving substrate 100, each of semiconductor elements such as a field effect transistor including the gate electrode 140 disposed adjacent to each of the photodiodes 132 is also arranged at a position spaced from the connection portion 360 at equal intervals. . With such an arrangement, even when the thermal stress generated in the connection portion 360 acts on the entire light receiving substrate 100 and the capacitance value of the semiconductor element fluctuates, the fluctuation is caused by the periodically arranged semiconductor elements. Acts equally on all. Therefore, in the laminated semiconductor device 400, variations in characteristics due to thermal stress are suppressed for the periodically arranged semiconductor elements.

  FIG. 10 is a schematic cross-sectional view showing a part of the stacked semiconductor device 400 shown in FIG. 9 in detail, and exaggeratedly shows the effect of thermal stress caused by the connection portion 360. As described with reference to FIGS. 5 to 8, thermal stress may occur in the stacked semiconductor device 400 due to the presence of the connection portion 360 formed of a material different from the surroundings. FIG. 10 shows the effect of such thermal stress by a change in thickness generated in the light receiving substrate 100.

  As illustrated, in the stacked semiconductor device 400, the thickness of the light receiving substrate 100 varies periodically, and a plurality of depressions 155 are formed at positions where the photodiodes 132 are provided. Each of the photodiodes 132 receives incident light through the on-chip lens 190. Since the on-chip lens 190 is formed by flattening the surface of the light receiving substrate 100 after the light receiving substrate 100 and the processing substrate 200 are joined, the on-chip lens 190 and the photodiode 132 are located at a position where the depressed portion 155 is generated. Spacing increases.

  When the distance between the photodiode 132 and the light receiving substrate 100 changes, the amount of light received by the photodiode 132 through the on-chip lens 190 also changes. However, in the stacked semiconductor device 400, since the connection portion 360 and the photodiode 132 are arranged at the same position in the surface direction of the light receiving substrate 100, each of the photodiodes 132 is a bottom portion of the depressed portion 155. Is located.

Thus, when a representative of the respective positions of the photodiodes 132 by the bottom center of the figure, the incident surface of the photodiode 132 in the stacked semiconductor device 400 is arranged on a single array plane P _1. Therefore, the on-chip lens 190 produces the same optical action with respect to the photodiode 132, and variation in optical characteristics of the photodiode 132 due to thermal stress of the light receiving substrate 100 is suppressed.

  The distribution of thermal stress in the light receiving substrate 100 does not always appear as a variation in the thickness of the light receiving substrate 100. For example, even if the thickness of the light receiving substrate 100 is uniform in appearance, the refractive index of the light receiving substrate 100 may be distributed. In addition, in semiconductor elements other than the photodiode 132, the distribution of thermal stress may be manifested as variations in capacitance or the like. Such variation in characteristics is also suppressed by making the positional relationship between the photodiode 132 and the connection portion 360 constant.

  As described above, in the laminated semiconductor device 400, even when the non-uniform stress is generated in the laminated semiconductor device 400 due to the processing associated with polishing, bonding, and the like, and distribution is formed in the optical characteristics, the connection that causes the connection is caused. The distribution is compensated by arranging the portion 360 and the photodiode 132 at the same position. In addition, semiconductor elements arranged periodically also suppress variations in characteristics by arranging them at positions where the thicknesses are equal.

  In the above example, the photodiode 132 and the connection portion 360 are arranged at the same position in the surface direction of the light receiving substrate 100. However, even when the positions of the photodiode 132 and the connection portion 360 are not arranged at the same position, as long as the relative position between the photodiode 132 and the connection portion 360 is constant, as in the above case, The influence of thermal stress on the photodiode 132 and the like is made uniform, and variations in characteristics can be suppressed.

  FIG. 11 is a schematic cross-sectional view of another stacked semiconductor device 401. In the light receiving substrate 101 of the stacked semiconductor device 401, each of the connection portions 360 is disposed between the photodiodes 132 adjacent to each other in the plane direction of the stacked semiconductor device 401. As a result, the ratio between the arrangement period of the connecting portions 360 and the arrangement period of the photodiodes 132 is 2: 1.

  By disposing the photodiode 132 and the connection portion 360 as described above, the relative positions in the surface direction of the light receiving substrate 101 between the connection portion 360 that causes thermal stress and the individual photodiodes 132 become uniform. . Therefore, the influence of the thermal stress on the photodiode 132 becomes uniform, and the characteristic distribution of the light receiving substrate 101 due to the thermal stress is compensated.

  FIG. 12 is a schematic plan view of the stacked semiconductor device 401. The light receiving substrate 101 of the stacked semiconductor device 401 includes an on-chip color filter, and each of the photodiodes 132 selectively receives a specific band different from each other, for example, a band including any of red, blue, and green. Subpixels are formed.

In the stacked semiconductor device 401, the color pixel 134 is formed by combining a plurality of subpixels. In the illustrated example, in each of the color pixels 134, a subpixel R that is located at the lower left in the drawing and receives a band including red, and a subpixel B that is positioned at the upper right in the drawing and receives a band including blue, A single color pixel 134 is formed by combining subpixels G ₁ and G ₂ that are positioned at the upper left and lower right in the drawing and receive a band including green.

When attention is paid to the color pixel 134 in the stacked semiconductor device 401, the connection portion 360 is arranged at the same position as the center of the color pixel 134 in the surface direction of the stacked semiconductor device 401. Thereby, in each color pixel 134, the stress generated by the connection portion 360 acts equally on the four subpixels R, B, G ₁ and G ₂ . Accordingly, the subpixel R due to thermal stress in the interior of each of the color pixels 134, B, variation in G _1, G ₂ mutual characteristic can be prevented.

FIG. 13 is a schematic cross-sectional view showing a part of the stacked semiconductor device 401 shown in FIG. 12 in detail, and exaggerates the action of thermal stress caused by the connection portion 360. In each of the color pixels 134 of the stacked semiconductor device 401, the connection portion 360 is the center of each of the color pixels 134 and is located at an intermediate position between the photodiodes 132 that form the subpixels R, B, G ₁ , and G _2. It is arranged in. Therefore, each of the photodiodes 132 is located at a portion having the same height on the slope of the depressed portion 155 caused by the difference in thermal expansion coefficient of the connection portion 360.

Thus, when a representative of the respective positions of the photodiodes 132 by the bottom center of the figure, the incident surface of the photodiode 132 in the stacked semiconductor device 401 is placed on a single array plane P _2. Therefore, the on-chip lens 190 produces the same optical effect on the photodiode 132, and variations in optical characteristics of the photodiode 132 due to thermal stress are suppressed.

  In this way, by setting the arrangement period of the photodiodes 132 and the arrangement period of the connection parts 360 to an integer ratio, the influence of the stress generated by the connection parts 360 on the photodiodes 132 is uniform in the entire stacked semiconductor device 401. Thus, the characteristics of the photodiode 132 can be stabilized. In the above example, the case where the ratio of the array periods is 2: 1 is shown for the sake of explanation. However, in consideration of the integration density of the photodiodes 132 in the image sensor, the ratio of the array periods may be further increased.

  Note that the stacked semiconductor device 401 includes a connecting portion 360 that is added to the outer side (left side in the drawing) further than the outermost photodiode 132 located on the left side in the drawing. As a result, the same stress as the other photodiodes 132 acts on the outermost photodiode 132. In the laminated semiconductor device 401, a dummy connection portion 360 that is not used for electrical connection may be disposed for the purpose of maintaining the periodicity of the disposition of the connection portion 360.

  FIG. 14 is a schematic cross-sectional view of the stacked semiconductor device 402. In the light receiving substrate 101 of the stacked semiconductor device 401, each of the connection portions 360 is disposed directly below one of a pair of adjacent photodiodes 132 among the plurality of photodiodes 132 that are periodically disposed. As a result, the ratio between the arrangement period of the connection portions 360 and the arrangement period of the photodiodes 132 is 2: 1.

  In the stacked semiconductor device 402, among the plurality of photodiodes 132, the photodiode 132 arranged at the same position as the connection portion 360 in a plane direction of the stacked semiconductor device 402 and a fixed relative position with respect to the connection portion 360. The arranged photodiodes 132 are mixed. For these two types of photodiodes 132, the effects of thermal stress due to the connecting portion 360 are also different from each other. However, in the entire laminated semiconductor device 402, the influence of the thermal stress in the surface direction of the light receiving substrate 102 becomes substantially uniform. Therefore, variation in characteristics of the light receiving substrate 102 due to thermal stress is suppressed.

  FIG. 15 is a schematic plan view of the stacked semiconductor device 402. Also in the stacked semiconductor device 402, as in the stacked semiconductor device 401, each of the photodiodes 132 forms a subpixel by an on-chip color filter, and a plurality of subpixels form a color pixel 134.

When attention is paid to one color pixel 134 in the stacked semiconductor device 402, in the stacked semiconductor device 402, the connection portion 360 is disposed between _one green subpixel G ₁ and the red subpixel R. Accordingly, in the cross section shown by the dashed line S ₁ in the figure, as in the case of the photodiode 132 of the stacked semiconductor device 401 shown in FIG. 13, a photodiode 132 forming the sub-pixel G _1, R, single Are arranged on the arrangement plane.

Also, other sub-pixels B in the multilayer semiconductor device 402, a photodiode 132 forming the G ₂ is, as shown by one-dot chain line S ₂ in the figure, is arranged in a region where the connecting portion 360 is not present. Since the region where the connecting portion 360 does not exist no distribution of optical properties in the multilayer semiconductor device 402, the sub-pixel B, does not easily vary the properties of G _2.

Further, when attention is paid to the photodiode 132 corresponding to a specific band in the stacked semiconductor device 402, for example, the photodiode 132 that forms the sub-pixel R corresponding to the band including red, the entire stacked semiconductor device 402 is relative to the connection portion 360. The position becomes constant. Therefore, in the entire stacked semiconductor device 402, variations in characteristics of the subpixel R are suppressed. Similarly, with respect to the subpixels B, G ₁ , and G ₂ corresponding to other bands, variation in characteristics is suppressed in the entire stacked semiconductor device 402.

As described above, in the stacked semiconductor device 402, each type of subpixel R, B, G ₁ , G ₂ is arranged even though the connection portion 360 is arranged to be biased with respect to the position of the color pixel 134. Focusing on the above, the relative position with respect to the connecting portion 360 is kept constant. Further, the arrangement period of the individual types of subpixels R, B, G ₁ , and G ₂ forms an integer ratio with the arrangement period of the connection unit 360. Thereby, also in the laminated semiconductor device 402, the influence of the stress generated by the connection portion 360 on the photodiode 132 can be made uniform throughout the laminated semiconductor device 402, and the characteristics of the photodiode 132 can be stabilized.

  FIG. 16 is a cross-sectional view of another stacked semiconductor device 403. The laminated semiconductor device 403 has the same structure as that of the laminated semiconductor device 400 shown in FIG. Therefore, the same reference numerals are assigned to the common parts, and redundant description is omitted.

  The stacked semiconductor device 403 includes a light receiving substrate 103 and a processing substrate 201 that are bonded to each other. The light receiving substrate 103 has bumps 162 instead of the connection pads 160 in the light receiving substrate 100 shown in FIG. The processing substrate 201 has bumps 262 instead of the connection pads 260 in the processing substrate 200 shown in FIG. In the laminated semiconductor device 403, these bumps 162 and 262 electrically connect the light receiving substrate 103 and the processing substrate 201.

  17 to 19 are schematic cross-sectional views showing in detail a part of the manufacturing process of the laminated semiconductor device 403 by paying attention to the bonding stage of the light receiving substrate 100 and the processing substrate 200. FIG. In the drawing, the light receiving substrate 103 and the processing substrate 201 are shown in a simplified manner.

  As shown in FIG. 17, when manufacturing the laminated semiconductor device 403, protruding bumps 162 are formed on the lower surface of the light receiving substrate 100 in the drawing, that is, the surface 158 on the side bonded to the processing substrate 201. Further, bumps 262 are also formed on the upper surface of the processing substrate 201, that is, the surface 258 on the side bonded to the light receiving substrate 103. The bumps 162 and 262 can be formed of a metal such as solder.

  Next, as shown in FIG. 18, in a state where the light receiving substrate 103 and the processing substrate 201 are overlapped and the bumps 162 and 262 are in contact with each other, the bumps 162 and 262 are fused by pressing or heating and pressing. Thereby, an electrical connection in the thickness direction of the substrate is formed between the light receiving substrate 103 and the processing substrate 201, and the light receiving substrate 103 and the processing substrate 201 become the laminated substrate 301.

  Note that the support substrates 110 and 210 are left on the light receiving substrate 103 and the processing substrate 201 at least until the light receiving substrate 103 and the processing substrate 201 are bonded as described above. Accordingly, each of the light receiving substrate 103 and the processing substrate 201 can withstand a mechanical load related to bonding.

  When the stacked semiconductor device 403 illustrated in FIG. 16 is manufactured, after the light receiving substrate 103 and the processing substrate 201 are bonded, the support substrate 110 of the light receiving substrate 103 is removed, and the support substrate 210 of the processing substrate 201 is thinned. The support substrates 110 and 210 are removed or thinned by chemical mechanical polishing, for example.

  In chemical mechanical polishing, the pressure applied from the polishing tool to the support substrates 110 and 210 also affects the polishing efficiency. On the other hand, in the multilayer substrate 301, there are a region where the back surface of the support substrate 110, 210 to be polished is supported by the bumps 162, 262 and a region where the bumps 162, 262 are not present and are floated. For this reason, even if a flat polishing tool is used, the amount of polishing of the support substrates 110 and 210 is distributed.

  FIG. 19 is a schematic cross-sectional view showing a state after the support substrate 110 of the light receiving substrate 103 is polished. As shown in the figure, the region where the bumps 162 and 262 exist is firmly supported from the back surface by the bumps 162 and 262, so that the polishing efficiency is increased and the polishing amount is increased. On the other hand, the polishing amount is small in the region where the bumps 162 and 262 are not present. Therefore, a depression 155 is formed in a region where the bumps 162 and 262 are present in the plane direction of the stacked semiconductor device 402.

  Thus, when the laminated substrate 301 having the light receiving substrate 103 and the processing substrate 201 bonded by the bumps 162 and 262 is polished, a thickness distribution is generated on the substrate. For this reason, in the light receiving substrate 103 that transmits the incident light, the optical characteristics change according to the thickness distribution of the light receiving substrate 103 and the processing substrate 201. In addition, the characteristics of the semiconductor elements included in the light receiving substrate 103 and the processing substrate 201 also vary depending on the thickness distribution of the substrate.

  FIG. 20 is a schematic cross-sectional view of the laminated semiconductor device 403, focusing on the relative positions of the bumps 162 and 262, the photodiode 132, and the gate electrode 140 in the surface direction of the laminated semiconductor device 403. In order to simplify the drawing, a part of the cross section of the wiring layer and the like is simplified.

  In the stacked semiconductor device 403, the bumps 162 and 262 are arranged at the same position as the photodiode 132 in the plane direction of the stacked semiconductor device 403, in other words, at the position overlapping the photodiode 132 in the thickness direction of the stacked semiconductor device 403. Has been. Therefore, the period of the thickness distribution generated by polishing the support substrates 110 and 210 coincides with the arrangement period of the photodiodes 132 affected by the optical characteristics of the substrate. Thereby, the dispersion | variation in the characteristic of the photodiode 132 is suppressed.

  Similarly, each semiconductor element such as a field effect transistor arranged adjacent to each of the photodiodes 132 is also arranged with a period equal to the period of the thickness distribution of the substrate. Therefore, variation in characteristics of the semiconductor element is also suppressed.

  FIG. 21 is a schematic cross-sectional view of another stacked semiconductor device 404. In the laminated semiconductor device 404, the light receiving substrate 104 and the processing substrate 202 are joined by bumps 162 and 262.

  The bumps 162 and 262 in the laminated semiconductor device 404 are arranged in the middle of the adjacent photodiodes 132 in the plane direction of the laminated semiconductor device 404. Thereby, the arrangement period of the bumps 162 and 262 is exactly twice the arrangement period of the photodiode 132. Therefore, the change in the optical characteristics due to the thickness distribution caused by the presence of the bumps 162 and 262 affects each of the photodiodes 132 equally, and variations in the characteristics of the photodiodes 132 are suppressed.

  FIG. 22 is a schematic cross-sectional view of another stacked semiconductor device 405. In the laminated semiconductor device 405, the light receiving substrate 105 and the processing substrate 203 are joined by bumps 162 and 262.

  In the light receiving substrate 105 of the stacked semiconductor device 405, a connection portion 360 is disposed immediately below one of a pair of adjacent photodiodes 132. However, the stacked semiconductor device 405 includes a Bayer array on-chip color filter 180 to form a color image sensor, similarly to the light receiving substrate 102 of the stacked semiconductor device 402 shown in FIG. Therefore, focusing on the subpixels corresponding to each band, the photodiode 132 has a certain relative position with respect to the bumps 162 and 262 in the plane direction of the stacked semiconductor device 402. Therefore, variation in characteristics of the photodiode 132 due to the substrate thickness distribution is suppressed.

  FIG. 23 is a schematic cross-sectional view of another stacked semiconductor device 406. FIG. 23 is drawn focusing on the processing substrate 200 side in the stacked semiconductor device 406.

  Also in the laminated semiconductor device 406, the thermal stress from the connection part 360 acts on the semiconductor well 230 through the multilayer wiring layer 250. However, as already described, the processing substrate 200 is supported by a part of the support substrate 210 and has high rigidity. Therefore, the thermal stress of the connection part 360 exclusively affects the light receiving substrate 100.

  On the other hand, the processing substrate 200 has a through electrode 256 that penetrates the support substrate 210 and forms an electrical connection in the thickness direction of the support substrate 210. Since the through electrode 256 has a length that penetrates the thick support substrate 210, the through electrode 256 exerts stress on the semiconductor well 230 of the processing substrate 200.

  Therefore, in the processing substrate of the stacked semiconductor device 406, the same number of gate electrodes 240 that form semiconductor elements as field effect transistors as the through electrodes 256 are positioned in the immediate vicinity of the through electrodes 256 in the plane direction of the stacked semiconductor device 406. It is arranged. As a result, the stress acting on the semiconductor element from the through electrode 256 becomes substantially uniform, and variations in characteristics of the semiconductor element due to the stress distribution of the support substrate 210 are suppressed.

  FIG. 24 is a schematic cross-sectional view of another stacked semiconductor device 407. FIG. 24 is drawn focusing on the processing substrate 204 in the stacked semiconductor device 407.

  In the processing substrate 204 of the stacked semiconductor device 407, each of the through electrodes 256 is disposed in the middle of the adjacent gate electrodes 240 in the plane direction of the stacked semiconductor device 407. Thereby, the arrangement period of the through electrodes 256 is twice the arrangement period of the semiconductor elements. However, the distance from each of the through electrodes 256 to the gate electrode 240 is the same. Therefore, the stress generated by the through electrode 256 acts equally on each of the semiconductor elements, and variation in characteristics of the semiconductor elements is suppressed.

  Note that the structure of the processing circuit 211 formed on the processing substrate 204 is less periodic than the light receiving circuit 111 formed on the light receiving substrate 100. However, variation in element characteristics can be suppressed by selecting some semiconductor elements whose characteristics are desired to be uniform and disposing them at positions that are equidistant from the through electrodes 256.

  Further, even when the periodicity of the arrangement of the photodiode 132, the gate electrode 240, the connection portion 360, and the like is not constant throughout the stacked semiconductor devices 400, 401, 402, 403, 404, 405, 406, 407, For example, variation in characteristics can be suppressed by disposing semiconductor elements whose characteristics are preferably uniform in a region where the arrangement intervals of the connection portions 360 are equal. Furthermore, the arrangement interval of the connection portions 360 may be adjusted for the purpose of suppressing variations in characteristics of the semiconductor elements. Furthermore, a dummy connection portion 360 that is not used for electrical connection may be disposed for the purpose of suppressing variation in characteristics of the semiconductor element.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

100, 101, 102, 103, 104, 105 Light receiving substrate, 110, 210 Support substrate, 111 Light receiving circuit, 120 Insulating layer, 130, 230 Semiconductor well, 132 Photodiode, 134 Color pixel, 140, 240 Gate electrode, 150, 250 Multilayer wiring layer, 152, 252 Interlayer insulating material, 154, 254 Wiring material, 155 Depressed part, 158, 258 Surface, 159, 259 Bonding surface, 160, 260 Connection pad, 162, 220, 262 Bump, 170 Light shielding layer, 172 planarization layer, 174, 182 organic planarization layer, 180 on-chip color filter, 190 on-chip lens, 200, 201, 202, 203, 204 processing substrate, 211 processing circuit, 256 through electrode, 300, 301 multilayer substrate, 360 connections, 400, 401, 402, 403, 404, 405, 406, 407 Multilayer semiconductor device

Claims (12)

A semiconductor device comprising a substrate and a plurality of light receiving elements formed in the surface direction of the substrate,
In the substrate, undulation occurs by stacking the substrate on another substrate,
The optical conditions of the plurality of light receiving elements change due to the undulations,
Each of the plurality of light receiving elements is disposed at a position where the optical conditions are equal when the undulation occurs .
A plurality of connecting portions for forming an electrical connection between the substrate and another substrate;
A relative position between at least one of the plurality of light receiving elements and at least one of the plurality of connection portions is the same as a relative position between at least one of the plurality of light receiving elements and at least one other of the plurality of connection portions. The plurality of light receiving elements are arranged so that
The plurality of light receiving elements are respectively disposed at the same position with respect to any one of the plurality of connection portions and the surface direction,
A semiconductor device, wherein a value of a ratio between the undulation distribution period and the arrangement period of the plurality of light receiving elements is an integer other than 1 in the plane direction .   The semiconductor device according to claim 1, wherein the optical condition is an amount of light received by each of the plurality of light receiving elements, and the plurality of light receiving elements are arranged so that the amounts of received light are equal. A lens disposed above the plurality of light receiving elements;
The semiconductor device according to claim 1, wherein the optical condition is an interval between the plurality of light receiving elements and the lens, and the plurality of light receiving elements are arranged so that the intervals are equal. The undulation has a plurality of depressions;
Wherein the plurality of light receiving elements, the plurality of recessed portion, and are arranged in one of between the plurality of depressions, from claim 1 and the other not located in any one of 3 The semiconductor device described. A semiconductor device comprising a substrate and a plurality of light receiving elements arranged in a surface direction of the substrate,
In the substrate, stress is generated by stacking the substrate on another substrate,
The optical conditions of the plurality of light receiving elements are changed by the stress,
Each of the plurality of light receiving elements is disposed at a position where the optical conditions are equal when the stress is generated ,
A plurality of connecting portions for forming an electrical connection between the substrate and another substrate;
A relative position between at least one of the plurality of light receiving elements and at least one of the plurality of connection portions is the same as a relative position between at least one of the plurality of light receiving elements and at least one other of the plurality of connection portions. The plurality of light receiving elements are arranged so that
The plurality of light receiving elements are respectively disposed at the same position with respect to any one of the plurality of connection portions and the surface direction,
A semiconductor device, wherein a value of a ratio between a distribution period of the stress and an arrangement period of the plurality of light receiving elements is an integer excluding 1 in the plane direction . The semiconductor device according to claim 5 , wherein the stress includes a thermal stress generated by a thermal history with respect to the semiconductor device. The semiconductor device according to claim 1, further comprising the other substrate stacked on the substrate. Wherein the plurality of light receiving elements, and one of each of the plurality of connection portions, the semiconductor device according to any one of claims 1 to 7 disposed at a position that overlaps the said surface direction. A plurality of second light receiving elements each having a plurality of first light receiving elements each corresponding to a first light receiving band and a plurality of other light receiving elements each corresponding to a second light receiving band; of a sub-pixel, the semiconductor device according to any one of the plurality of first sub-pixels and the plurality of second of claims 1 to form a pixel in sub-pixel 8. In the plurality of first subpixels and the plurality of second subpixels forming the pixel, the plurality of light receiving elements and the plurality of other light receiving elements are disposed at the same height position. Item 10. The semiconductor device according to Item 9 . A semiconductor device comprising a substrate and a plurality of semiconductor elements arranged in a surface direction of the substrate,
Each of the plurality of semiconductor elements is disposed at a position where stress generated in the substrate acts equally when the substrate is stacked on another substrate ,
A plurality of connecting portions for forming an electrical connection between the substrate and another substrate;
A relative position between at least one of the plurality of semiconductor elements and at least one of the plurality of connection portions is the same as a relative position between at least one other of the plurality of semiconductor elements and at least one other of the plurality of connection portions. The plurality of semiconductor elements are arranged so that
Each of the plurality of semiconductor elements is arranged at the same position as any one of the plurality of connection portions in the plane direction,
A semiconductor device, wherein a value of a ratio between a distribution period of the stress and an arrangement period of the plurality of semiconductor elements is an integer other than 1 in the plane direction . A plurality of connecting portions for forming connections in the thickness direction of the substrate;
A relative position between at least one of the plurality of semiconductor elements and any one of the plurality of connection portions is a relative position between at least one other of the plurality of semiconductor elements and any one of the plurality of connection portions. The semiconductor device according to claim 11 , wherein the plurality of semiconductor elements are arranged so as to be the same.

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