KR20120016780A - Method of manufacturing vertical light emitting diode device - Google Patents

Abstract

PURPOSE: A method of manufacturing a vertical light emitting diode device is provided to a process time and manufacturing costs by reducing the processing depth of a via hole. CONSTITUTION: A first compound semiconductor layer(111), an active layer(112), a second compound semiconductor layer(113) are laminated on the substrate(100) to form a compound semiconductor structure(110). A first conductive layer(130) and a second conductive layer(140) are formed in the top side of the compound semiconductor structure. An insulating layer(120) is coated in the remaining area except for a part of the domain in which the first conductive layer and the second conductive layer are arranged. A first electrode(171) and a second electrode(172) are form in the conductive substrate(170) while the first and second electrodes are separated from each other. The first electrode and second electrode are respectively electrically connected to the first conductive layer and the second conductive layer.

Description

Method of manufacturing vertical light emitting device

The present invention relates to a vertical light emitting device manufacturing method.

A light emitting device, such as a light emitting diode (LED), refers to a semiconductor device capable of realizing various colors of light by forming a light emitting source through pn junction of a compound semiconductor. For example, nitride-based LEDs are group III-V compound semiconductors such as GaN, InN, and AlN, and are widely used in light emitting devices capable of emitting short wavelength light (ultraviolet to green light), particularly blue light. Such a light emitting device has a long lifespan, can be downsized and lightened, and has a strong directivity of light to enable low voltage driving. In addition, such a light emitting device is resistant to shock and vibration, does not require preheating time and complicated driving, and can be packaged in various forms, and thus can be applied to various applications.

One approach to manufacturing light emitting devices such as LEDs is to employ a vertical structure in which compound substrate layers are removed using an insulating substrate, such as a sapphire substrate, which is known to most satisfy the lattice matching conditions for crystal growth. It is proposed. The vertical light emitting device is classified into a case in which an n-type electrode and a p-type electrode are provided on the same side of the compound semiconductor structure and a case where the n-type electrode and the p-type electrode are provided on different surfaces of the compound semiconductor structure. Positioning the n-type electrode and the p-type electrode on the same side of the compound semiconductor structure is advantageous in terms of current spreading, and it is advantageous in that it can reduce the phenomenon that the light path of the light is blocked by the electrode. have.

In the vertical light emitting device in which the first conductive layer and the second conductive layer are located on the same side of the compound semiconductor structure, the present invention can manufacture a vertical light emitting device that can be easily mass-produced and large in area, and can reduce manufacturing costs. Provide a method.

According to an aspect of the present invention, there is provided a method of manufacturing a vertical light emitting device, including: forming a compound semiconductor structure by stacking a first compound semiconductor layer, an active layer, and a second compound semiconductor layer on a substrate; Forming a first conductive layer and a second conductive layer electrically connected to the first compound semiconductor layer and the second compound semiconductor layer, respectively, on an upper surface of the compound semiconductor structure; Applying an insulating layer to a region other than a portion of the region in which the first conductive layer and the second conductive layer are located; Forming a first electrode on the conductive substrate so as to be exposed to one surface of the conductive substrate, and a second electrode spaced apart from the first electrode; Bonding the conductive substrate using the conductive adhesive layer such that the first electrode and the second electrode are electrically connected to the first conductive layer and the second conductive layer, respectively; Removing a portion of the conductive substrate such that the first electrode and the second electrode are exposed to the other surface of the conductive substrate; and removing the substrate.

The thickness of the 1st electrode and the 2nd electrode is 130 micrometers-150 micrometers.

Forming the first conductive layer and the second conductive layer,

Forming at least one via hole from at least one region of the second compound semiconductor layer to the first compound semiconductor layer; Forming a protective layer on the second compound semiconductor layer and at least one non-hole; Exposing the first compound semiconductor layer by removing a protective layer located at the bottom of the at least one hole; Forming a first conductive layer in the exposed region of the first compound semiconductor layer; Removing a protective layer in a region in which at least one via hole of the second compound semiconductor layer is not formed; And forming a second conductive layer in the exposed region by removing the protective layer of the second compound semiconductor layer.

Applying the insulating layer,

Applying an insulating layer over the top surface of the first conductive layer, the second conductive layer, and the compound semiconductor structure; And exposing the first conductive layer and the second conductive layer by removing regions in which the first conductive layer and the second conductive layer are located in the insulating layer.

The compound semiconductor structure is formed by stacking nitride semiconductor layers.

The substrate is a sapphire substrate.

The method of manufacturing a vertical light emitting device according to the disclosed embodiment can reduce processing time and cost by reducing processing depths of via holes for forming a first electrode and a second electrode on a conductive substrate.

1 to 11 is a cross-sectional view sequentially showing the method for manufacturing a vertical light emitting device according to an embodiment of the present invention.
<Description of the symbols for the main parts of the drawings>
100 --- substrate 110 --- compound semiconductor structure
111 --- First Compound Semiconductor Layer 112 --- Active Layer
113 --- second compound semiconductor layer 120 --- insulating layer
130 --- first conductive layer 140 --- second conductive layer
160 --- conductive adhesive layer 170 --- conductive substrate
171 --- first electrode 172 --- second electrode
180 --- Insulation bulkhead

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments illustrated below are not intended to limit the scope of the invention, but rather to provide a thorough understanding of the invention to those skilled in the art. In the drawings, like reference numerals refer to like elements, and the size of each element in the drawings may be exaggerated for clarity and convenience of description.

1 to 11 are process cross-sectional views sequentially illustrating a method of manufacturing a vertical light emitting device according to an embodiment of the present invention. 1 to 11 illustrate a process of manufacturing one light emitting device for convenience of description, in practice, a plurality of light emitting devices are integrally formed on a wafer and then cut individually to manufacture individual light emitting devices.

Referring to FIG. 1, the compound semiconductor structure 110 is formed by sequentially growing the first compound semiconductor layer 111, the active layer 112, and the second compound semiconductor layer 113 on the upper surface of the substrate 100. .

The substrate 100 may be selected to be suitable for the compound semiconductor to be crystal-grown. For example, in the case of growing a nitride semiconductor single crystal, the substrate 100 may include a sapphire substrate, a zinc oxide (ZnO) substrate, a gallium nitride (GaN) substrate, and a silicon carbide (Sillicon Carbide (SiC) substrate. And aluminum nitride (AlN) substrates. Although not shown in FIG. 1, a buffer layer (not shown) may be formed between the substrate 100 and the first compound semiconductor layer 111. The buffer layer is a layer for improving lattice matching with the substrate 100 before growing the first compound semiconductor layer 111 and may be generally formed of AlN / GaN.

The compound semiconductor structure 110 may be formed by, for example, crystal growth of a group III-V compound semiconductor such as GaN, InN, AlN, or the like. For example, when the compound semiconductor structure 110 is a gallium nitride-based light emitting diode, the first compound semiconductor layer 111, the active layer 112, and the second compound semiconductor layer 113 may be Al _x In _y Ga _{(1-xy). )} May be a semiconductor material having an N composition formula (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), and a metal organic chemical vapor deposition (MOCVD) facility is installed. It may be formed by the epitaxial growth method used. That is, the first compound semiconductor layer 111 may be formed of a GaN or GaN / AlGaN layer doped with first conductivity type impurities such as Si, Ge, and Sn. The active layer 112 may be formed of an InGaN / GaN layer having a multi-quantum well structure, or may be formed of one quantum well layer or a double hetero structure. The second compound semiconductor layer 113 may be formed of a GaN layer or a GaN / AlGaN layer doped with a second conductivity type impurity such as Mg, Zn, or Be.

Next, referring to FIG. 2, a portion of the compound semiconductor structure 110 corresponding to the region corresponding to the formation region of the first conductive layer 130 (see FIG. 1) is formed to have a predetermined depth from the second compound semiconductor layer 113. Etching to form a via hole 110a to expose a portion of the first compound semiconductor layer 111. The via hole 110a may be formed in a mesa structure or a vertical structure. A plurality of via holes 110a may be formed to correspond to the plurality of first conductive layers 130. Thereafter, a passivation layer 121 is applied to the entire upper surface of the compound semiconductor structure 110 including the via holes 110a by using a known deposition method. For example, the protective layer 121 may be formed by depositing SiO ₂ to a thickness of about 6000 kW using plasma enhanced chemical vapor deposition (PECVD).

Next, referring to FIG. 3, the portion of the protective layer 121 formed in the bottom of the via hole 110a is etched to expose the first compound semiconductor layer 111. Such etching may be performed using, for example, reactive ion etching (RIE) and buffered oxide etch (BOE). Then, the first conductive layer 130 is formed in the exposed region of the first compound semiconductor layer 111. For example, the first conductive layer 130 may be formed by depositing an Al / Ti / Pt layer with a thickness of 200 nm / 1200 nm / 20 nm. In this case, a plurality of first conductive layers 130 may be formed to improve current spreading to the first compound semiconductor layer 111.

Referring to FIG. 4, the protective layer 121 in the remaining regions except for the region surrounding the first conductive layer 130 is etched to expose the second compound semiconductor layer 113. Such etching can be done using, for example, RIE and BOE. Next, the second conductive layer 140 is formed on the exposed second compound semiconductor layer 113. In this case, the second conductive layer 140 is formed to be spaced apart from the first conductive layer 130. The second conductive layer 140 may be formed of a metal having both ohmic and light reflecting properties to serve as a reflective film, or may be formed as a multilayer formed by sequentially stacking metals having both ohmic and light reflecting properties. For example, the second conductive layer 140 may be formed by depositing a Ni / Ag / Pt / Ti / Pt layer with a thickness of 0.5 nm / 250 nm / 50 nm / 300 nm / 50 nm.

Next, referring to FIG. 5, an insulating material layer 122 is coated on the upper side of the compound semiconductor structure 110 with a predetermined thickness. The insulating material layer 122 is applied to the entire area including the first conductive layer 130, the second conductive layer 140, and the protective layer 121. The insulating material layer 122 may be formed by, for example, depositing SiO ₂ to a thickness of about 8000 kPa using PECVD. The protective layer 121 and the insulating material layer 122 may be formed of the same material, and form the insulating layer 120 with respect to the first conductive layer 130 and the second conductive layer 140.

Next, referring to FIG. 6, the insulating layer 120 is etched to expose the first conductive layer 130 and the second conductive layer 140. A conductive adhesive layer 160 for bonding is formed on the first conductive layer 130 and the second conductive layer 140. The conductive adhesive layer 160 is formed by patterning the first electrode region 161 and the second electrode region 162. The first electrode region 161 and the second electrode region 162 are separated by the boundary region 160a. The first electrode region 161 is an area covering the exposed first conductive layer 130, and the second electrode region 162 is an area where a part of the second conductive layer 140 is exposed.

Next, as shown in FIG. 7, the insulating partition wall 180 is formed by filling an insulating material in the boundary region 160a of the conductive adhesive layer 160. After forming the insulating partition 180, the surface of the conductive adhesive layer 160 may be planarized through a process such as chemical mechanical polishing (CMP).

Referring to FIG. 8, the second via hole 172a is disposed at a portion spaced apart from the first via hole 171a and the first via hole 171a by a predetermined depth (x) from the upper surface 170a of the conductive substrate 170. Form. Via holes may be formed using various methods such as mechanical drilling, ultrasonic processing, laser processing, sand blasting or dry etching, or a combination of these methods. The etching depth x of the first via hole 171a and the second via hole 172a is 130 μm to 150 μm. Then, each of the first bar hole 171a and the second via hole 172a is filled with a metal material such as copper, nickel, or chromium by a sputter or chemical vapor deposition (CVD) method. 171 and the second electrode 172 are formed.

Then, as illustrated in FIG. 9, the conductive substrate 170 is bonded to the conductive adhesive layer 160 by applying a predetermined temperature and pressure. The conductive substrate 170 is bonded onto the conductive bonding layer 160 by applying a temperature of 300 ° C. or higher and a predetermined pressure to the conductive bonding layer 160. Since the conductive substrate 170 serves as a supporting layer of the final light emitting device and a temperature of 300 ° C. or more is applied during bonding, it is preferable to use a substrate having a thermal expansion coefficient similar to that of the substrate 100. As the conductive substrate 170, a silicon (Si) substrate, a GaAs substrate, or a Ge substrate may be used.

Referring to FIG. 10, the conductive substrate 170 is etched to expose the first electrode 171 and the second electrode 172 from the lower surface (170b of FIG. 8) of the conductive substrate 170. As a result, the thickness of the via holes 171a and 172a formed in the conductive substrate 170 becomes thinner than before, thereby reducing process time and cost.

Meanwhile, after the first electrode 171 and the second electrode 172 are formed in the manufacturing procedure shown in FIG. 8, the first electrode 171 is formed from the lower surface 170b of the conductive substrate 170 as shown in FIG. 10. ) And the second electrode 172 may be etched to expose the conductive substrate 170.

Next, referring to FIG. 11, the substrate 100 is removed from the compound semiconductor structure 110. The upper surface 110c (see FIG. 1) of the compound semiconductor structure 110 is a portion from which light is extracted and removes the substrate 100 to increase light extraction efficiency. In addition, although not shown in the drawings, the surface uneven structure is formed on the upper surface 110c of the compound semiconductor structure 110, thereby increasing the light extraction efficiency.

The above-described method for manufacturing a vertical light emitting device according to the present invention has been described with reference to the embodiments shown in the drawings for clarity, but it is merely an example, and those skilled in the art may have various modifications and equivalents therefrom. It will be appreciated that other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the appended claims.

Claims (6)

Stacking a first compound semiconductor layer, an active layer, and a second compound semiconductor layer on a substrate to form a compound semiconductor structure;
Forming a first conductive layer and a second conductive layer electrically connected to the first compound semiconductor layer and the second compound semiconductor layer, respectively, on an upper surface of the compound semiconductor structure;
Applying an insulating layer to a region other than a portion of the region in which the first conductive layer and the second conductive layer are located;
Forming a first electrode on the conductive substrate and a second electrode spaced apart from the first electrode so as to be exposed on one surface of the conductive substrate;
Bonding the conductive substrate using a conductive adhesive layer such that the first electrode and the second electrode are electrically connected to the first conductive layer and the second conductive layer, respectively;
Removing a portion of the conductive substrate such that the first electrode and the second electrode are exposed to the other surface of the conductive substrate;
Removing the substrate; Method of manufacturing a vertical light emitting device comprising a. The method of claim 1,
The thickness of the first electrode and the second electrode is a manufacturing method of the vertical light emitting device is 130㎛ 150㎛. The method according to claim 1,
Forming the first conductive layer and the second conductive layer,
Forming at least one via hole from at least one region of the second compound semiconductor layer to the first compound semiconductor layer;
Forming a protective layer on the second compound semiconductor layer and the at least one non-hole;
Exposing the first compound semiconductor layer by removing a protective layer located at the bottom of the at least one hole;
Forming a first conductive layer in an exposed region of the first compound semiconductor layer;
Removing a protective layer of a region in which the at least one via hole is not formed in the second compound semiconductor layer; And
And forming a second conductive layer in the exposed area by removing the protective layer of the second compound semiconductor layer. The method according to claim 1,
Applying the insulating layer,
Applying an insulating layer over the upper surface of the first conductive layer, the second conductive layer, and the compound semiconductor structure; And
And exposing the first conductive layer and the second conductive layer by removing regions in which the first conductive layer and the second conductive layer are located in the insulating layer. The method according to claim 1,
The compound semiconductor structure is a method of manufacturing a vertical light emitting device formed by stacking nitride semiconductor layers. The method according to claim 1,
The substrate is a sapphire substrate manufacturing method of a vertical light emitting device.

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