KR20120003655A - Image sensor - Google Patents

Abstract

PURPOSE: An image sensor is provided to reduce a reset signal sampling section and an image signal sampling section. CONSTITUTION: If a pixel control signal is activated, a pixel unit(310) outputs a pixel signal. When the pixel control signal is deactivated, a sampling rate accelerator(340) discharges the output node of the pixel unit. The sampling rate accelerator comprises a pulse generator(341) and an electric discharge unit. The pulse generator is synchronized in the inactivation timing of the pixel control signal. The pulse generator generates a pulse signal.

Description

Image Sensor

The present invention relates to an image sensor.

In general, an image sensor among semiconductor devices is a semiconductor device that converts an optical image into an electrical signal. Representative image sensor devices include a charge coupled device (CCD) and a CMOS image sensor; CIS).

Among them, the charge-coupled device is a device in which charge carriers are stored and transported in the capacitor while individual metal-oxide-silicon (MOS) capacitors are located very close to each other, and the CMOS image sensor is a control circuit and a signal processing device. By using CMOS technology that uses a signal processing circuit as a peripheral circuit, a MOS transistor (typically four MOS transistors) corresponding to the number of pixels is made and sequentially output using the same.

1 is a circuit diagram of an image sensor according to the related art.

Referring to FIG. 1, the image sensor 200 includes a plurality of unit pixels, and each unit pixel includes a pixel unit 210, a signal output unit 220, and a current source 230. The pixel unit 210 includes a photodiode PD, a reset transistor n1, a driving transistor n2, a line selection transistor n3, and a transfer transistor n4. It can be seen that the signal output unit 220 includes an image output transistor n5, a reset output transistor n6, an image capacitor Cs, and a reset capacitor Cr.

Hereinafter, a sampling operation of an image sensor according to the related art will be described with reference to FIG. 2.

When the line selection control signal Ls is activated and the reset control signal Rx and the reset output control signal Rs are also activated, the image sensor 200 generates a floating voltage through the reset transistor n1. The driving and line selection transistors n2 and n3 are transferred to the fusion node FD and output the reset signal rst generated by source following the driving voltage VDD to the output node out. The reset output transistor n6 then causes the rst node rst to have the same voltage level as the output node out.

Subsequently, when the reset control signal Rx is deactivated, the voltage level of the output node out is gradually lowered due to a clock feed-through phenomenon. At this time, since the current amount of the current source 230 has a relatively small value of several uA, and the capacity of the reset capacitor Cr has a large value, the charge of the reset capacitor Cr is slowly discharged. As a result, the voltage level of the output node (out) becomes slow, and as a result, the reset signal rst has a long signal tail.

For this reason, the stabilization time of the output node (out) also becomes relatively long, and thus a problem arises in that the next sampling operation should be performed for a sufficient time. This problem also occurs in the sampling operation of the image signal sig, so that the sampling rate of the image sensor is lowered as a whole.

Accordingly, the present invention is to provide an image sensor that can improve the sampling rate of the image sensor by shortening the output node stabilization time of the pixel portion.

As a means for solving the above problems, according to an embodiment of the present invention, a pixel unit for outputting a pixel signal when the pixel control signal is activated; And a sampling rate accelerator for discharging an output node of the pixel unit when the pixel control signal is deactivated.

The image sensor of the present invention further includes a sampling rate accelerator connected to an output node of the pixel unit, and connects the output node to ground when the reset control signal or the transfer control signal is deactivated to transfer charges applied to the output node. By artificially discharging, the stabilization time of the output node of the pixel portion is shortened.

Accordingly, the reset signal sampling section and the video signal sampling section can be shortened, and the time interval between different sampling operations can be shortened, thereby improving the sampling rate of the image sensor as a whole.

1 is a circuit diagram of an image sensor according to the related art.
2 is a signal timing diagram for explaining a sampling method of an image sensor according to the related art.
3 is a circuit diagram of an image sensor according to an exemplary embodiment of the present invention.
4 is a detailed circuit diagram of a pulse generator according to an embodiment of the present invention.
5 is a signal timing diagram for describing an operation of a pulse generator according to an exemplary embodiment of the present invention.
6 is a signal timing diagram illustrating a sampling method of an image sensor according to an exemplary embodiment of the present invention.

As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description.

However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. In describing the present invention, in order to facilitate the overall understanding, the same reference numerals are used for the same elements in the drawings, and redundant description of the same elements is omitted.

3 is a circuit diagram of an image sensor according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the image sensor 300 includes a plurality of unit pixels, and each unit pixel has a pixel signal having a value corresponding to the driving voltage VDD when the reset control signal Rx is activated. The pixel unit 310 outputs a pixel signal having a value corresponding to the amount of photo charge accumulated in the photodiode when the transfer control signal Tx is activated, and the pixel when the reset output control signal Rs is activated. The signal output unit 32 and the image sensor 300 which output a reset signal rst by sampling a signal, and output a video signal sig by sampling a pixel signal when the image output control signal Ss is activated. Sampling rate acceleration unit for discharging the output node (out) of the pixel portion 310 when the current source 330, the reset control signal (Rx) or the transfer control signal (Tx) for providing a driving current (I) of the 340) and the like.

For reference, since the image sensor 300 generates the reset signal and the image signal by the source following method, the voltage level rising speed of the output node out is very fast while the voltage level falling speed is relatively slow.

Accordingly, the present invention aims to improve the sampling rate of the image sensor as a whole by improving the voltage level drop rate of the output node out.

Subsequently, the pixel unit 310 floats the driving voltage VDD when the photo diode PD and the reset control signal Rx, which accumulate photocharges according to the amount of light incident thereon, are activated. When the reset transistor n1 applied to the transfer control signal Tx is activated, the transfer transistor n4 that applies a signal corresponding to the amount of photocharge accumulated in the photodiode PD to the floating diffusion node FD, When the driving transistor n2 for source following the voltage of the floating diffusion node FD and the line selection control signal Ls are activated, the output of the driving transistor n2 is transferred to the output node out. And a line select transistor n3.

When the image output control signal Ss is activated, the signal output unit 320 outputs an image output transistor n5 and an image capacitor by sampling a pixel signal applied to the output node out and outputting an image signal sig. (Cs), when the reset output control signal Rs is activated, the reset output transistor n6 for sampling the pixel signal applied to the output node out and outputting the reset signal rst, and the reset capacitor Cr. Is made of.

The sampling rate accelerator 340 generates a pulse signal 341 for generating a pulse signal Sp_en in synchronization with the deactivation time of the reset control signal Rx or the transfer control signal Tx, and the pulse signal. And a discharge unit n7 which discharges the output node out in response to Sp_en.

4 is a detailed circuit diagram of a pulse generator according to an embodiment of the present invention.

Referring to FIG. 4, the pulse generator 341 receives the reset control signal Rx, the transfer control signal Tx, and the operation enable signal En_n to perform a logical sum operation on a first logic gate ( OR), odd number of inverters D1 to D3 for inverting and delaying an output signal of the first logic gate OR, and output signals of the first logic gate OR and the odd number of inverters D1 to The second logic gate NOR generates the pulse signal Sp_en by receiving the output signal of D3) and performing a negative-OR operation.

In this case, the operation enable signal En_n may be generated by a controller (not shown) that generates general timing control signals and addressing signals for selecting each pixel and outputting a sensed image signal. The signal value may vary depending on whether the corresponding pixel unit is activated.

Hereinafter, the operation of the pulse generator 341 according to an embodiment of the present invention will be described with reference to FIG. 5.

When one of the reset control signal Rx and the transfer control signal Tx is activated, the first logic gate OR outputs a high level signal and the odd-numbered inverters D1 to D3 output a low level signal. do. The second logic gate NOR negatively sums them and outputs a low level signal.

In this state, when any one of the reset control signal Rx and the transfer control signal Tx is deactivated again, only the signal of the first logic gate OR is transitioned to the low level and the second logic gate NOR is the high level. Outputs the signal of.

When a predetermined time (time equal to the delay time of the odd number of inverters D1 to D3) has elapsed and the odd number of inverters D1 to D3 output a high level signal, the second logic gate NOR is again low. Outputs a level signal.

As a result, the pulse generator 341 of the present invention can generate the pulse signal Sp_en clocked in synchronization with the point of inactivation of the reset control signal Rx or the transfer control signal Tx.

Hereinafter, a sampling operation of the image sensor 300 according to an exemplary embodiment of the present invention will be described with reference to FIG. 6.

First, the photodiode PD accumulates an optical charge corresponding to the amount of light incident on the photodiode PD.

If the reset control signal Rx and the reset output control signal Rs are also enabled after the line selection control signal Ls is activated in this state, the reset transistor n1 floats the driving voltage VDD. The driving node n2 and the line select transistor n3 output a signal corresponding to the driving voltage VDD to the output node out.

When the reset control signal Rx is deactivated again after a predetermined time, the supply of the driving voltage is interrupted by the reset transistor n1, and the voltage level of the output node out is set to the signal output unit 320 (especially, the reset capacitor). The clock feed-draw phenomenon by (Cr)) starts to decrease gradually. In this case, the voltage drop rate due to the clock feed-draw phenomenon depends on the rate at which the charge of the reset capacitor Cr is discharged according to the current amount of the current source 330.

However, the present invention further includes a sampling rate accelerator 340 connected to the output node out, thereby artificially discharging the output node out when the line selection control signal Ls is deactivated, thereby outputting the output node. It shortens the stabilization time of (out). At this time, the signal tail of the reset signal is shorter than in the prior art as shown in FIG.

Accordingly, the reset signal sampling period can be shortened by the stabilization time (Δt) of the output node (out) shortened, and the image signal sampling operation after the reset signal sampling operation is also shortened. As soon as you can do it.

The same effect appears in the video signal sampling interval, which will be described below.

After the output node out is stabilized by the above operation, when the transfer control signal Tx and the image output control signal Ss are activated instead of the reset control signal Rx and the reset output control signal Rs, The signal corresponding to the amount of photo charge accumulated in the diode PD is transferred to the output node out through the driving transistor n2 and the line selection transistor n3.

When the transfer control signal Tx is deactivated again after a predetermined time, the line select transistor n3 cuts off the supply of a signal corresponding to the amount of photo charge.

Then, the voltage level of the output node (out) is drastically lowered again by the signal output unit 320 (particularly, the image capacitor Cs) and the discharge unit n7, and the stabilization time of the output node (out) at this time is also conventionally reduced. Compared to the shorter.

Therefore, the video signal sampling interval can be shortened by the stabilization time (△ t) of the shortened output node (out), and the next sampling operation can be performed earlier by the stabilization time (△ t) of the shortened output node (out). do.

As described above, in the present invention, by using the sampling rate accelerator 340, the reset signal sampling section and the image signal sampling section can be shortened, and the time interval between different sampling operations can be shortened, thereby, the sampling rate of the image sensor. Improve overall.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

300: unit pixel 310: pixel portion
320: signal output unit 330: current source
340: sampling rate accelerator 341: pulse generator

Claims (5)

A pixel unit which outputs a pixel signal when the pixel control signal is activated; And
And a sampling rate accelerator for discharging an output node of the pixel portion when the pixel control signal is deactivated.
The method of claim 1, wherein the sampling rate acceleration unit
A pulse generator for generating a pulse signal in synchronization with the point of inactivation of the pixel control signal; And
And a discharge unit configured to discharge an output node of the pixel unit in response to the pulse signal.
The method of claim 1, wherein the pixel control signal is
An image sensor, characterized in that a reset control signal or a transfer control signal.
The method of claim 3, wherein the pixel unit
Outputting a pixel signal having a value corresponding to a driving voltage when the reset control signal is activated, and outputting a pixel signal having a value corresponding to the amount of photo charge accumulated in the photodiode when the transfer control signal is activated. Image sensor.
The method of claim 4, wherein
And a signal output unit for sampling the pixel signal when the reset output control signal is activated and outputting a reset signal, and outputting an image signal by sampling the pixel signal when the image output control signal is activated. sensor.

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