KR20080035914A - Low noise cmos image sensor with low power consumption - Google Patents

Abstract

A low noise CMOS image sensor with low power consumption is provided to remove noise due to transistors by including no transistors installed in existing pixel sensors, and reduce power consumption by removing a current path formed by transistors. In a pixel sensor array, plural pixel sensors are arranged in columns and rows. Plural transfer circuits are respectively related with the rows. Each of the pixel sensors receives lamp voltage, and compares the lamp voltage with a difference between reset voltage and pixel signal voltage corresponding to image information inputted form the outside. The pixel sensor outputs a comparison signal. Each of the transfer circuit transfers the comparison signal from the related pixel sensor to outside.

Description

LOW NOISE CMOS IMAGE SENSOR WITH LOW POWER CONSUMPTION

1 is a block diagram showing a configuration of a general CMOS image sensor including an analog-to-digital converter having a CDS structure.

2 exemplarily shows a configuration of one pixel in the active pixel sensor array shown in FIG. 1 and one CDS circuit in an analog-to-digital converter;

3 is a view showing the configuration of one pixel sensor and one transfer circuit corresponding to one column provided in a CMOS image sensor according to an exemplary embodiment of the present invention; And

 4 is a timing diagram of signals used in the pixel sensor shown in FIG. 3.

* Description of the main parts of the drawings

100: CMOS image sensor 110: active pixel sensor array

120: analog-to-digital converter 130: data buffer

140: lamp voltage generator 150: low driver

160: timing controller 210: fax sensor

220: transmission circuit

The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor, and more particularly to a CMOS image sensor comprising a correlated double sampling circuit.

The image sensor refers to a device for capturing an image by using a property of a semiconductor that reacts to light. In recent years, with the development of CMOS technology, an image sensor using a CMOS transistor has been widely used.

Such an image sensor includes an analog-to-digital converter for converting acquired analog image information into a digital signal, and the analog-to-digital converter is generally configured in a correlated double sampling (CDS) structure.

1 is a block diagram showing a configuration of a general CMOS image sensor including an analog-to-digital converter having a CDS structure.

Referring to FIG. 1, the CMOS image sensor 100 includes an active pixel sensor array 110, an analog-to-digital converter 120 having a CDS structure, a data buffer 130, and a ramp voltage generator. 140, a row driver 150, and a timing controller 160.

FIG. 2 exemplarily shows the configuration of one pixel 112 in the active pixel sensor array 110 and one CDS circuit 122 in the analog-to-digital converter 120 shown in FIG. 1.

One pixel 112 in the active pixel sensor array 110 includes four transistors M11-M14 and one photo-diode PD1. The pixel 112 receives the sensing voltage Va corresponding to the image information sensed by the photodiode PD1 in response to the reset signal RST, the transmission signal TX, and the selection signal SEL. To provide.

The CDS circuit 122 includes a plurality of transistors M21-M31 and capacitors C11-C13. The CDS circuit 122 compares the sensing voltage Va provided from the pixel 112 with the ramp voltage VRAMP provided from the lamp voltage generator 150 shown in FIG. 1, and outputs the signal OUT according to the comparison result. )

However, as shown in FIG. 2, while the selection signal SEL is activated at a high level and the voltage V1 is supplied, the transistors M13 and M14 and the CDS circuit 122 constituting the pixel 112 are provided. Transistors M21 are all turned on. As a result, a current path is formed between the power supply voltage and the ground voltage through the transistors M13, 14, and M21 to increase the current consumption.

It is therefore an object of the present invention to provide an image sensor with reduced power consumption.

(Configuration)

According to an aspect of the present invention for achieving the object as described above, the CMOS image sensor comprises: a pixel sensor array in which a plurality of pixel sensors are arranged in rows and columns, and a plurality of transfer circuits respectively associated with the columns. Include. Each of the pixel sensors receives a ramp voltage, compares a difference between a reset voltage and a pixel signal voltage corresponding to image information input from the outside and the ramp voltage, and outputs a comparison signal. Each of the transfer circuits transmits the comparison signal from an associated pixel sensor to the outside.

In this embodiment, each of the pixel sensors has a first transistor connected between a power supply voltage and a first node, controlled by a reset signal, one end and the other end connected to the first node, and connected to a transmission signal. A second transistor controlled by the second transistor; a photodiode connected between the other end of the second transistor and a ground voltage; a first capacitor connected between a lamp voltage and the first node; and between the first node and the second node. A third transistor connected between the connected second capacitor, the second node and a first output terminal for outputting the sensing signal, and controlled by a first switching signal, and one end and the other end connected to the first output terminal. A fourth transistor controlled by a second selection signal, the other end of the fourth transistor and a ground voltage, And a fifth transistor controlled by the signal.

In this embodiment, each of the transfer circuits includes a sixth transistor connected between a power supply voltage and the first output terminal, a fourth capacitor connected between the first output terminal and a third node, and the fourth capacitor. And an inverter connected between the second output terminal and a seventh transistor connected between the second output terminal and the third node and controlled by a third switching signal.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating the configuration of one pixel sensor 210 and one transfer circuit 220 corresponding to one column provided in the CMOS image sensor according to the exemplary embodiment of the present invention.

The pixel sensor 210 shown in FIG. 3 is one of a plurality of pixels arranged in rows and columns of the active pixel sensor array 110 shown in FIG. 1, and the transfer circuit 220 shown in FIG. One of the transfer circuits, each connected to a plurality of columns, configured in the analog-to-digital converter 120 shown in FIG. 1.

The pixel sensor 210 includes NMOS transistors M31-M35, capacitors C21 and C22, and a photodiode PD2. The drain of the transistor M31 is connected to the power supply voltage VDD, the source is connected to the first node N1, and the gate is controlled by the reset signal RST. The drain of the transistor M32 is connected to the first node N1, the source is connected to the photodiode PD1, and the gate is controlled by the transfer signal TX. Photodiode PD2 is connected between the source of transistor MN32 and ground voltage.

The capacitor C21 is connected between the ramp voltage VRAMP provided from the ramp voltage generator 140 shown in FIG. 1 and the first node N1. The capacitor C22 is connected between the first node N1 and the second node N2.

The transistors M34 and M35 are sequentially connected in series between the third node N3 and the ground voltage, the gate of the transistor M34 is connected to the selection signal RSEL, and the gate of the transistor M35 is connected to the third node N3 and the ground voltage. It is connected to two nodes N2. A drain of the switching transistor M33 is connected to the third node N3, a source is connected to the second node N2, and a gate is connected to the switching signal S1.

The transfer circuit 220 includes PMOS transistors M41-M44, NMOS transistors M45 and M46, and a capacitor C23. The transistors M41 and M42 are sequentially connected in series between the power supply voltage VDD and the third node N3, and are controlled by the voltages V1 and V2, respectively. The capacitor C23 is connected between the third node N3 and the fourth node N4. The transistors M43-M45 are sequentially connected in series between the power supply voltage VDD and the ground voltage. The gate of the transistor M43 is connected to the voltage V1, and the gates of the transistors M44 and M45 are connected to the fourth node N4. Transistors M44 and M45 operate as inverters. The drain of the transistor M46 is connected to the fifth node N5, the source is connected to the fourth node N4, and the gate is controlled by the switching signal S2. The reset signal RST, the transfer signal TX, the selection signal RSEL, and the switching signals S1 and S2 used in the pixel sensor 210 and the transfer circuit 220 shown in FIG. 3 are shown in FIG. 1. From the timing controller 160.

The pixel sensor 210 according to the preferred embodiment of the present invention does not include the transistors M13 and M14 included in the conventional pixel sensor 112 shown in FIG. 2, and the capacitors C21 and C22 and the transistors are not included in the pixel sensor 210. And M33-M35 to receive the ramp voltage VRAMP, and the difference VRST-VSIG between the reset voltage VRST and the pixel signal voltage VSIG corresponding to the image information input from the outside. The lamp voltage VRAMP is compared to output the first output signal OUT1. That is, the CDS operation is performed in each pixel sensor 210. The transfer circuit 220 transfers the first output signal OUT1 output from the pixel sensor 210 as the second output signal OUT2. By not including the transistors M13 and M14 included in the conventional pixel sensor 112 shown in FIG. 2, noise caused by the transistors M13 and M14 may be removed, and the transistors M13 and M14 may be removed. Power consumption can be reduced by eliminating the current path formed by M21).

The operation of the pixel sensor 210 and the transfer circuit 220 having such a configuration will be described with reference to the timing diagram shown in FIG. 4. 4 is a timing diagram of signals used in the pixel sensor shown in FIG. 3. As the reset signal RST is activated to a high level, the voltage VFD of the first node N1 rises to the reset voltage VRST, which is a difference between the power supply voltage VDD and the threshold voltage Vth of the transistor M31. do. When the voltage of the second node N2 becomes higher than the threshold voltage of the transistor M35 through the capacitor C22, the transistor M35 is turned on and the transistor M34 is turned on by the high selection signal RSEL. When turned on, the third node N3 is discharged to the ground voltage. As the switching signal S1 becomes high, the second node N2 is set to the ground voltage, and the transistor M35 is turned off.

When the transfer signal TX is activated to the high level after the reset signal RST transitions to the low level, the voltage VFD of the first node N1 is charged to the capacitor C22 by the photodiode PD2. It is set to the difference VRES-VSIG between the reset voltage VRST and the video signal voltage VSIG corresponding to the image input from the outside, that is, the brightness of the light.

Meanwhile, in the transfer circuit 220, when the levels of the voltages V1 and V2 are set such that the transistors M41-M43 are turned on, the third node N3 is set to the power supply voltage VDD level. At this time, since the transistor M33 is turned off by the low level switching signal S1, the voltage of the node N2 is not affected. In addition, the transistors M44 and M45 are turned on so that the fifth node N5 is set to a low level.

As the transfer signal TX is inactivated to a low level and the ramp voltage VRAMP is increased, when the ramp voltage VRAMP becomes higher than the difference voltage VRES-VSIG charged in the capacitor C22, the transistor M35 is turned on. The first output signal OUT1 that is turned on and output to the third node N3 is discharged to the ground voltage at the power supply voltage VDD level.

As the third node N3 is discharged, the PMOS transistor M45 is turned on, the NMOS transistor M45 is turned off, and the second output signal OUT2 output to the fifth node N5 is at a high level. Is set.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the invention may include various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention as described above, power consumption of the CMOS imaging apparatus is reduced. In addition, since noise generated in the transistors in the pixel sensor is removed, a low noise image sensor is realized.

Claims (5)

A pixel sensor array in which a plurality of pixel sensors are arranged in rows and columns; And A plurality of transfer circuits each associated with said columns; Each of the pixel sensors receives a ramp voltage, compares a difference between a reset voltage and a pixel signal voltage corresponding to image information input from the outside and the ramp voltage, and outputs a comparison signal; Each of said transfer circuits transmits said comparison signal from an associated pixel sensor to the outside. According to claim 1, Each of the pixel sensors, A first transistor coupled between the power supply voltage and the first node and controlled by a reset signal; A second transistor having one end and the other end connected to the first node and controlled by a transmission signal; A photodiode coupled between the other end of the second transistor and a ground voltage; A first capacitor coupled between a ramp voltage and said first node; A second capacitor connected between the first node and a second node; A third transistor connected between the second node and a first output terminal for outputting the sensing signal and controlled by a first switching signal; A fourth transistor having one end and the other end connected to the first output terminal and controlled by a second selection signal; And a fifth transistor coupled between the other end of the fourth transistor and a ground voltage and controlled by a signal of the second node. The method of claim 2, Each of the transfer circuits, A sixth transistor connected between a power supply voltage and the first output terminal; A fourth capacitor connected between the first output terminal and a third node; An inverter connected between the fourth capacitor and a second output terminal; And And a seventh transistor connected between the second output terminal and the third node and controlled by a third switching signal. A pixel sensor configured to output a detection signal corresponding to image information input from the outside; And A transmission circuit for transmitting the sensed signal from the pixel sensor to the outside; The pixel sensor, A first transistor coupled between the power supply voltage and the first node and controlled by a reset signal; A second transistor having one end and the other end connected to the first node and controlled by a transmission signal; A photodiode coupled between the other end of the second transistor and a ground voltage; A first capacitor coupled between a ramp voltage and said first node; A second capacitor connected between the first node and a second node; A third transistor connected between the second node and a first output terminal for outputting the sensing signal and controlled by a first switching signal; A fourth transistor having one end and the other end connected to the first output terminal and controlled by a second selection signal; And a fifth transistor coupled between the other end of the fourth transistor and a ground voltage and controlled by a signal of the second node. The method of claim 4, wherein The transfer circuit, A sixth transistor connected between a power supply voltage and the first output terminal; A fourth capacitor connected between the first output terminal and a third node; An inverter connected between the fourth capacitor and a second output terminal; And And a seventh transistor connected between the second output terminal and the third node and controlled by a third switching signal.

Images