KR101675933B1 - Image Sensor - Google Patents

Abstract

The present invention relates to an image sensor capable of improving a sampling rate of a unit pixel by shortening an output node stabilization time of a pixel portion, the image sensor comprising: a pixel portion for outputting a pixel signal when a pixel control signal is activated; And a sampling rate acceleration unit for discharging the output node of the pixel unit when the pixel control signal is inactivated.

Description

Image sensor

The present invention relates to an image sensor.

2. Description of the Related Art In general, an image sensor of a semiconductor device is a semiconductor device that converts an optical image into an electrical signal. Typical image sensor devices include a charge coupled device (CCD) and a CMOS image sensor. CIS).

Among them, the charge-coupled device is a device in which individual MOS (Metal-Oxide-Silicon) capacitors are located in close proximity to each other and the charge carrier is stored and transferred to the capacitor. The CMOS image sensor has a control circuit and a signal processing (Typically four MOS transistors) corresponding to the number of pixels using a CMOS technology using a signal processing circuit as a peripheral circuit, and sequentially outputs the MOS transistors using the MOS transistors.

1 is a circuit diagram of an image sensor according to a conventional technique.

Referring to FIG. 1, the image sensor 200 includes a plurality of unit pixels, and each unit pixel includes a pixel unit 210, a signal output unit 220, and a current source 230. The pixel unit 210 includes a pixel unit 210 including a photodiode PD, a reset transistor n1, a driving transistor n2, a line selection transistor n3, and a transfer transistor n4. The signal output unit 220 includes a video output transistor n5, a reset output transistor n6, an image capacitor Cs, and a reset capacitor Cr.

Hereinafter, the sampling operation of the image sensor according to the related art will be described with reference to FIG.

When the line selection control signal Ls is activated and the reset control signal Rx and the reset output control signal Rs are also activated, the image sensor 200 outputs a driving voltage VDD through the reset transistor n1, And the drive and line select transistors n2 and n3 output the reset signal rst generated by following the source voltage VDD to the output node out. The reset output transistor n6 then allows the rst node rst to have the same voltage level as the output node out.

Subsequently, when the reset control signal Rx is deactivated, the voltage level of the output node out is gradually lowered by a clock feed-through phenomenon. At this time, the current amount of the current source 230 has a relatively small value of several uA, and the capacitance of the reset capacitor Cr has a large value, so that the charge of the reset capacitor Cr is discharged slowly. As a result, the voltage level of the output node (out) becomes low, so that the reset signal rst has a long signal tail.

For this reason, the stabilization time of the output node (out) becomes relatively long, and accordingly, the following sampling operation also has to be performed for a sufficient time. This problem also occurs in the sampling operation of the image signal sig, so that the sampling rate of the image sensor is lowered as a whole.

Accordingly, it is an object of the present invention to provide an image sensor capable of improving the sampling speed of an image sensor by shortening the output node stabilization time of the pixel portion.

According to an aspect of the present invention, there is provided a pixel unit for outputting a pixel signal when a pixel control signal is activated; And a sampling rate acceleration unit for discharging the output node of the pixel unit when the pixel control signal is inactivated.

The image sensor of the present invention further includes a sampling rate acceleration unit coupled to an output node of the pixel unit and connects the output node to ground when the reset control signal or the transfer control signal is deactivated, By artificially discharging, the stabilization time of the output node of the pixel portion is shortened.

Therefore, the reset signal sampling period and the video signal sampling period are shortened, and the time interval between the different sampling operations can be shortened, so that the sampling rate of the image sensor can be improved as a whole.

1 is a circuit diagram of an image sensor according to a conventional technique.
2 is a signal timing diagram for explaining a sampling method of an image sensor according to a conventional technique.
3 is a circuit diagram of an image sensor according to an embodiment of the present invention.
4 is a detailed circuit diagram of a pulse generator according to an embodiment of the present invention.
5 is a signal timing chart for explaining the operation of the pulse generator according to an embodiment of the present invention.
6 is a signal timing diagram for illustrating a sampling method of an image sensor according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate the understanding of the present invention, the same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

3 is a circuit diagram of an image sensor according to an embodiment of the present invention.

3, the image sensor 300 includes a plurality of unit pixels, and each unit pixel includes a pixel signal having a value corresponding to the driving voltage VDD when the reset control signal Rx is activated, A pixel unit 310 for outputting a pixel signal having a value corresponding to the amount of light stored in the photodiode when the transfer control signal Tx is activated, a pixel unit 310 for outputting a pixel signal when the reset output control signal Rs is activated, A signal output unit 32 for sampling a signal to output a reset signal rst and sampling the pixel signal when the image output control signal Ss is activated to output a video signal sig; A current source 330 providing a drive current I of the pixel portion 310 and a sampling rate acceleration portion 330 discharging the output node out of the pixel portion 310 when the reset control signal Rx or the transfer control signal Tx is deactivated 340), and the like.

For reference, the image sensor 300 generates a reset signal and a video signal in a source follow-up manner, so that the output node OUT has a very high voltage level rise speed while a voltage level drop rate is relatively slow.

Accordingly, the present invention intends to improve the sampling rate of the image sensor as a whole by improving the voltage drop rate of the output node out.

The pixel unit 310 includes a photodiode PD for accumulating photo charges according to the amount of light incident on the pixel unit 310, a driving voltage VDD to the floating diffusion node FD when the reset control signal Rx is activated, A transfer transistor n4 for applying a signal corresponding to the amount of light stored in the photodiode PD to the floating diffusion node FD when the transfer control signal Tx is activated, A driving transistor n2 for source following the voltage of the floating diffusion node FD and an output of the driving transistor n2 to the output node out when the line selection control signal Ls is activated And a line selection transistor n3.

The signal output unit 320 includes a video output transistor n5 for sampling a pixel signal applied to the output node out and outputting a video signal sig when the video output control signal Ss is activated, A reset output transistor n6 for sampling the pixel signal applied to the output node out and outputting a reset signal rst when the reset output control signal Rs is activated, .

The sampling rate accelerating unit 340 includes a pulse generating unit 341 for generating a pulse signal Sp_en in synchronization with the inactivation timing of the reset control signal Rx or the transfer control signal Tx, And a discharging unit n7 for discharging the output node out in response to the control signal Sp_en.

4 is a detailed circuit diagram of a pulse generator according to an embodiment of the present invention.

4, the pulse generator 341 receives a reset control signal Rx, a transfer control signal Tx, and an operation enable signal En_n to perform a logical sum operation, OR), an odd number of inverters D1 to D3 for inverting and delaying the output signal of the first logic gate OR and an odd number of inverters D1 to D3 for outputting the output signal of the first logic gate OR, And a second logic gate (NOR) for receiving the output signal of the first logic gate (D3) and performing a NOR operation to generate the pulse signal Sp_en.

At this time, the operation enable signal En_n may be generated by a control unit (not shown) that generates general timing control signals and addressing signals for selecting each pixel and outputting the sensed video signal. And the signal value varies depending on whether the corresponding pixel unit is activated or not.

Hereinafter, the operation of the pulse generator 341 according to an embodiment of the present invention will be described with reference to FIG.

When either the reset control signal Rx or the transfer control signal Tx is activated, the first logic gate OR outputs a high level signal and the odd inverters D1 to D3 output a low level signal do. The second logic gate (NOR) performs a NOR operation on them and outputs a low-level signal.

When either the reset control signal Rx or the transfer control signal Tx is deactivated again in this state, only the signal of the first logic gate OR shifts to the low level and the second logic gate NOR shifts to the high level .

When the odd number of inverters D1 to D3 output a signal of a high level after a predetermined time (the delay time of the odd number of inverters D1 to D3) has elapsed, the second logic gate NOR becomes low again Level signal.

As a result, the pulse generator 341 of the present invention can generate the pulse signal Sp_en that is clocked in synchronization with the inactivation timing of the reset control signal Rx or the transfer control signal Tx.

Hereinafter, a sampling operation of the image sensor 300 according to an embodiment of the present invention will be described with reference to FIG.

First, the photodiode PD accumulates light charges corresponding to the amount of light incident on the photodiode PD through the photoelectric conversion operation.

When the reset control signal Rx and the reset output control signal Rs are also activated after the line selection control signal Ls is activated in this state, the reset transistor n1 outputs the driving voltage VDD as a floating And the drive transistor n2 and the line select transistor n3 output a signal corresponding to the drive voltage VDD to the output node out.

When the reset control signal Rx is deactivated again after a predetermined time has elapsed, the driving voltage supply is interrupted by the reset transistor n1 and the voltage level of the output node out becomes higher than the voltage level of the signal output part 320 (Cr)) due to the clock feed-draw phenomenon. At this time, the voltage drop rate due to the clock feed-draw phenomenon follows the rate at which the charge of the reset capacitor Cr is discharged in accordance with the amount of current of the current source 330.

However, the present invention further includes a sampling rate accelerator 340 connected to the output node out, thereby artificially discharging the output node out when the line selection control signal Ls is inactivated, thereby shortening the stabilization time of out. At this time, the signal tail of the reset signal becomes shorter than that of the prior art as shown in FIG.

The reset signal sampling period can be shortened by the stabilization time? T of the shortened output node out and the video signal sampling operation after the reset signal sampling operation is also shortened by the stabilization time? T of the shortened output node out. As shown in FIG.

These effects are also exhibited in the video signal sampling period.

When the transfer control signal Tx and the video output control signal Ss are activated instead of the reset control signal Rx and the reset output control signal Rs after the output node out is stabilized by the above operation, A signal corresponding to the amount of light accumulated in the diode PD is transmitted to the output node out through the driving transistor n2 and the line selection transistor n3.

When the transfer control signal Tx is deactivated again after a predetermined time has elapsed, the line selection transistor n3 blocks the supply of the signal corresponding to the amount of light charge.

The voltage level of the output node out is rapidly lowered again by the signal output section 320 (particularly, the image capacitor Cs) and the discharge section n7, and the stabilization time of the output node out at this time is also .

Therefore, the video signal sampling period can be shortened by the stabilization time? T of the shortened output node out and the next sampling operation can be performed earlier than the stabilization time? T of the shortened output node out do.

As described above, according to the present invention, the reset signal sampling period and the video signal sampling period are shortened by using the sampling rate accelerating unit 340, and the time interval between sampling operations which are different from each other can be shortened, .

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

300: unit pixel 310: pixel unit
320: signal output unit 330: current source
340: Sampling rate acceleration part 341: Pulse generation part

Claims (5)

A pixel unit for outputting a pixel signal when the pixel control signal is activated; And
And a sampling rate acceleration unit for discharging the output node of the pixel unit when the pixel control signal is inactivated,
Wherein the sampling rate acceleration unit comprises:
A pulse generator for generating a pulse signal in synchronization with a deactivation time of the pixel control signal; And
And a discharging unit discharging an output node of the pixel unit in response to the pulse signal.
delete Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, wherein the pixel control signal
A reset control signal or a transfer control signal.
Claim 4 has been abandoned due to the setting registration fee. The display device according to claim 3, wherein the pixel portion
And outputs a pixel signal having a value corresponding to the driving voltage when the reset control signal is activated and a pixel signal having a value corresponding to the amount of light stored in the photodiode when the transfer control signal is activated As shown in Fig.
Claim 5 has been abandoned due to the setting registration fee. 5. The method of claim 4,
Further comprising a signal output unit for sampling the pixel signal to output a reset signal when the reset output control signal is activated and outputting a video signal by sampling the pixel signal when the video output control signal is activated, sensor.

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