KR20110139886A - Gate drive circuit of inverter - Google Patents

Gate drive circuit of inverter Download PDF

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Publication number
KR20110139886A
KR20110139886A KR1020100059972A KR20100059972A KR20110139886A KR 20110139886 A KR20110139886 A KR 20110139886A KR 1020100059972 A KR1020100059972 A KR 1020100059972A KR 20100059972 A KR20100059972 A KR 20100059972A KR 20110139886 A KR20110139886 A KR 20110139886A
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KR
South Korea
Prior art keywords
transistor
idle
gate
electrode
electrically connected
Prior art date
Application number
KR1020100059972A
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Korean (ko)
Inventor
이원경
Original Assignee
현대모비스 주식회사
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Application filed by 현대모비스 주식회사 filed Critical 현대모비스 주식회사
Priority to KR1020100059972A priority Critical patent/KR20110139886A/en
Publication of KR20110139886A publication Critical patent/KR20110139886A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/081—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source
    • H02M1/082—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source with digital control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2089—Modifications to facilitate cooling, ventilating, or heating for power electronics, e.g. for inverters for controlling motor

Abstract

The present invention relates to a gate drive circuit of an inverter, wherein an idle is turned off, and a transistor electrically connected between the gate and the emitter of the idle is turned on to conduct the gate and the emitter of the idle, and the gate and collector By storing the ground voltage in the parasitic capacitor in between, and fixing the gate voltage to the ground voltage, it is possible to prevent the idle from being turned on by the noise applied to the gate of the idle.

Description

Gate drive circuit of inverter {GATE DRIVE CIRCUIT OF INVERTER}

The present invention relates to a gate drive circuit of an inverter, and more particularly, through an transistor connected between an gate of an idle and an emitter, an inverter capable of preventing the turning on of the inverter by noise applied to the idle gate. It relates to a gate drive circuit.

In general, one of the main points to design the inverter for controlling the operation of the drive motor of the hybrid vehicle and the electric vehicle is the gate driver design and its manufacturing technology.

Here, the design technology of the gate driver is a technology belonging to the field of power electronics. In general, a method of limiting overvoltage by increasing the gate resistance or using a zener diode during turn-off of an overcurrent or a short circuit accident is generally used.

However, currently used high voltage IGBT gate drive circuits operate in a very high noise environment because the power converter switches power, and the noise must not affect the operation of the circuit.

The general gate drive circuit 1A is a push-pull circuit including a first transistor Q1 and a second transistor Q2 driven on / off by operating by a control signal INs as shown in FIG. 1A. And a resistor R1 for controlling the current applied to the gate of the idle S. As shown in FIG. At this time, the power supplies Vcc1 and Vcc2 applied to the first transistor Q1 and the second transistor Q2 are two separate power supplies, and two power supplies Vcc1 and Vcc2 are driven to drive one idleness S. As a result, the circuit board becomes complicated, and the size becomes large.

In order to prevent this, the gate drive circuit 1B configured as a single voltage source includes a first transistor Q1 and a second transistor (Q1) driven to be turned on / off by operating by a control signal INs as shown in FIG. 1B. A push-pull circuit composed of Q2) and a resistor R1 for controlling the current applied to the gate of the idle S. In this case, the idle S may be driven by the power supply Vcc1 applied to the first transistor Q1. The gate drive circuit maintains the gate voltage at "0", which is a ground voltage, when no power is applied when the idle S is turned off.

However, in the gate drive circuit as described above, even when the idle S is to be turned off, the idle S may be turned on due to a voltage change caused by parasitic capacitance or noise. Due to such abnormal driving, problems such as the temperature of the IGBT element used in the inverter is raised or destroyed and the reliability of the system is lowered.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned conventional problems, and an object of the present invention is to provide an inverter capable of preventing the turning on of the idle when the idle drive is driven through a transistor connected between the gate and the emitter of the idle. It is to provide a gate drive circuit.

In order to achieve the above object, a gate drive circuit of an inverter according to the present invention has a first electrode electrically connected to a first control power supply, and a control electrode is electrically connected to a drive unit, and is operated by a signal applied from the drive unit. A first transistor, a second transistor electrically connected to the second electrode of the first transistor, a control electrode electrically connected to the driving unit, and a second transistor operated by a signal applied from the driving unit; A first resistor electrically connected between the first transistor and the second transistor and a second electrode electrically connected to a gate of the idle, and a second electrode of the first resistor and an emitter of the idle It may include a third transistor electrically connected therebetween.

In the third transistor, a first electrode is electrically connected to a second electrode of the first resistor and a gate of the idle, a second electrode is electrically connected to an emitter of the idle, and a control electrode is connected to the first electrode. It may be electrically connected to the second electrode of the second resistance.

A second electrode may further include a second resistor electrically connected to the driving unit, a control electrode of the first transistor, and a control electrode of the second transistor, and a second electrode of the second transistor may be electrically connected to the control electrode of the third transistor. Can be.

When the idle is turned off, the third transistor may be turned on to fix the gate of the idle to a ground voltage, thereby blocking the operation of the idle by parasitic capacitance between the gate and the cathode of the idle. .

The first transistor may be an N-type transistor, and the second transistor and the third transistor may be a P-type transistor.

In the gate drive circuit of the inverter according to the present invention, the transistor is connected between the gate and the emitter of the idle, so that the idle can be prevented from being turned on during the idle off driving.

1A and 1B are circuit diagrams showing a gate drive circuit of a conventional inverter.
2 is a circuit diagram illustrating a gate drive circuit of an inverter according to an embodiment of the present invention.
3 is a block diagram illustrating a connection relationship between a gate drive circuit and a driving motor of the inverter of FIG. 2.
4 is a timing diagram illustrating a driving waveform of the idleness of FIG. 3.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention. Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals.

2, a gate drive circuit of an inverter according to an embodiment of the present invention is shown.

As shown in FIG. 2, the gate drive circuit 10 of the inverter is driven by receiving a control signal INs applied from the driving unit and controls the large-capacity driving motor M that is a power source of the vehicle. Controlling the voltage applied to the gate electrode of the Insulated Gate Bipolar transistor.

The gate drive circuit 10 of the inverter includes a push-pull circuit for amplification consisting of an N-type first transistor Q1 and a P-type second transistor Q2, and a gate current of the idle S. Is composed of a first resistor (R1) for controlling the voltage, a third transistor (Q3) for fixing the gate voltage of the idle S, and a second resistor (R2) for controlling the base current of the third transistor (Q3). .

First, the first transistor Q1 has the first electrode 1 electrically connected to the first control power supply Vcc1, and the second electrode 2 is electrically connected to the first electrode 1 of the second transistor Q2. It is connected to, and operates by receiving a control signal (INs) applied from the drive unit to the control electrode (3).

In the second transistor Q2, the first electrode 1 is electrically connected to the second electrode 2 of the first transistor Q1, and the second electrode 2 is an emitter of the idle S. It is electrically connected to 2) and is operated by receiving the control signal INs applied from the driver to the control electrode 3.

The first transistor Q1 is an N type, and the second transistor Q2 is a P type, and is a push-pull circuit that operates in reverse by a control signal INs applied from a driver.

In the first resistor R1, the first electrode 1 is electrically connected to the second electrode 2 of the first transistor Q1 and the first electrode 1 of the second transistor Q2. The electrode 2 is electrically connected to the gate 3 of the idle S and the first electrode 1 of the third transistor Q3.

The first resistor R1 controls the current applied to the gate 3 of the idle S.

In the third transistor Q3, the first electrode 1 is electrically connected to the second electrode 2 of the first resistor R1 and the gate 3 of the idle S, and the second electrode 2 is connected to the third electrode Q3. ) Is electrically connected to the emitter 2 of the idle S, and the control electrode 3 is electrically connected to the second electrode 2 of the second resistor R2.

When the third transistor Q3 is turned off, the third transistor Q3 has a voltage of the gate S3 of the idle S due to parasitic capacitance between the collector 1 and the gate 3 of the idle S. This shaking is prevented, and the gate 3 voltage is fixed at OV.

In the second resistor R2, the first electrode 1 is electrically connected to the control electrode 3 of the first transistor Q1 and the control electrode 3 of the second transistor Q2. 2) is electrically connected to the control electrode 3 of the third transistor Q3.

The second resistor R2 controls the current applied to the control electrode 3 of the third transistor Q3.

3, a block diagram in which the gate drive circuit 10 of the inverter of FIG. 2 is connected to the idle S for controlling the operation of the driving motor M is illustrated. Here, the configurations of the gate drive circuit 10A of the first inverter and the gate drive circuit 10B of the second inverter are the same as those of the gate drive circuit 10 of the inverter of FIG. 2.

As shown in FIG. 3, two identities S1 and S2 connected in series control a voltage applied to one of three phases of the driving motor M. FIG. That is, the voltage for each phase of three phases is controlled through six idles S to control driving of the driving motor M. FIG.

As shown in FIG. 3, the first image is driven by the gate drive circuit 10A of the first inverter and the gate drive circuit 10B of the second inverter, respectively, to which the control signals INs1 and INs2 are applied. The bit S1 and the second idle bit S2 are driven. In addition, the operation of the driving motor M is controlled by controlling the voltage applied to one of the three phases of the driving motor M by the driving of the first idle S1 and the second idle S2. .

The operation of the gate drive circuit 10A of the first inverter and the gate drive circuit 10B of the second inverter for controlling the driving of the first idle S1 and the second idle S2 is illustrated in FIG. 4. This will be explained through the driving waveform of.

In the first period T1 of FIG. 4, a first control signal INs1 having a low level is applied to the gate drive circuit 10A of the first inverter from the driver, and a high level is applied to the gate drive circuit 10B of the second inverter. The second control signal INs2 is applied. Therefore, the first idle S1 turns off the voltage S1Vge between the gate 3 and the emitter 2 to zero, and the second idle S2 turns to the gate 3 to control the first control power supply ( Vcc1) is applied, and is turned on while the voltage S2Vge between the gate 3 and the emitter 2 increases.

In the second period T2, the low level second control signal INs2 is applied to the gate drive circuit 10B of the second inverter. Therefore, the second idle S2 is turned off, and the second idle S2 is turned on through the first resistor R1 of the gate drive circuit 10B of the second inverter and the second transistor Q2 turned on. The voltage stored in the parasitic capacitor Cge between the gate 3 and the emitter 1 is discharged. In addition, the third transistor Q3 is turned on to electrically conduct between the gate 3 and the emitter 2 of the second idle S2.

In the third period T3, through the emitter 2 and the gate 3 of the second idle S2 that are turned on and conducting the third transistor Q3, the collector of the second idle S2 ( The voltage of the gate 3 is fixed to '0' by charging the ground GND power supply to the parasitic capacitor Cgc between 1) and the gate 3.

Therefore, even if the first idle S1 is turned on in the fourth period T4, the voltage of the gate 3 of the second idle S2 is fixed to '0', so that the second idle S2 is parasitic. It can be prevented from being turned on by the capacitance.

What has been described above is only one embodiment for implementing the gate drive circuit of the inverter according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Q1; First transistor Q2; 2nd transistor
Q3; Third transistor R1; First resistance
R2; Second resistance S; Ibizity

Claims (5)

A first transistor electrically connected to a first control power source, and a control electrode electrically connected to a driving unit, the first transistor operating by a signal applied from the driving unit;
A second transistor electrically connected to a second electrode of the first transistor, a control electrode electrically connected to the driver, and a second transistor operated by a signal applied from the driver;
A first resistor electrically connected between the first transistor and the second transistor and a second electrode electrically connected to a gate of the idle; And
And a third transistor electrically connected between the second electrode of the first resistor and the emitter of the idle. The method according to claim 1,
In the third transistor, a first electrode is electrically connected to a second electrode of the first resistor and a gate of the idle, a second electrode is electrically connected to an emitter of the idle, and a control electrode is connected to the first electrode. A gate drive circuit of an inverter, electrically connected to a second electrode having two resistors. The method according to claim 1,
A first resistor electrically connected to the driving unit, a control electrode of the first transistor, and a control electrode of the second transistor; and a second resistor electrically connected to the control electrode of the third transistor. The gate drive circuit of the inverter, characterized in that. The method according to claim 1,
When the idle is turned off, the third transistor is turned on to fix the gate of the idle to a ground voltage, thereby preventing the idle from being operated by parasitic capacitance between the gate and the cathode of the idle. A gate drive circuit of an inverter. The method according to claim 1,
The first transistor is an N-type transistor, and the second transistor and the third transistor are P-type transistors.
KR1020100059972A 2010-06-24 2010-06-24 Gate drive circuit of inverter KR20110139886A (en)

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Application Number Priority Date Filing Date Title
KR1020100059972A KR20110139886A (en) 2010-06-24 2010-06-24 Gate drive circuit of inverter

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Application Number Priority Date Filing Date Title
KR1020100059972A KR20110139886A (en) 2010-06-24 2010-06-24 Gate drive circuit of inverter

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KR20110139886A true KR20110139886A (en) 2011-12-30

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105024557A (en) * 2015-08-07 2015-11-04 姚晓武 Power circuit for driving insulted gate bipolar transistor (IGBT)
CN105048790A (en) * 2015-07-22 2015-11-11 深圳市稳先微电子有限公司 Power tube control system and drive circuit for driving external power tube
CN105790554A (en) * 2016-04-06 2016-07-20 杭州电子科技大学 IGBT circuit having dual-isolation characteristic and control method thereof
KR20200058036A (en) * 2018-11-19 2020-05-27 엘지전자 주식회사 Motor driving apparatus and home appliance including the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105048790A (en) * 2015-07-22 2015-11-11 深圳市稳先微电子有限公司 Power tube control system and drive circuit for driving external power tube
CN105048790B (en) * 2015-07-22 2017-12-05 深圳市稳先微电子有限公司 Power tube control system and the drive circuit for driving external power tube
CN105024557A (en) * 2015-08-07 2015-11-04 姚晓武 Power circuit for driving insulted gate bipolar transistor (IGBT)
CN105790554A (en) * 2016-04-06 2016-07-20 杭州电子科技大学 IGBT circuit having dual-isolation characteristic and control method thereof
CN105790554B (en) * 2016-04-06 2018-02-06 杭州电子科技大学 A kind of IGBT drive circuit and control method with dual resisteance
KR20200058036A (en) * 2018-11-19 2020-05-27 엘지전자 주식회사 Motor driving apparatus and home appliance including the same

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