KR20110131041A

KR20110131041A - Embedded pcb and manufacturing method of the same

Info

Publication number: KR20110131041A
Application number: KR1020100050667A
Authority: KR
Inventors: 이민석
Original assignee: 엘지이노텍 주식회사
Priority date: 2010-05-28
Filing date: 2010-05-28
Publication date: 2011-12-06

Abstract

PURPOSE: An embedded printed circuit board and a manufacturing method thereof are provided to reduce process costs by connecting a part to a solder without a separate surface process. CONSTITUTION: A plurality of insulating barriers(121) forms opening on a first metal layer at regular intervals. The first metal layer comprises a circuit pattern(111). An insulating film is formed on the first metal layer. An insulating barrier and the opening in which a first metal layer is exposed are formed by processing the insulating film using laser. Terminals of electronic device chips(140,150) are combined in the opening between the insulating barriers by the media of a solder member. The electronic device chip is buried in the first insulation layer. A second metal layer is included on the top of the first insulation layer. The second metal layer comprises a circuit pattern(191).

Description

Embedded PCB and Manufacturing method of the same {Embedded PCB and Manufacturing method of the same}

The present invention relates to a structure of a component-embedded printed circuit board for mounting an electronic device chip using a solder member and a method of manufacturing the same.

Printed circuit boards are solidifying their status as one of electronic components with the development of semiconductors and electronic devices, and all electric and electronic devices such as radios, televisions, PCS, and various other electrical and electronic products, as well as computers and high-tech electronic equipment. It is widely used as a component for implementing the circuit of. In recent years, as the technological progress in this field becomes remarkable, high quality is required in printed circuit boards, thereby rapidly increasing density. Particularly, in the manufacture of embedded PCB, a metal material such as Au is plated on the part where the component is to be surface-mounted, and for this purpose, masking treatment is performed using a dry film resist (hereinafter referred to as 'DFR'). This is achieved through a process.

One of the most important parts of the embedded technology of the embedded PCB is the high I / O count of the embedded components. This can be expressed as a fine pitch implementation level. For this, most development technologies use vias and / or metal bumps and lands to connect electronic device chips with circuits. Or, it is implemented using a fine pattern circuit technology such as a bonding process using a structure such as solder and solder pad (Solder / Pad).

Referring to FIG. 1, this conceptually illustrates a process of mounting an electronic device chip on a printed circuit board using solder and a solder pad (Solder / Pad) in a conventional buried printed circuit board manufacturing process.

Conventionally, in order to connect the electronic device chip 5 on the inner circuit board on which the insulating layer 1 and the outer metal layers 2 and 2 'and the circuit pattern 3 are implemented, the solder ball pad 6 is shown. ) To form a solder ball (7), and indirectly connected to a part of the circuit pattern (3) of the printed circuit board. Subsequently, the insulation layer 8 is stacked upside down and the outer circuit pattern is implemented 10 or the via hole 11 is plated to complete the circuit.

On the other hand, in the case of a component-embedded board for mounting a chip by applying such a solder member (Solder), the technology of soldering (base) to the base substrate (base) is very important, conventionally Au in the soldering (Soldering) part To make a separate pad (Pa / Ni), or using a metal pattern (Cu Pattern) using a method of using the difference between the wettability (Wettability) of the metal pattern (Cu Pattern) and epoxy (Epoxy). However, solder has the property of implementing wetting on all metals, and the degree varies depending on the surface state and the reactivity with the solder material. However, in the conventional method, a selective method of forming Au / Ni, which is a noble metal, must be performed for selective soldering, which is a process material and a product because the price of gold, a plating material, is expensive. Increasing prices and delaying the process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to form an insulating partition pattern on a first metal layer, and to mount an electronic device chip through an insulating member in the insulating partition to separate surfaces. Since the parts can be connected using solder without treatment, the present invention provides a manufacturing process and a structure according to which the process cost can be greatly reduced and the manufacturing process can be accelerated.

As a means for solving the above problems, the present invention comprises the steps of forming an insulating partition wall spaced a predetermined distance on the first metal layer; It can provide a method for manufacturing a buried printed circuit board comprising a; step 2 of mounting the electronic device chip in the opening region between the insulating partition wall using a solder member.

Particularly, the first step may include forming an insulating film on the first metal layer and laser processing the insulating film to form an opening through which the first metal layer is exposed and an insulating partition wall having a protruding pattern, or an insulating material on the first metal layer. Forming a protrusion pattern by partially printing the ink, or forming a protrusion pattern on the first metal layer, and forming a protrusion pattern through an exposure and development process.

In addition, the insulating partition wall in the above-described process, it may be processed using any one selected from epoxy, phenol resin, prepreg, polyimide film, ABF (Ajinomoto Build up Film), RCC.

In the above-described manufacturing process, the second step may include: a1) forming solder joints by applying solder paste to the opening regions; a2) bonding and reflowing the connection terminal of the electronic device chip to the terminal joining unit; . &Lt; / RTI >

Subsequently, after the step 2, the method may further include a third step of stacking the first insulating layer to bury the electronic device chip and the second metal layer on the first insulating layer.

Further, after the step 3, the method may further include forming a through hole for electrically connecting the first metal layer and the second metal layer, and forming a circuit pattern by patterning the first metal layer and the second metal layer. have.

In addition, after the second step, a second insulating layer having an internal circuit pattern inserted into the first insulating layer, wherein a first insulating layer filling the electronic device chip and a second metal layer are stacked on the first insulating layer. The method further includes a step of stacking layers, and after the step 3, a through hole for electrically connecting the first and second metal layers and the internal circuit pattern is formed, and the first and second metal layers are patterned. It is also possible to implement in a process further comprising four steps of forming a circuit pattern.

The structure of the buried printed circuit board manufactured according to the above-described manufacturing process is as follows.

Specifically, the structure of the buried printed circuit board according to the present invention, a plurality of insulating partitions arranged to form a predetermined gap opening on the first metal layer; And an electronic device chip having a terminal coupled to a solder member formed in the opening region. In particular, the insulating partition wall is formed using an epoxy, a phenol resin, a prepreg, a polyimide film, or an Ajinomoto Build up Film (ABF). Can be. In addition, the solder member is formed in the opening formed by the insulating partition wall, it may be formed to a height greater than the insulating partition wall.

In this case, the mounted electronic device chip may be an active device or a passive device.

In particular, the above-described buried printed circuit board according to the present invention includes a first insulating layer surrounding the electronic device chip, and further includes a second metal layer formed on the first insulating layer. The second metal layer may be embodied in a circuit pattern having conductive holes electrically connected to each other.

Of course, the first insulating layer according to the present invention may be formed in a structure further including an internal circuit pattern in which the first and second metal layers and at least one region are electrically connected. It is, of course, also possible to modify the multilayer structure having at least one or more insulating layers and circuit pattern layers stacked on the second metal layer.

According to the present invention, by forming an insulating partition pattern on the first metal layer and mounting an electronic device chip through the insulating member in the insulating partition, the parts can be connected by soldering without any surface treatment, so that the process cost It is possible to realize the effect of drastically reducing the cost and speeding up the manufacturing process.

1 is a conceptual diagram illustrating a chip mounting method of a conventional buried printed circuit board.
Figure 2a is a flow chart showing a manufacturing process according to the present invention, Figures 2b to 2d shows a process chart according to an embodiment of the present invention.
3 is a process diagram showing a modified embodiment according to the present invention.
Figure 4 shows the structure of a buried printed circuit board according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation according to the present invention. In the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the reference numerals, and duplicate description thereof will be omitted. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The present invention is to provide an economical and reliable process by connecting a chip using solder to an opening in which an insulating partition is formed without additional surface treatment on the first metal layer in mounting the component. .

Specifically, the manufacturing process according to the present invention with reference to Figures 2a to 2c as follows.

The present invention includes a first step of forming an insulating partition spaced at a predetermined interval on the first metal layer and two steps of mounting an electronic device chip using a solder member in an opening region between the insulating partition walls. Steps 1 and 2 may be performed directly on the first metal layer in the process of forming and filling the mounting region of the electronic device chip, but the first metal layer is formed on the carrier board. Can be performed. Hereinafter, the process of the present invention will be described using the process of directly performing the process on the first metal layer as an example. (If there is a carrier board, the process of removing the carrier board later is added. The order is almost the same.)

The above-described process will be described in detail with reference to the presented flowchart and process diagram.

1. Insulation bulkhead and chip mounting process

In the first step, as shown in FIG. 2B, a process of forming the insulating partition 121 on the first metal layer 110 is performed (step S 1). The insulating partition defined in the present invention is defined as a protruding structure that partitions a region (opening 122) separated by the partition structure 121 while the surface of the first metal layer is exposed on the first metal layer 110. The first metal layer may be formed using a material such as Cu, Ag, Sn, Au, Ni, Pd, and the like, and in particular, the first metal layer is formed of Cu as an example.

The process of forming the insulating partition wall 121 is illustrated in FIG. 2C as an example.

As shown in (a) of FIG. 2C, the same structure as the above-described embodiment is a method of forming the structure including the opening 122 and the insulating partition 121. As shown in (b), the first metal layer ( An insulating layer 120 such as epoxy, phenol resin, prepreg, polyimide film, Ajinomoto build up film (ABF), RCC, etc. is formed on the substrate 110 and processed using a laser (L) to form an insulating partition wall ( 121).

Alternatively, as illustrated in (c), the mask M on which the pattern is formed may be disposed on the first metal layer 110, and the insulating partition wall 121 may be implemented through printing.

Alternatively, as shown in (d), the photosensitive material layer 123 is formed on the first metal layer 110 and is insulated using a photolithography method that performs an exposure and development process using an exposure film F or the like. The partition wall 121 may be formed. In an embodiment of the present invention will be described for the manufacturing process that proceeds through the above-described printing process.

Subsequently, in step S 2, the connection structure 130 is formed using a solder member in the opening 122. Thereafter, the connection terminal 130 of the passive element 140 or the active element 150 is connected to the connection structure 130, and the chip is mounted through a reflow process. In particular, the insulating partition wall 121 according to the present invention described above is epoxy, phenolic resin, prepreg, polyimide film, ABF (Ajinomoto Build up Film), RCC, etc. has almost no wetting (wetting) property for the solder, mounting Since the material can exist inside the printed circuit board, no separate removal process is required, so that the solder member for connection can prevent the problem of spreading the wetness characteristic over the partition wall during chip mounting, thereby improving the reliability of the connection. It can be guaranteed.

Thereafter, a lay-up process accompanying a general buried printed circuit board manufacturing process may be performed. The layup process herein means a process of laminating an insulating layer and a metal layer by laminating by heating and pressing. In general, the stacked metal layer is processed to form a circuit pattern, and a process of processing a conductive hole electrically connected between each circuit pattern is included.

As shown in step S3, in the present invention, the first insulating layers 160 and 170 filling the electronic device chips 140 and 150 and the second metal layer 190 are stacked on the first insulating layer. A step of forming the through hole H1 electrically connecting the first metal layer 110 and the second metal layer 190 may be performed. In the present invention, the first insulating layer is formed of an internal circuit pattern 180 made of an internal insulating layer 181 having a circuit pattern 182 in addition to the simple insulating layer. .

In addition, as in step S4 illustrated in FIG. 2D, a process of filling the inside of the through hole with a metal material may be performed. The metal material (H2) to be filled is electroless plating, electroplating, screen printing, sputtering, evaporation of any one selected from Cu, Ag, Sn, Au, Ni, Pd ( Filling may be performed using any one of evaporation, inkjetting, dispensing, or a combination thereof. Thereafter, the first and second metal layers 110 and 190 may be patterned to form circuit patterns 111 and 191. The circuit pattern may be formed using an etching method or an addifive method.

2. Multilayer PCB Implementation Process

The layup process may be repeatedly performed to implement the multilayer PCB on the result of step S4 of the buried printed circuit board according to the present invention.

As shown in FIG. 2D, the insulating layer 210 and the metal layer 220 are further stacked on the circuit patterns 111 and 191, and the process of processing and filling the through hole H3 and processing of the circuit pattern are performed. By proceeding, it is possible to implement a variety of layers of the printed circuit board according to the present invention (P1 ~ P3 step).

A buried printed circuit board manufactured according to the above-described process will be described with reference to the structure shown in FIG. 3.

As shown in (a), the buried printed circuit board according to the present invention includes a plurality of insulating partitions 121 disposed to form a predetermined gap opening on the first metal layer including the circuit pattern 111, The openings between the insulating partition walls 121 have a structure in which terminals 141 and 151 of the electronic device chips 140 and 150 are coupled to each other through the solder member 130. In addition, the electronic device chips 140 and 150 may be filled with a first insulating layer, and the second insulating layer 160 may include a second metal layer including a circuit pattern 191 on the first insulating layer. 170 may be purely formed of an insulating material, but may be formed of a structure including an internal circuit pattern 180 having an internal insulating layer 181 having a separate independent circuit pattern 182 therein. It may be. The internal circuit pattern 182 and the above-described circuit patterns 111 and 191 may include the conductive holes H1 electrically connected to each other, as described above in the manufacturing process.

In particular, the insulating barrier rib 121 is formed using an epoxy, a phenol resin, a prepreg, a polyimide film, or an Ajinomoto Build up Film (ABF), and the solder is connected to a terminal of an electronic device chip between the insulating barrier ribs. The member 130 may be formed to have a height equal to or greater than an insulating partition wall between adjacent insulating partition walls. Of course, in the present invention, the electronic device chip may be applied to either an active device or a passive device or both.

In addition, as shown in (b), it is possible to deform to the structure having at least one additional circuit pattern 221 and the insulating layer 210 in the structure of (a) described above.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical idea of the present invention should not be limited to the embodiments of the present invention but should be determined by the equivalents of the claims and the claims.

110: first metal layer
120: insulation layer
121: insulated bulkhead
130: solder member
140: passive element
150: active element
160: insulation layer
170: insulation layer
180: internal circuit pattern
190: second metal layer

Claims

A step of forming an insulating partition wall spaced at a predetermined interval on the first metal layer;
Mounting an electronic device chip using a solder member in an opening region between the insulating partition walls;
Method of manufacturing a buried printed circuit board comprising a.

The method according to claim 1,
The first step,
Forming an insulating film on the first metal layer, and laser processing the same to form an insulating partition wall through which the first metal layer is exposed and an insulating partition wall having a protrusion pattern.

The method according to claim 1,
The first step,
A method of manufacturing a buried printed circuit board, the step of forming a protruding pattern by partially printing an insulating material on the first metal layer.

The method according to claim 1,
In the first step,
Forming a photosensitive insulating layer on the first metal layer, and forming a protruding pattern through an exposure and development process.

The method according to claim 2 or 3,
The insulating partition wall,
A method of manufacturing a buried printed circuit board processed using any one selected from epoxy, phenol resin, prepreg, polyimide film, Ajinomoto build up film (ABF), and RCC.

The method according to any one of claims 1 to 4,
In the second step,
a1) forming a terminal junction by applying solder paste to the opening region;
a2) bonding and reflowing the connection terminal of the electronic device chip to the terminal joining unit;
Method of manufacturing a buried printed circuit board which is a step comprising a.

The method of claim 6,
After step 2,
3. A method of manufacturing a buried printed circuit board, further comprising: stacking a first insulating layer filling the electronic device chip and a second metal layer on the first insulating layer.

The method according to claim 7,
After step 3,
Forming a through hole electrically connecting the first metal layer and the second metal layer;
The method of claim 1, further comprising forming a circuit pattern by patterning the first metal layer and the second metal layer.

The method of claim 6,
After step 2,
Laminating a first metal layer and a second metal layer on the first insulating layer to fill the electronic device chip,
A method of manufacturing a buried printed circuit board further comprising: stacking a second insulating layer having an internal circuit pattern inserted into the first insulating layer.

The method according to claim 9,
After step 3,
Forming a through hole electrically connecting the first and second metal layers to the internal circuit pattern;
The method of claim 1, further comprising forming a circuit pattern by patterning the first and second metal layers.

A plurality of insulating partition walls disposed to form a predetermined gap opening on the first metal layer;
An electronic device chip having a terminal coupled to a solder member formed in the opening region;
Embedded printed circuit board comprising a.

The method of claim 11,
The insulating partition wall,
A buried printed circuit board formed using epoxy, phenol resin, prepreg, polyimide film, and ABF (Ajinomoto Build up Film).

The method of claim 12,
The solder member,
The buried printed circuit board is formed in the opening formed by the insulating partition wall, and formed to a height greater than the insulating partition wall.

The method of claim 12,
The electronic device chip is a buried printed circuit board which is an active device or a passive device.

The method according to any one of claims 11 to 14,
A first insulating layer surrounding the electronic device chip;
A buried printed circuit board further comprising a second metal layer formed on the first insulating layer.

The method according to claim 15,
The first and second metal layer,
An embedded printed circuit board having a circuit pattern having a through hole electrically connected to each other.

The method according to claim 16,
The first insulating layer,
An embedded printed circuit board further comprising an internal circuit pattern in which the first and second metal layers and at least one region are electrically connected to each other.

18. The method of claim 17,
An embedded printed circuit board further comprising at least one insulating layer and a circuit pattern layer stacked on the first and second metal layers.