KR20110123297A - Wafer level semiconductor package and fabrication method thereof - Google Patents

Abstract

PURPOSE: A wafer level semiconductor package and a manufacturing method thereof are provided to prevent an exfoliation phenomenon and cracks generated on a junction part between different materials of a semiconductor package, thereby improving reliability of the semiconductor package. CONSTITUTION: A first semiconductor chip(110) and second semiconductor chip(210) are connected to each other by a bump(150) in a face-to-face type. A first dielectric layer(120) and second dielectric layer(140) are arranged on the upper surface of the first semiconductor chip. A first redistribution conductive layer(130) is arranged between the first dielectric layer and second dielectric layer. A molding part(300) is arranged between the first semiconductor chip and second semiconductor chip. A third dielectric layer(220) and fourth dielectric layer(240) are arranged on the surface of the molding part.

Description

Wafer Level Semiconductor Package and Manufacturing Method therefor {WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level semiconductor package and a method of manufacturing the same. Specifically, the present invention proposes a light and simple wafer level semiconductor package with improved durability against external impact.

Wafer-level package is a technology that makes a finished product immediately after completing a series of assembly processes such as die bonding, molding, marking, etc., without separating the chips printed on the wafer individually. In addition to reducing the speed of operation, the operation speed is improved, making it suitable for high-speed data processing.

In particular, since the package can be packaged in the same size as a semiconductor chip, more chips can be mounted in a memory module having the same area, making it easier to manufacture a large-capacity memory module.

In addition, semiconductors with wafer-level package technology shorten external connection terminals, which greatly improves the chip's electrical characteristics and heat dissipation characteristics, compared to other packages, thereby reducing overheating caused by high-speed memory products. Innovative improvements are also possible in terms of characteristics and reliability.

1 illustrates a wafer 100 for implementing a wafer level package, and a plurality of semiconductor chips 110 are formed on a top surface of the wafer. Electrical components or other semiconductor chips may be mounted on each semiconductor chip 110 to form a molding, thereby completing a plurality of packages in a single process.

In the case of a semiconductor package in which a plurality of semiconductor chips are stacked on each other, the size and thickness of the package are affected by the substrate. In addition, the larger the thickness of the package, the longer the wiring path from the chip to the external connection terminal, there is a limit to high-speed and large-capacity signal processing.

On the other hand, in a semiconductor package in which a plurality of semiconductor chips are laminated to each other, heterogeneous materials having different physical properties, for example, a junction between a semiconductor chip and a molding material are vulnerable to stress, and are particularly cracked by thermal and mechanical stress from the outer surface or edge of the package. Or peeling occurs. Such cracks or delamination reduce the physical durability of the wafer-level semiconductor package and become more severe as the package becomes lighter and thinner.

SUMMARY OF THE INVENTION The present invention has been made under the foregoing technical background, and an object of the present invention is to prevent cracks and peeling from occurring at the joints between dissimilar materials of a semiconductor package, thereby improving reliability of the package.

Another object of the present invention is to produce a light and simple chip size package at the wafer level.

Still another object of the present invention is to provide a semiconductor package which prevents warpage of a wafer during wafer level processing and improves reliability.

Other objects and technical features of the present invention will be presented in more detail in the following detailed description.

In order to achieve the above object, the present invention provides a semiconductor device comprising: a first semiconductor chip having a first repositioning conductive layer formed thereon, a second semiconductor chip having a smaller size than the first semiconductor chip, and mounted on the first semiconductor chip; A molding part formed on the first semiconductor chip around a second semiconductor chip, electrically connected to the first repositioning conductive layer, and a conductive post passing through the molding part, and formed on an upper surface of the molding part and electrically connected to the conductive post. And a second repositioning conductive layer connected thereto and an external connection terminal electrically connected to the second repositioning conductive layer, wherein a contact interface between the first semiconductor chip and the molding part is formed at an edge of the first semiconductor chip. Provided is a semiconductor package which is extended than other portions.

Preferably, the contact interface between the first semiconductor chip and the molding part at the edge of the first semiconductor chip is formed below the surface of the first semiconductor chip.

Upper surfaces of the first semiconductor chip and the second semiconductor chip may face each other and may be electrically connected to each other by bumps. The edge of the first semiconductor chip may be formed in a stepped structure or an inclined structure, and the molding part is completely filled in the edge so that the interface between the semiconductor chip and the molding part is planar in appearance.

The present invention also provides a wafer including a plurality of first semiconductor chips having a first repositioning conductive layer formed on an upper surface thereof, forming a conductive post on the first semiconductor chip, and forming an edge on the edge of the first semiconductor chip. A continuously indented shape of a moat is formed, a second semiconductor chip is mounted on the first semiconductor chip, a molding part is formed on the first semiconductor chip, and the molding part is polished to expose an upper surface of the conductive post. And forming a second relocation conductive layer electrically connected to the conductive post on the molding unit, and forming an external connection terminal electrically connected to the second relocation conductive layer. Provide a method.

According to the present invention, in the semiconductor package, stress concentrated at the outer edge of the junction between the semiconductor chip and the mold material is dispersed to reduce defects occurring at the interface and the edge. As a result, it is possible to complete a chip size package having excellent physical durability and light weight. In particular, a plurality of packages having excellent reliability can be manufactured by a wafer level process, and warping of the wafer can be suppressed in the manufacturing process.

1 is a plan view showing a wafer level semiconductor package.
2 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.
3 to 9 are flow charts showing a wafer level semiconductor package manufacturing process according to a preferred embodiment of the present invention.
10 is a sectional view of a semiconductor package according to another embodiment of the present invention.
11 is a graph showing the stress distribution test results of the semiconductor package.
12 is a graph showing a stress distribution test result of a semiconductor package according to an embodiment of the present invention.
Figure 13 is a graph showing the stress distribution test results of the semiconductor package according to another embodiment of the present invention.
DESCRIPTION OF THE REFERENCE SYMBOLS
110: first semiconductor chip 115: indentation
150: bump 210: the second semiconductor chip
300: molding part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package by a wafer level process, particularly a system-in-package, and proposes a semiconductor package having a new structure having a step formed along an outer cutting line of a base chip.

2, a wafer level semiconductor package according to a preferred embodiment of the present invention is shown. The semiconductor package includes a first semiconductor chip 110 corresponding to a base chip and a second semiconductor chip 210 electrically connected to and stacked on the first semiconductor chip. The first semiconductor chip 110 and the second semiconductor chip 210 are connected to each other by the bumps 150 in a face-to-face type in which the surfaces (top surfaces) on which the integrated circuits are formed face each other. It is. Unlike shown, the semiconductor package of the present invention may be connected such that the bottom surface of the second semiconductor chip faces the top surface of the first semiconductor chip. In this case, the second semiconductor chip may be mounted on the first semiconductor chip by a die attach method.

The first dielectric layer 120 and the second dielectric layer 140 are formed on the upper surface of the first semiconductor chip 110, and the first repositioned conductive layer 130 is formed between the first dielectric layer 120 and the second dielectric layer 140. ) Is formed. The first reposition conductive layer 130 serves as a wiring for electrically connecting the bump 150 and the first semiconductor chip 110, and also connects the first semiconductor chip 110 to the external connection terminal through the conductive post 160. It acts as a wiring to connect with. When the first repositioning conductive layer 130 is formed, a thin film type passive device (not shown) may be formed between the first dielectric layer 120 and the second dielectric layer 140. This passive element, together with the first semiconductor chip and the second semiconductor chip, constitutes a system in package.

A molding part 300 is formed between the first semiconductor chip 110 and the second semiconductor chip 210 to protect the integrated circuits and various wirings formed on each chip from the outside and simultaneously with the two semiconductor chips 110 and 210. Integrate to form one physical structure. The molding part 300 is formed only by the length of the first semiconductor chip 110 so that the overall package size is limited to the size of the first semiconductor chip. Therefore, a chip size package can be implemented.

The molding part 300 completely covers the second semiconductor chip 210, and is in contact with the first semiconductor chip 110 mainly horizontally (parallel) at the upper surface thereof. However, the edge (part A) of the first semiconductor chip 110 is partially removed, so that the contact surface area is extended at the interface edge between the molding part 300 and the first semiconductor chip 110. In the present embodiment, the first semiconductor chip has a stepped structure formed along the edge, and the molding portion penetrates deeper toward the first semiconductor chip in the stepped portion. The molding part fits tightly in the stepped portion of the edge of the first semiconductor chip to form a rectangular structure and a hexahedral structure in three-dimensional view of the package as a whole. In addition, since the edge of the first semiconductor chip 110 is formed to be stepped, it can be seen that the position of the contact interface is different in the molding portion and the outer portion of the first semiconductor chip compared with other portions. In other words, the contact interface at the edge is moved toward the inside of the chip rather than the wiring (for example, the first repositioning conductive layer) position of the first semiconductor chip.

As such, by increasing the contact area of the first semiconductor and the molding part exposed to the outside in the entire package, the mechanical strength of the package and the durability against external impact may be increased. In addition, by changing the position of the contact interface between the first semiconductor and the molding portion, it is possible to greatly improve the resistance to crack generation and crack propagation. In particular, there is an advantage in that a light and simple semiconductor package can be implemented without using a separate substrate or greatly changing the shape of the molding part.

If the stepped edge A of the first semiconductor chip 110 can increase the contact interface between the first semiconductor chip and the molding part, as described below, for example, a double stepped structure or an inclined structure may be used. May be transformed into

The third dielectric layer 220 and the fourth dielectric layer 240 are formed on the surface of the molding part 300, and the second reposition conductive layer 230 is formed between the third dielectric layer 220 and the fourth dielectric layer 240. It is. The second reposition conductive layer 230 is electrically connected to the conductive post 160, while a part of the second reposition conductive layer 230 is exposed to the surface of the fourth dielectric layer 240 to be electrically connected to the external connection terminal 250. The plurality of external connection terminals 250 are connected to the second relocation conductive layer 230 and are disposed in a fan-out type at the periphery of the second semiconductor chip 210. The molding part 300 may completely cover the second semiconductor chip 210, or may be formed around the second semiconductor chip so that the surface of the second semiconductor chip is exposed to the outside. In this case, the third dielectric layer 220 and the fourth dielectric layer 240 may also be removed from the exposed surface of the second semiconductor chip.

In the semiconductor package according to the present embodiment, since the first semiconductor chip serves as a base chip and does not require a separate substrate, a package having a small thickness and a small size can be implemented. In addition, since the wiring length of the first semiconductor chip and the second semiconductor chip is short, high-speed signal transmission is possible.

Hereinafter, a method of manufacturing a wafer level semiconductor package according to a preferred embodiment of the present invention will be described.

As shown in FIG. 1, a wafer on which a plurality of first semiconductor chips 110 are formed is prepared. A first dielectric layer 120 is formed on an upper surface of the first semiconductor chip, a first reposition conductive layer 130 is formed on the first dielectric layer, and a second dielectric layer 140 is formed on the first relocation conductive layer. Locally expose the relocation conductive layer.

Conductive posts 160 are formed on the upper surface of the first semiconductor chip 110 at the wafer level (FIG. 3). The conductive post 160 is electrically connected to the first reposition conductive layer formed on the upper surface of the first semiconductor chip 110. The conductive posts correspond to metal bumps and serve as electrical passages of the first semiconductor chip 110. The conductive posts 160 may be formed in plural on the upper surface of the first semiconductor chip. Processes such as photoresist, etching and the like for forming the conductive posts are well known to those skilled in the art, and thus detailed descriptions thereof will be omitted.

When the conductive posts 160 are formed, separate structures 162 may be formed simultaneously or sequentially. The structure 162 may be formed around the integrated circuit area of the first semiconductor chip 110 to form a continuous (or discontinuous) ring shape. The structure 162 serves as a barrier to disperse the interfacial stress between the chip and the mold and to break the mold cover region into packaging units when forming a molding part on a large wafer in a wafer level process, thereby preventing warpage of the wafer. Reduce.

Next, an indentation 115 is formed around each unit unit, that is, around the first semiconductor chip 110 at the wafer level (FIG. 4). This indentation is formed in a continuous moat shape around the first semiconductor chip, and is disposed in a lattice pattern when viewed throughout the wafer. The indentation 115 is formed on a scribe lane on the wafer, and may be formed by a method such as mechanical sawing or etching.

Next, the second semiconductor chip 210 is mounted on the first semiconductor chip 110 at the wafer level (FIG. 5). The second semiconductor chip 210 is smaller in size than the first semiconductor chip 110 and is electrically connected to the first reposition conductive layer 130 of the first semiconductor chip 110 through the bump 150. The mounting of the second semiconductor chip may be performed before the indentation is formed.

After the mounting of the second semiconductor chip, the molding part 300 is formed on the first semiconductor chip at the wafer level (FIG. 6). The molding part is filled in the indentation 115 to completely fill the indentation, and covers the second semiconductor chip 210 as a whole to protect it from the outside. After forming the molding part, the upper surface of the molding part is polished to expose the surface of the conductive post 160 (FIG. 7). Through the polishing process, the top surface of the structure 162 or the second semiconductor chip 210 as well as the conductive post may be exposed. The lower surface of the first semiconductor chip 110 may be polished and thinned at the wafer level after the molding part is polished or before polishing.

Next, at the wafer level, a third dielectric layer 220, a second repositioning conductive layer 230, and a fourth dielectric layer 240 are formed on the molding unit 300, respectively (FIG. 8). The second reposition conductive layer 230 is patterned to be electrically connected to the conductive post 160. If necessary, the third dielectric layer 220, the second repositioning conductive layer 230, and the fourth dielectric layer 240 on the upper surface of the second semiconductor chip 210 may be locally removed to expose the surface of the second semiconductor chip to the outside. have. After forming the second relocation conductive layer, a test may be performed for each package at the wafer level to select a good die.

Finally, the external connection terminal 250 is formed to be electrically connected to the second relocation conductive layer 230 at the wafer level, and the individual indentation is completed by cutting the point where the indentation is formed for each package (FIG. 9). The completed package has the same shape as in the embodiment of FIG. A stepped structure is formed around the junction of the first semiconductor chip and the molding part to disperse the stress concentrated on the part, thereby suppressing the interface defect between the chip and the molding.

The back surface of the first semiconductor chip 110 serving as a substrate is exposed to the outside, and thus is easily radiated heat, and has an advantage of being easily coupled with a heat spreader.

Through such a wafer level process, it is possible to manufacture a highly durable and lightweight semiconductor package.

FIG. 10 illustrates a semiconductor package according to another embodiment of the present invention. Unlike the previous embodiment, the contact interface A between the first semiconductor chip 110 and the molding part 300 is inclined at a package edge. It is formed in the form. The inclined contact interface A may be obtained by forming the indentation 115 in a slit or inclined trench structure instead of a rectangular shape in the process of FIG. 4. In this case, the interface area between the first semiconductor chip and the molding part may be increased and the contact position may be changed, thereby improving durability of the package.

11 to 13 are simulation results for testing the durability of the semiconductor package according to the present invention, and FIG. 11 shows stress distribution test results for a package that does not change the contact interface between the first semiconductor chip and the molding part. 12 shows a stress distribution of a package according to the first embodiment related to FIG. 2, and FIG. 13 shows a package according to the second embodiment related to FIG. 10.

It can be seen that the packages according to the embodiment of the present invention have a good stress distribution, and in particular, the stress is reduced at the interface between the chip and the molding part at the edge of the package, thereby providing excellent durability.

The present invention has been exemplarily described through the preferred embodiments, but the present invention is not limited to such specific embodiments, and various forms within the scope of the technical idea presented in the present invention, specifically, the claims. May be modified, changed, or improved.

Claims (11)

A first semiconductor chip having a first repositioning conductive layer formed thereon,
A second semiconductor chip having a smaller size than the first semiconductor chip and mounted on the first semiconductor chip;
A molding part formed on the first semiconductor chip around the second semiconductor chip;
A conductive post electrically connected to the first repositioning conductive layer and penetrating the molding part;
A second reposition conductive layer formed on an upper surface of the molding part and electrically connected to the conductive post;
An external connection terminal electrically connected to the second relocation conductive layer,
The contact interface between the first semiconductor chip and the molding part at the edge of the first semiconductor chip is extended than other portions of the first semiconductor chip.
Semiconductor package. The semiconductor package of claim 1, wherein a contact interface between the first semiconductor chip and the molding part is formed below the surface of the first semiconductor chip at an edge of the first semiconductor chip. The semiconductor package of claim 1, wherein the first semiconductor chip and the second semiconductor chip have upper surfaces facing each other and electrically connected to each other by bumps. The semiconductor package of claim 1, wherein a lower surface of the second semiconductor chip is die attached to an upper portion of the first semiconductor chip. The semiconductor package of claim 1, wherein one surface of the second semiconductor chip is exposed to the outside. The semiconductor package according to claim 1, wherein a thin film type passive element is formed between the first semiconductor chip and the second semiconductor chip. The semiconductor package of claim 1, wherein an edge of the first semiconductor chip is formed in a stepped structure, and a molding part is completely filled in the stepped part. The semiconductor package of claim 1, wherein an edge of the first semiconductor chip is formed to have an inclined structure, and a molding part is completely filled in the inclined portion. Preparing a wafer including a plurality of first semiconductor chips having a first repositioning conductive layer formed on an upper surface thereof;
Forming a conductive post on the first semiconductor chip,
Forming a hat-shaped indentation continuously connected to an edge of the first semiconductor chip,
Mounting a second semiconductor chip on the first semiconductor chip,
Forming a molding part on the first semiconductor chip,
Polishing the molding to expose an upper surface of the conductive post,
Forming a second repositioning conductive layer electrically connected to the conductive post on an upper surface of the molding part,
Forming an external connection terminal electrically connected to the second relocation conductive layer;
Wafer level semiconductor package manufacturing method. 10. The method of claim 9, wherein the indentation portion is formed in a stepped structure. 10. The method of claim 9, wherein the indentation portion is formed in an inclined structure.

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