KR20150107527A - Localized high density substrate routing - Google Patents

Localized high density substrate routing Download PDF

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Publication number
KR20150107527A
KR20150107527A KR1020140030620A KR20140030620A KR20150107527A KR 20150107527 A KR20150107527 A KR 20150107527A KR 1020140030620 A KR1020140030620 A KR 1020140030620A KR 20140030620 A KR20140030620 A KR 20140030620A KR 20150107527 A KR20150107527 A KR 20150107527A
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South Korea
Prior art keywords
electrically conductive
die
circuit element
electrically
pad
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KR1020140030620A
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Korean (ko)
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KR101595216B1 (en
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로버트 스탁스톤
디벤드라 말릭
존 에스 구젝
치아-핀 치우
디팍 쿨카르니
라비 브이 마하잔
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인텔 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

One embodiment of the present invention relates to a system and a method for localized high density substrate routing. According to one or more embodiments, an apparatus includes a medium, first and second circuit elements, an interconnect element, and a dielectric layer. The medium can include low density routing inside. The interconnect element can be buried in the medium and include a plurality of electrically conductive members inside. The electrically conductive members can be electrically connected to the first and second circuit elements. The interconnect element can include high density routing inside. The dielectric layer can be mounted on an interconnect die and include the first and second circuit elements penetrating the dielectric layer.

Description

Localized high density substrate routing {LOCALIZED HIGH DENSITY SUBSTRATE ROUTING}

The present invention relates generally to electronic chip architectures.

A semiconductor device, such as an electronic device, may include substrate routing having a lower density than a portion of routing in a chip attached to the substrate. Such a device may include a particularly complex routing scheme in an area where the attached chip includes a higher density of routing than the routing of the substrate.

FIG. 1 illustrates an example of an apparatus that includes localized high density substrate routing in accordance with one or more embodiments.
Figure 2 illustrates an example of a high-density interconnect element in accordance with one or more embodiments.
FIG. 3 illustrates an example of another apparatus that includes localized high density substrate routing in accordance with one or more embodiments.
4 illustrates an example of a technique for fabricating an apparatus having localized dense substrate routing in accordance with one or more embodiments.
5 illustrates an example of an electronic device according to one or more embodiments.

The following description and drawings fully illustrate specific embodiments in order to enable those skilled in the art to practice the specific embodiments. Other embodiments may incorporate structural, logical, electrical, process, or other changes. Portions and features of some embodiments may be included or substituted in portions and features of other embodiments. The embodiments disclosed in the claims include all the possible equivalents of these claims.

Embodiments of systems and methods for localized dense substrate routing are described generally herein. In one or more embodiments, an apparatus includes a medium, first and second circuit elements, one or more interconnect elements, and a dielectric layer. The medium may include low density routing therein. The interconnect element may be embedded in the medium and may include a plurality of electrically conductive members therein, and the electrically conductive member of the electrically conductive members may be electrically connected to the first circuit element and the second circuit element. The interconnect element may include high density routing therein. The dielectric layer may be on the interconnect element and the dielectric layer may include first and second circuit elements therethrough.

A substrate solution can be used to provide chip-to-chip interconnect. The I / O (Input / Output) density of the package substrate can be determined by the minimum trace and spatial dimensions of the substrate. The minimum trace and spacing dimensions may be limited by the resolution of the lithography and plating process used in the substrate manufacturing process (s). This limitation may be a function of the economic cost to achieve resolution. The routing density in the multi-chip substrate may be approximately 100 times less than the routing density of the chip level routing process. Problems associated with using lower routing densities may include a wider area of the substrate dedicated to I / O and reduced system and power performance.

The problems associated with prior multi-chip package substrates may be that they do not take advantage of chip level routing density for substrate routing in a cost-effective or manufacturing-friendly manner. Solutions to this problem include using high density interconnect elements (e.g., interconnect dies or interconnect chips) that include chip level routing (e.g., high density routing) embedded in a medium . This solution can be used to modify a localized high-density routing element or package design that allows a localized high bandwidth (e.g., density) chip-to-chip interconnect to be created, And to add functionality that can benefit from a large-chip interconnect. In addition, such a solution can provide a high density interconnect only where the high density interconnect is useful, so that the high density interconnect is less expensive and less expensive to be used in conventional package routing (e.g., low density routing) And a plating process. This solution also allows for the dimensional variation in the arrangement of the high-density interconnect elements when the interconnect elements are embedded at or below the N-1 layer (e.g., the layer below the top layer of the substrate (N layer) Can be provided. In an embodiment that includes more than one interconnect element, the alignment of one interconnect element may depend on other interconnect elements. Embodiments that include a high density interconnect buried beneath the top layer of the substrate may incorporate package core routing and high bandwidth interconnect routing into a single imaged bump field on the substrate for subsequent chip attachment. Also, this solution can provide that the chips are routed differently and perhaps more economically. High bandwidth interconnect routing can be isolated to the portion of the chip at or near the location where the high bandwidth interconnect couples physically occur, leaving the remainder of the chip space for low density routing. By including pads on the interconnector element that are sized or shaped to be larger than circuit elements (e.g., electrically conductive vias), variations in the placement of circuit elements can be tolerated.

FIG. 1 illustrates an example of an apparatus 100 that may include localized high density substrate routing. Apparatus 100 includes a substrate 102A that includes a substrate 102A, one or more high density interconnect elements 104, an optional dielectric layer 108, one or more first circuit elements 110A, one or more second circuit elements 110B, 122, or one or more dies 114A-B.

Medium 102A may include low density interconnect routing therein. The medium 102A may be a substrate such as a semiconductor substrate (e.g., silicon, gallium, indium, germanium, or a variation or combination thereof in other substrates), FR-4, polytetrafluoroethylene (Teflon), cotton- One or more insulating layers such as glass-reinforced epoxy such as CEM-3, phenol-glass (G3), paper-phenol (FR-1 or FR-2), polyester- such as glass, or any combination thereof, that can be used in a circuit board. Media 102A may be fabricated using a bumpless buildup layer process (BBUL) or other technique to create media 102A. The BBUL process includes one or more buildup layers formed below elements such as the high-density interconnect element 104 or the die 114. A micro-via formation process, such as laser drilling, can form a connection between the build-up layer and the die or die bond pad. The build-up layer may be formed using a high-density integrated patterning technique. The die or die 114 and the high-density interconnect element 104 may be embedded in a substrate, or may be electrically connected using a BBUL or other process.

The high-density interconnect element 104 may include a plurality of electrically conductive members 106 arranged, disposed, formed, or otherwise disposed within the same. The electrically conductive member 106 may be made of any material that may be possible with conventional substrate routing techniques, such as using a die routing technique to create a high density interconnect element 104 (e.g., Density interconnect element 104 with a gap between the electrically conductive members 106 that may be smaller (e.g., about 100 times smaller) than the electrically conductive members 106 (which may include high density substrate routing). The high density interconnect element 104 may be a semiconductor die such as a silicon die. The high-density interconnect element 104 may comprise a layer of at least one glass, ceramic, or organic material.

3, the high-density interconnect element 104 may be placed in the medium 102A at a layer below the surface (e.g., N-layer or below) (E. G., N layer). ≪ / RTI >

As shown in Figure 2, the high-density interconnect element 104 may be formed on the high-density interconnect element 104, or at least a portion thereof, such as on at least a portion thereof on or above the top surface 226 of the high- And an electrically conductive pad 224 disposed on the top surface of the substrate. As shown in FIG. 2, the electrically conductive pad 224 may be electrically connected between the electrically conductive member 106 and the circuit elements 110A-B. The electrically conductive pad 224 may comprise a conductive metal such as copper, gold, silver, aluminum, zinc, nickel, brass, bronze, The electrically conductive pads 224 (e.g., the high density electrically conductive pads 224) may include a footprint having an area that is larger than the corresponding footprint area of the circuit element 110. This configuration may allow variations in dimensions in manufacturing or in placing the high-density interconnect element 104 in the medium 102. The electrically conductive pad 224 may include a footprint that is circular, square, rectangular, triangular, or a combination thereof. 50㎛ as the electrically conductive pad (224) including a footprint dimension, such as circular, electrically conductive pad 224 having a square or footprint area of approximately 2 1963㎛ having a footprint area of approximately 2 2500㎛ , The footprint area of the electrically conductive pad 224 may be between approximately 175 μm 2 and 10,000 μm 2 . In some embodiments, the electrically conductive pad 224 may include a footprint area between approximately 1900 μm 2 and 2550 μm 2 .

A dielectric layer 108 may be laid over the high-density interconnect element 104 (an example of the lower boundary of the dielectric layer 108 is represented by the horizontal dotted line of the medium 102A). The dielectric layer 108 may include a circuit element 110 therethrough. The inclusion of the dielectric layer 108 may help to allow variations in dimensions in placement, embedding, or otherwise placing the high-density interconnect elements 104 on or at least partially within the medium 102A. The dielectric layer 108 may comprise an oxide or other material, such as an insulating material.

The high-density interconnect element 104 may include interconnection circuitry, such as first and second circuit elements 110A-B, which may be a high-density circuit element 110. [ The circuit elements 110A-B are formed by electrically connecting the high density electrically conductive pads 224A-B of the die 114A-B to the high density electrically conductive pads 224 of the high density interconnect element 104 As well as to electrically connect the electrically conductive member 106, as shown in FIG. Circuit elements 110A-B may be electrically conductive vias. 30㎛ approximately the footprint dimension as the circuit element 110 comprising a substantially square circuit element (110 having a substantially circular shape or footprint area of approximately 2 900㎛ having a footprint area of approximately 2 707㎛ ), circuit elements (such as 110) may include a footprint area of approximately between 2 and 175㎛ 3,600㎛ 2. In some embodiments, the circuit element 110 may comprise a footprint area of approximately between 2 and 600㎛ 1,000㎛ 2.

One or more dies 114A-B may be laid over the media 102. [ Dies 114A-B may be electrically connected to circuit elements 110A-B via electrically conductive adhesive 112, such as solder, tape, glue, or other electrically conductive adhesive. The electrically conductive adhesive 112 may be applied to the first die 114A by placing a high density electrically conductive pad 224A on or at least partially within the first die 114A on the second die 114B, The first die 114A may be electrically connected to the second die 114B, such as by electrically connecting the second die 114B to the second die 114B. The first or second die 114A-B may be logic, memory, central processing unit (CPU), graphics, radio, or any other type of die or package. The electrically conductive pads 224 of the high density interconnect element 104 may be placed between the circuit elements 110 and the ends 238A-B of the electrically conductive member 106. [

The first and second die 114A-B may include a low-density interconnect pad 328 that may be used for power, ground, or other electrical connection thereto. The low density interconnect pads 328 may be electrically coupled to the bus 120, such as a power supply, ground, or data bus, such as through a low density interconnect element 118. The low density interconnect pads 328 may be electrically connected to the electrically conductive pads 332, such as through a conductive adhesive 116. Conductive adhesive 116 may be a microball, such as a microball, configured for solder (e.g., solder paste), electroplating, or a flip chip interconnect (e.g., a collapsed controlled chip connection (C4) interconnect).

The adhesive layer 122 may be operable to prevent the conductive adhesive 116 from bridging between the conductors, such as to help prevent short circuits. The adhesive layer 122 may be a solder resist (e.g., solder mask), an electrically conductive glue resist, a silica loaded capillary bottom filler, or other type of insulator operable to prevent bridging between conductors. The adhesive layer 122 may be placed over the dielectric layer 108 and then selectively removed to at least partially expose the circuit element 110 or the electrically conductive pad 332 or 224; The adhesive layer 122 may be selectively placed over the dielectric layer 108 such that the electrically conductive elements such as the circuit elements 110 are not completely covered by the adhesive layer 122. [ The adhesive layer 122 may be applied at the edge of the die 114 or at the edge of the die 114, such as by using pneumatic or capillary action, such as to at least partially fill the space between the conductors under the die 114. [ May be dispensed near or under the die 114.

Figure 2 shows an example of variation in dimensions in the arrangement of the first and second circuit elements 110 or the high-density interconnect element 104. [ Density electrical conductive pad 224 including a high density electrically conductive pad 224 that includes a footprint area that is greater than the footprint area of the circuit element 110 connected thereto. 110 may be formed, or some error in the placement of the high-density interconnect element 104 may be tolerated.

The high-density interconnect element 104 may simultaneously electrically couple more than two dies 114, such as a CPU die coupled to one or more of memory, logic, graphics or other CPU die, or other types of die.

FIG. 3 illustrates an example of an apparatus 300 that may include a high-density interconnect element 104 on the upper layer of medium 102B. In such an embodiment, the high-density interconnect element 104 may be held in place through an adhesive layer 334, such as a solder layer. The adhesive layer 334 may attach the high density interconnect element 104 to a selective metal pad 336, such as a copper pad, or it may be attached directly to the medium 102B. The metal pad 336 may serve as a stop layer for the laser to remove through the adhesive layer 334, such as to stop the laser from penetrating into the medium 102B. This configuration may allow for better control in the placement or attachment of the high-density interconnect element 104. [

FIG. 4 illustrates an example of a technique 400 for fabricating a device that may include a high-density interconnect element 104. At 402, the high density interconnect element 104 may be embedded in the medium 102. The high-density interconnect element 104 may include one or more electrically conductive members 106. At 404, the dielectric layer 108 may be deposited over the high-density interconnect element 104. At 406, the circuit element 110 may be electrically coupled to the high-density interconnect element 104, such as electrically connecting two circuit elements 110A-B to one another.

An example of an electronic device using one or more high-density interconnect element (s) 104 is included to illustrate an example of a device application for the present invention. FIG. 5 illustrates an example of an electronic device 500 incorporating one or more high-density interconnect element (s) 104. The electronic device 500 is just one example of a device in which embodiments of the present invention may be used. Examples of electronic device 500 include, but are not limited to, personal computers, tablet computers, supercomputers, servers, telecommunication switches, routers, mobile telephones, personal data assistants, MP3 or other digital music players, But is not limited thereto. In this example, the electronic device 500 includes a data processing system that includes a system bus 502 that connects various components of the system. The system bus 502 provides a communication link between the various components of the electronic device 500 and may be implemented as a single bus, as a combination of buses, or in any other suitable manner.

The electronic assembly 510 is connected to the system bus 502. The electronic assembly 510 may comprise a circuit or a combination of circuits. In one embodiment, the electronic assembly 510 includes a processor 512 that may be of any type. As used herein, the term "processor" may refer to a microprocessor, microcontroller, complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, (digital signal processor), a multicore processor, or any other type of processor or processing circuitry, but is not limited thereto.

Other types of circuitry that may be included in the electronic assembly 510 may be used for use in wireless devices such as, for example, mobile telephones, pagers, personal digital assistants, portable computers, two-way radios, A dedicated circuit such as one or more circuits (such as communication circuitry 514), an application-specific integrated circuit (ASIC), and the like. The IC may perform any other type of function.

The electronic device 500 may include an external memory 520 and the external memory may in turn include a main memory 522 in the form of a random access memory (RAM), one or more hard drives 524, and / ), DVD (digital video disk), and the like, as well as one or more memory elements suitable for a particular application, such as one or more drives.

The electronic device 500 may also include a display device 516, one or more speakers 518, and a keyboard and / or controller 530, which allows a system user to enter information into the electronic device 500 A trackball, a touch screen, a voice-recognition device, or any other device that enables a user to receive and receive information from the device.

Additional comments and examples

In Example 1, the apparatus includes a medium that includes low density interconnect routing therein.

In Example 2, the apparatus of Example 1 includes a first circuit element and a second circuit element.

In example 3, at least one of the examples 1 and 2 includes an interconnect element.

In Example 4, at least one of the interconnect elements of Examples 1 to 3 is embedded in the medium.

In Example 5, at least one of the interconnect elements of Examples 1 to 4 contains high density substrate routing therein.

In Example 6, at least one of the interconnect elements of Examples 1 to 5 includes a plurality of electrically conductive members.

In Example 7, the electrically conductive member among the plurality of electrically conductive members of at least one of Examples 1 to 6 is electrically connected to the first circuit element and the second circuit element.

In example 8, at least one of the examples 1 to 7 comprises a dielectric layer, the dielectric layer is above the interconnect die, and the dielectric layer comprises first and second circuit elements passing therethrough.

In Example 9, at least one of Examples 1 to 8 is a substrate.

In Example 10, at least one of Examples 1 to 9 is a semiconductor (e.g., silicon) substrate.

In Example 11, at least one of the interconnect elements of Examples 1 to 10 is an interconnect die.

In Example 12, at least one of Examples 1 to 11 is a first die.

In Example 13, at least one of the dies of Examples 1 to 12 is electrically connected to the first circuit element.

In Example 14, at least one of the first die to the thirteenth die is placed on the medium.

In Example 15, at least one of Examples 1 to 14 comprises a second die.

In Example 16, at least one of the dies of Examples 1 to 15 is electrically connected to the second circuit element.

In Example 17, at least one of the dies of Examples 1 to 16 is placed on the medium.

In Example 18, the first die of at least one of Examples 1 to 17 is a logic die.

In Example 19, at least one of the dies of Examples 1 to 18 is a memory die.

In Example 20, at least one of the first circuit elements of Examples 1 to 19 is a first electrically conductive via.

In Example 21, at least one of the second circuit elements of Examples 1 to 20 is a second electrically conductive via.

In Example 22, at least one of the first electrically conductive vias of Examples 1 to 21 is electrically connected to the first pad.

In Example 23, the first pad of at least one of Examples 1 to 22 is on, or at least partially within, the upper surface of the interconnect die.

In Example 24, at least one of the first to eighth pads is laid between (1) the first electrically conductive via and (2) the first end of the electrically conductive member.

In Example 25, at least one of the second circuit elements of Examples 1 to 24 is electrically connected to the second pad.

In Example 26, the second pad of at least one of Examples 1 to 25 is on, or at least partially inside, the upper surface of the interconnect die.

In Example 27, the second pad of at least one of Examples 1 to 26 is laid between (1) the second electrically conductive via and (2) the second end of the electrically conductive member.

In Example 28, the first pad of at least one of Examples 1 to 27 includes a footprint dimension of 50 micrometers.

In Example 29, the first circuit element of at least one of Examples 1 to 28 comprises a footprint dimension of about 30 micrometers.

In Example 30, at least one of Examples 1 to 29 comprises an adhesive.

In Example 31, at least one of the adhesives of Examples 1 to 30 is a solder resist.

In Example 32, at least one of the adhesives of Examples 1 to 31 is on the dielectric layer.

In Example 33, at least one of the adhesives of Examples 1 to 32 does not completely cover the first and second circuit elements.

In Example 34, at least one of Examples 1 to 33 may be placed in a package.

In Example 35, at least one of the first die to the fourth die is electrically connected to the second die through the first electrically conductive via and the second electrically conductive via.

In Example 36, the second pad of at least one of Examples 1 to 35 includes a footprint having a dimension of 50 micrometers.

In Example 37, at least one of the second circuit elements of Examples 1 to 36 comprises a footprint having a dimension of approximately 30 micrometers.

In Example 38, at least one of the interconnect elements of Examples 1 to 37 is a silicon interconnect die.

In Example 39, the method includes embedding high density interconnect element 104 in media 102.

In Example 40, at least one of Examples 1 to 39 includes electrically connecting the first and second circuit elements 110 to the electrically conductive member 106 of the interconnect element.

In Example 41, the method of any one of Examples 1 to 40 includes placing a dielectric layer 108 over the interconnect element.

In Example 42, the method of any one of Examples 1 to 41 includes placing a first die 114A on a medium.

In Example 43, the method of any one of Examples 1 to 42 comprises electrically connecting the first die to the first circuit element.

In Example 44, the method of any one of Examples 1 to 43 includes placing a second die 114B on the medium.

In example 45, at least one of examples 1 to 44 comprises electrically connecting a second die to a second circuit element.

In Example 46, laying the first die on at least one of the media of Examples 1 to 45 includes placing a logic die on the substrate.

In Example 47, placing the second die on at least one of the substrates of Examples 1 to 46 includes placing a memory die on the substrate.

In Example 48, electrically connecting at least one of the first and second circuit elements of Examples 1 to 47 includes electrically connecting the first and second electrically conductive vias to the electrically conductive member.

In Example 49, the method of any one of Examples 1 to 48 includes placing a first pad on, or at least partially within, the upper surface of the interconnect element.

In Example 50, laying the first pad of at least one of Examples 1 to 49 includes placing a first pad between (1) the first electrically conductive via and (2) the first end of the electrically conductive member .

In Example 51, electrically connecting at least one of the first and second electrically conductive vias of Examples 1 to 50 includes electrically connecting the first electrically conductive via to the first pad.

In Example 52, at least one of Examples 1 to 51 includes placing a second pad on the top surface of the interconnect element or at least partially within the top surface thereof.

In Example 53, laying the second pad includes placing a second pad between (1) the second electrically conductive via and (2) the second end of the electrically conductive member.

In Example 54, electrically connecting at least one of the first and second electrically conductive vias of Examples 1 to 53 includes electrically connecting the second electrically conductive via to the second pad.

In Example 55, laying out the first pad of at least one of Examples 1 to 54 includes placing a first pad comprising a footprint dimension of about 50 micrometers.

In Example 56, electrically connecting at least one of the first and second circuit elements of Examples 1 to 55 includes electrically connecting the first circuit element comprising a footprint dimension of approximately 30 micrometers do.

In Example 57, the method of any one of Examples 1 to 56 includes placing the adhesive layer 122 over the dielectric layer.

The foregoing description of the embodiments includes references to the accompanying drawings that form a part of the description of the embodiments. The drawings illustrate specific embodiments in which the invention may be practiced in the illustrative manner. Such an embodiment is also referred to herein as "YES ". These examples may include elements other than those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. The inventors have also found that for certain examples (or one or more aspects thereof), or for other examples (or one or more aspects thereof) shown or described herein, Consider also examples using any combination or permutation.

In this document, the term " a or an " as used in the patent document is used to include one or more than one of "at least one" or "at least one" independent of any other example or usage. In this document, the term "or" is used to denote that "A or B" is non-exclusive to include "A but not B," B "and" A and B " . In this document, the terms " including "and " in which" are used as " comprising "and" . Also, in the claims that follow, the terms "comprises" and "comprising" are open-ended, that is, systems, devices, products, compositions, . ≪ / RTI > Also, in the following claims, terms such as "first "," second ", and "third" are used merely as indicia and are not intended to impose numerical requirements on the object.

The foregoing description is illustrative and not restrictive. For example, the above-described example (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art that have reviewed the above description. The abstract is provided to comply with 37 C.F.R. § 1.72 (b), which allows the reader to quickly ascertain the nature of the technical specification. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above description of the embodiments, various features may be grouped together to simplify the present invention. This should not be interpreted as intended to imply that the claimed features which are not claimed are essential to any claim. Rather, the inventive subject matter may be less than all features of the specific embodiments disclosed. Accordingly, the following claims are hereby incorporated into the description of the embodiments, with each claim being on its own as a separate embodiment, and such embodiments are contemplated as being capable of being combined with one another in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (24)

A medium comprising a low density interconnect routing therein,
A first circuit element and a second circuit element,
An interconnect element comprising a plurality of electrically conductive members, wherein one of the plurality of electrically conductive members is embedded in the medium, wherein the electrically conductive member comprises a plurality of electrically conductive members, 2 electrically connected to circuit elements - and,
And a dielectric layer overlying the interconnect element, the dielectric layer including the first circuit element and the second circuit element therethrough
Device.
The method according to claim 1,
A first die electrically connected to the first circuit element, the first die on the medium,
And a second die electrically connected to the second circuit element,
Device. 3. The method of claim 2,
The first die is a logic die,
The second die is a memory die
Device.
The method according to claim 1,
Wherein the first circuit element is a first electrically conductive via and the second circuit element is a second electrically conductive via
Device.
5. The method of claim 4,
Wherein the first electrically conductive via is electrically connected to the first pad and the first pad is on or at least partially within the top surface of the interconnect element, A conductive via and an electrically conductive member disposed between the conductive via and the first end of the electrically conductive member
Device.
6. The method of claim 5,
The second electrically conductive via is electrically connected to the second pad and the second pad is on or at least partially within the upper surface of the interconnect element and the second pad is electrically connected to the second electrically conductive via And a second end of the electrically conductive member
Device.
The method according to claim 1,
And a solder resist on the dielectric layer, the solder resist not completely covering the first circuit element and the second circuit element
Device.
Embedding an interconnect die comprising an electrically conductive member in a substrate;
Electrically connecting the first circuit element and the second circuit element to the electrically conductive member,
Placing a dielectric layer over the interconnect die
Way. 9. The method of claim 8,
Placing a first die on the substrate,
Electrically connecting the first die to the first circuit element,
Placing a second die on the substrate,
And electrically connecting the second die to the second circuit element
Way.
10. The method of claim 9,
Wherein placing the first die on the substrate comprises placing a logic die on the substrate,
Wherein placing the second die on the substrate comprises placing a memory die on the substrate
Way.
9. The method of claim 8,
Wherein electrically connecting the first circuit element and the second circuit element comprises electrically connecting a first electrically conductive via and a second electrically conductive via to the electrically conductive member
Way.
12. The method of claim 11,
Placing a first pad on, or at least partially within, the upper surface of the interconnect die; (1) between the first electrically conductive via and (2) the first end of the electrically conductive member; And,
Wherein electrically coupling the first electrically conductive via and the second electrically conductive via comprises electrically coupling the first electrically conductive via to the first pad
Way.
13. The method of claim 12,
Placing a second pad on or at least partially within the upper surface of the interconnect die; and (2) placing the second pad between the second electrically conductive via and (2) the second end of the electrically conductive member. And,
Wherein electrically coupling the first electrically conductive via and the second electrically conductive via comprises electrically coupling the second electrically conductive via to the second pad
Way.
9. The method of claim 8,
Placing a solder resist over the dielectric layer
Way.
As a package,
A first die and a second die,
A substrate;
A first electrically conductive via and a second electrically conductive via,
An interconnect die embedded in the substrate and including an electrically conductive member buried therein, the interconnect die having a first electrically conductive pad and a second electrically conductive pad on the top surface of the interconnect die, Wherein the electrically conductive member is electrically connected to the first electrically conductive via via the first electrically conductive pad and electrically coupled to the second electrically conductive via via the second electrically conductive pad,
A dielectric layer over the interconnect die, the dielectric layer comprising the first electrically conductive via and the second electrically conductive via penetrating therethrough,
The first die is electrically connected to the second die via the first electrically conductive via and the second electrically conductive via
package.
16. The method of claim 15,
The first die is a logic die, and the second die is a memory die
package.
16. The method of claim 15,
Wherein both the first pad and the second pad include a footprint having a dimension of 50 micrometers and both the first electrically conductive via and the second electrically conductive via have a foot having a dimension of 30 micrometers Including print
package.
16. The method of claim 15,
And a solder resist on the dielectric layer,
Wherein the solder resist does not cover the first electrically conductive via and the second electrically conductive via
package.
A semiconductor substrate;
A first circuit element and a second circuit element,
A silicon interconnect die embedded in the semiconductor substrate and including an electrically conductive member, the electrically conductive member electrically connected to the first circuit element and the second circuit element;
And a dielectric layer over the silicon interconnect die, the dielectric layer including a dielectric layer comprising the first circuit element and the second circuit element therethrough
Device.
20. The method of claim 19,
A first die electrically connected to the first circuit element, the first die on the substrate,
And a second die electrically connected to the second circuit element,
Device.
21. The method of claim 20,
The first die is a logic die,
The second die is a memory die
Device.
20. The method of claim 19,
Wherein the silicon interconnect die comprises a first electrically conductive pad on or at least partially within an upper surface of the silicon interconnect die and the first electrically conductive pad is electrically connected to the first circuit element, 1 < / RTI > electrically conductive pad comprises a footprint dimension of about 50 micrometers
Device.
20. The method of claim 19,
Wherein the first circuit element comprises a footprint dimension of approximately 30 micrometers
Device.
20. The method of claim 19,
And a solder resist on the dielectric layer,
Wherein the solder resist does not cover the first circuit element and the second circuit element
Device.
KR1020140030620A 2014-03-14 2014-03-14 Localized high density substrate routing KR101595216B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110233764A1 (en) * 2010-03-29 2011-09-29 Hsiao-Chuan Chang Semiconductor device package and method of fabricating the same
KR20110123297A (en) * 2010-05-07 2011-11-15 주식회사 네패스 Wafer level semiconductor package and fabrication method thereof
KR20120014099A (en) * 2010-08-06 2012-02-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Flip chip substrate package assembly and process for making same
KR20130007049A (en) * 2011-06-28 2013-01-18 삼성전자주식회사 Package on package using through silicon via technique

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110233764A1 (en) * 2010-03-29 2011-09-29 Hsiao-Chuan Chang Semiconductor device package and method of fabricating the same
KR20110123297A (en) * 2010-05-07 2011-11-15 주식회사 네패스 Wafer level semiconductor package and fabrication method thereof
KR20120014099A (en) * 2010-08-06 2012-02-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Flip chip substrate package assembly and process for making same
KR20130007049A (en) * 2011-06-28 2013-01-18 삼성전자주식회사 Package on package using through silicon via technique

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