KR20110109405A - Stereoscopic image display and driving method thereof - Google Patents

Abstract

The present invention relates to a stereoscopic image display device, wherein each of the red, green, and blue subpixels present in each of the display lines of the display panel is divided into first to third subpixels. According to the present invention, left eye image data is written in the first subpixel of the radix display line and right eye image data is written in the first subpixel of the even display line during the Nth (N is positive integer) frame period in the 3D mode. After that, the left eye image data is written in the second subpixel of the odd display line and the right eye image data is written in the second subpixel of the even display line during the N + 1th frame period.

Description

Stereoscopic Display and Driving Method {STEREOSCOPIC IMAGE DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a stereoscopic image display device and a driving method thereof.

The stereoscopic image display device implements a stereoscopic image, that is, a three-dimensional (3D) image by using a stereoscopic technique or an autostereoscopic technique. The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. The spectacle method displays a polarization direction of the left and right parallax images on a direct-view display device or a projector by changing the polarization direction or time division method, and realizes a stereoscopic image using polarized glasses or liquid crystal shutter glasses. The autostereoscopic method is generally provided with an optical plate such as a parallax barrier for separating the optical axis of the left and right parallax images in front of or behind the display screen.

One example of the spectacle method is a stereoscopic image display device in which a patterned retarder is disposed on a display panel. This stereoscopic image display device realizes a 3D image by using the polarization characteristics of the pattern retarder and the polarization characteristics of the polarized glasses worn by the user, and the crosstalk of the left and right eyes in the 3D image is smaller than that of other 3D images. Excellent brightness and excellent image quality.

The stereoscopic image display apparatus using the pattern retarder has the disadvantage that the luminance of the 2D (2D) image is low, the vertical angle of view is low and the resolution is about 50% lower than that of the general 2D display apparatus.

For example, the pattern retarder transmits only the first polarized light of the left eye image incident from the odd display lines of the display panel, whereas only the second polarized light of the right eye image incident from the even display lines of the display panel is transmitted. Permeate. A user wearing polarized glasses can see the first polarization of the left eye image displayed on the radix lines through the left eye polarization filter of the polarized glasses, and the right eye image displayed on the even lines through the right eye polarization filter of the polarized glasses. 2 polarization can be seen. Accordingly, the user can see only the left eye image of the 3D image on the radix display lines LINE # 1 and LINE # 3 of the display panel during the Nth (N is positive integer) frame period as shown in FIG. Since only the right eye image of the 3D image is visible on the even display lines LINE # 2 and LINE # 4 of the display panel during one frame period, the 3D image having a resolution of 50% of the resolution of the display panel can be viewed.

The present invention provides a stereoscopic image display device and a driving method thereof to reduce resolution degradation when displaying a 3D image on a stereoscopic image display device using a pattern retarder.

A stereoscopic image display device includes a display panel including pixels in which data lines and gate lines intersect and are arranged in a matrix; A pattern retarder including a first retarder transmitting first polarization from the odd display line of the display panel and a second retarder transmitting second polarization from the even display line of the display panel; And polarizing glasses including a first polarizing filter for transmitting the first polarized light from the first retarder and a second polarizing filter for transmitting the second polarized light from the second retarder.

Each of the display lines of the display panel includes pixels including red, green, and blue subpixels. Each of the subpixels is divided into first and second subpixels.

In the 3D mode, the left eye image data is written in the first subpixel of the radix display line and the right eye image data is written in the first subpixel of the even display line during the Nth (N is positive integer) frame period. Left eye image data is written in the second subpixel of the odd display line and right eye image data is written in the second subpixel of the even display line during the N + 1th frame period.

In the 3D mode, black data is written in the second subpixel of each of the odd number display line and the even number display line during the Nth frame period, and the odd number display line and the even number display line during the N + 1th frame period. The black data is written to each of the first subpixels.

The stereoscopic image display device generates left eye compensation image data by interpolating left eye image data of a 3D input image, and generates right eye compensation image data by signal interpolating right eye image data of the 3D input image to increase the resolution of the 3D input image. A resolution converter; A data driving circuit for supplying a data voltage of data having a higher resolution by the resolution converter to the data lines; And a gate driving circuit which sequentially supplies gate pulses synchronized with the data voltage to the gate lines.

Data written in the second subpixel of the odd display line during the N + 1th frame period includes the left eye compensation image data. The right eye image data written in the second subpixel of the even display line includes the right eye compensation image data.

The stereoscopic image display device further includes a timing controller that inserts the black data into the 3D input image and supplies the black data to the data driving circuit, and controls an operation timing of the data driving circuit, the gate driving circuit, and the resolution converter. do.

The display panel includes a liquid crystal display, a field emission display, a plasma display panel, and a display panel of any one of an electroluminescent device and an electrophoretic display device.

The driving method of the stereoscopic image display apparatus may include dividing each of the red, green, and blue subpixels existing in each of the display lines of the display panel into first to third subpixels; Writing left eye image data in a first subpixel of the radix display line and writing right eye image data in a first subpixel of the even display line during an Nth (N is positive integer) frame period in a 3D mode; And writing left eye image data in a second subpixel of the odd display line and right eye image data in a second subpixel of the even display line during the N + 1 frame period in the 3D mode.

According to the present invention, the resolution of a 3D image may be increased by dividing pixels of a stereoscopic image display apparatus using a pattern retarder and writing left and right eye image data into each of the pixels in a time division and spatial division scheme.

FIG. 1 is a diagram illustrating 3D image data input to pixels of a stereoscopic image display apparatus using a pattern retarder.
2 is a diagram illustrating a configuration of a stereoscopic image display device according to an exemplary embodiment of the present invention.
3 is a block diagram illustrating a display panel and a driving circuit thereof according to the present invention.
4 to 6 are diagrams illustrating a pixel array of a display panel according to an exemplary embodiment of the present invention.
FIG. 7 is a diagram illustrating left eye image data generated by the resolution converter illustrated in FIG. 3.
FIG. 8 is a diagram illustrating right eye image data generated by the resolution converter illustrated in FIG. 3.
9A is a diagram illustrating 3D image data written in a pixel array of a display panel during an Nth frame period.
9B is a diagram illustrating 3D image data written in a pixel array of a display panel during an Nth frame period.
FIG. 10A is a waveform diagram illustrating an output of a data driving circuit and an output of a gate driving circuit for writing 3D image data as shown in FIG. 9A to a display panel.
FIG. 10B is a waveform diagram illustrating an output of a data driving circuit and an output of a gate driving circuit for writing 3D image data as shown in FIG. 9B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Component names used in the following description may be selected in consideration of ease of specification, and may be different from actual product part names.

2 and 3 are views illustrating a stereoscopic image display device according to an exemplary embodiment of the present invention.

2 and 3, a stereoscopic image display device according to an exemplary embodiment of the present invention includes a display panel 100, a pattern retarder 130, polarizing glasses 140, and driving circuits 101 to 104 of the display panel. ) And the like.

The display panel 100 is a display device for displaying 2D image and 3D image data, and includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel, PDP), and flat panel display devices such as electroluminescence devices (EL) and electrophoretic display devices (EPD), including inorganic electroluminescent devices and organic light emitting diodes (OLEDs). Can be. Hereinafter, the display panel 100 will be described based on the display panel of the liquid crystal display device.

In the display panel 100, a liquid crystal layer is formed between two glass substrates. The display panel 100 includes liquid crystal cells arranged in a matrix by a cross structure of the data lines 105 and the gate lines 106.

The lower glass substrate of the display panel 100 includes pixels including data lines 105, gate lines 106, thin film transistors (TFTs), pixel electrodes, and storage capacitors (Csts). Array 10 is formed. The pixel array 10 of the display panel may be implemented as shown in FIG. 4. The liquid crystal cells are driven by an electric field between the pixel electrodes connected to the TFT and the common electrode. A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the display panel 100. Polarizing films 10a and 10b are attached to each of the upper and lower glass substrates of the display panel 100 to form an alignment layer for setting a pre-tilt angle of the liquid crystal.

The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. The driving method is formed on the lower glass substrate together with the pixel electrode. Column spacers may be formed between the glass substrates to maintain a cell gap of the liquid crystal cell.

The display panel 100 may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, the backlight unit 20 is required. The backlight unit 20 may be implemented as a direct type backlight unit or an edge type backlight unit.

The pattern retarder 130 is attached to the upper polarizing film 10a of the display panel 100. A first retarder is formed in the odd display lines of the pattern retarder 130, and a second retarder is formed in the even display lines of the pattern retarder 130. The light absorption axis of the first retarder and the light absorption axis of the second retarder are different from each other. The first retarder of the pattern retarder 130 transmits the first polarized light (circularly polarized light or linearly polarized light) of light incident from the odd display lines of the pixel array 10 to face the odd display lines of the pixel array 10. Let's do it. The second retarder of the pattern retarder 130 transmits a second polarization (circular polarization or linearly polarized light) of light incident from the even display line of the pixel array 10 to face the even display line of the pixel array 10. . The first retarder of the pattern retarder 130 may be implemented as a polarization filter that transmits left circularly polarized light, and the second retarder of the pattern retarder 130 may be implemented as a polarization filter that transmits right circularly polarized light.

The left eye polarization filter (or first polarization filter) of the polarizing glasses 140 has the same light absorption axis as the first retarder of the pattern retarder 130. The right eye polarization filter (or second polarization filter) of the polarizing glasses 140 has the same light absorption axis as the second retarder of the pattern retarder 130. For example, the left eye polarization filter of the polarizing glasses 140 may be selected as a left circular polarization filter, and the right eye polarization filter of the polarizing glasses 140 may be selected as a right circular polarization filter. The user may view the first polarization of the left eye image passing through the first retarder of the pattern retarder 130 through the left eye polarization filter of the polarizing glasses 140, and the pattern may be viewed through the right eye polarization filter of the polarizing glasses 140. The second polarization of the right eye image passing through the second retarder of the retarder 130 may be viewed.

The driving circuits 101 to 104 of the display panel include a data driving circuit 102, a gate driving circuit 103, a resolution converter 120, a timing controller 101, and the like.

Each of the source drive ICs of the data driving circuit 102 includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, and the like. The data driving circuit 102 latches the digital video data RGB under the control of the timing controller 101. The data driving circuit 102 inverts the polarity of the data voltage by converting the digital video data RGB into analog positive gamma compensation voltage and negative gamma compensation voltage in response to the polarity control signal POL. The data driver circuit 102 outputs a data voltage synchronized with the gate pulse output from the gate driver circuit 103 to the data lines 105. The source drive ICs of the data driving circuit 102 may be mounted on a tape carrier package (TCP) and bonded to a lower glass substrate of the display panel 100 by a tape automated bonding (TAB) process.

The data driving circuit 102 outputs data voltages of the 2D image in which the left eye image and the right eye image are not distinguished in the 2D mode. The data driving circuit 102 supplies the data voltage of the left eye image, the data voltage of the right eye image, and the black data voltage to the data lines 105 in FIGS. 10A and 10B in the 3D mode.

The gate driving circuit 103 includes a shift register, a level shifter, and the like. The gate driving circuit 103 sequentially supplies a gate pulse (or scan pulse) to the gate lines 106 under the control of the timing controller 101. The gate driving circuit 103 is mounted on the TCP and bonded to the lower glass substrate of the display panel 100 by the TAB process, or simultaneously on the lower glass substrate at the same time as the pixel array 10 by the GIP (Gate In Panel) process. Can be formed directly.

The resolution converter 120 generates horizontal left and right eye images that were not present in the input image by performing horizontal scaling of the input image in 3D mode and interpolating the left eye image data and the right eye image data neighboring the input image. Double the resolution of the input image. The resolution converter 120 may be connected to the timing controller 101, disposed between the system board 104 and the timing controller 101, or between the timing controller 101 and the data driving circuit 102. To this end, the resolution converter 120 may include a memory and a resolution conversion module. In the example of FIG. 3, the resolution converter 120 increases the resolution of the 3D image data input from the timing controller 101 and supplies the 3D image data having the higher resolution to the timing controller 101. The timing controller 101 receives 3D image data having a higher resolution by the resolution converter 120 and supplies the 3D image data to the data driving circuit 102. The resolution converter 120 may convert the resolution of 3D image data to be input to the timing controller 101 in advance in the system board 104. A signal interpolation method of the resolution converter 120 to increase the resolution of 3D image data will be described later with reference to FIGS. 7 and 8.

The timing controller 101 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the system board 104. Control signals for controlling the operation timing of the driving circuit 102, the gate driving circuit 103, and the resolution converter 120 are generated. The timing controller 101 may receive a mode signal Mode from the system board 104 and determine a 2D / 3D mode.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) is generated once at the same time as the start of the frame period for one frame period, and the first gate pulse is applied to the gate drive integrated circuit (IC) to generate the first output of the gate drive IC. Let's do it. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). It includes. The source start pulse SSP controls the data sampling start timing of the data driving circuit. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the data driving circuit 102 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 102. The source output enable signal SOE controls the output timing of the data driver circuit 102. If the digital video data to be input to the data driving circuit 102 is transmitted in mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The timing controller 101 may transmit the data of the 2D image to the data driving circuit 102 at the frame frequency of the input frame frequency or the input frame frequency x i (i is a positive integer of 2 or more) Hz in the 2D mode. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the phase-alternating line (PAL) scheme. The timing controller 101 may transmit the data of the 3D image to the data driving circuit 102 at the frame frequency of the input frame frequency x iHz in the 3D mode. In the following description, the frame frequency of the 3D mode is described as 120 Hz, but the present invention is not limited thereto, and the frame frequency of the 3D mode is not only 120 Hz but also 60 × i Hz such as 100 Hz, 150 Hz, 180 Hz, 200 Hz, and 240 Hz. Care must be taken.

The timing controller 101 generates black data as digital data corresponding to grayscale '0' in the 3D mode. The timing controller 101 inserts the black data generated in the 3D mode into the 3D input image data or the 3D image data having a higher resolution by the resolution converter 120 and supplies the black data to the data driving circuit 102.

The system board 104 timings data and timing signals (Vsync, Hsync, DE, CLK) of 2D or 3D video through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. Supply to the controller 101. The system board 104 supplies a mode signal Mode indicating the 2D mode and the 3D mode to the timing controller 101 and the gate driving circuit 103. The system board 104 supplies 2D image data to the timing controller 101 in the 2D mode, while supplying 3D image data including a left eye image and a right eye image in the 3D mode to the timing controller 101.

The user may select a 2D mode and a 3D mode through the user interface 110. The user interface 110 includes a touch screen attached to or embedded in the display panel 100, an on screen display (OSD), a keyboard, a mouse, a remote controller, and the like.

The system board 104 switches between 2D mode operation and 3D mode operation in response to user data input through the user interface 110. The system board 104 includes a 2D / 3D identification code encoded in data of an input image, for example, a 2D / 3D identification code that can be coded in an electronic program guide (EPG) or an electronic service guide (ESG) of a digital broadcasting standard. By detecting, 2D mode and 3D mode can be distinguished.

4 to 6 are diagrams illustrating the pixel array 10 of the display panel 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the pixel array 10 includes m (m is a positive integer) data lines 105, 2n (n is a positive integer) gate lines 106, and data lines 105. And TFTs TFT1 to TFT3 formed at intersections of the gate lines 106. The pixel array 10 includes m × n pixels. In the pixel array 10, m pixels are disposed along the line direction (or row direction) in each of the n display lines LINE # 1 to LINE # n.

Each of the pixels includes a liquid crystal cell of a red subpixel R, a liquid crystal cell of a green subpixel G, and a liquid crystal cell of a blue subpixel B. Each of the red subpixel R, the green subpixel G, and the blue subpixel B includes first and second subpixels divided along a column direction (or a vertical direction).

Each of the first subpixels includes first pixel electrodes PIX1 to PIX3 and first TFTs TFT1 to TFT3. The first TFTs TFT1 to TFT3 supply the data voltages from the data lines D1 to D6 to the first pixel electrodes PIX1 to PIX3 in response to gate pulses from the odd-numbered gate lines G1 and G3. The gate electrodes of the first TFTs TFT1 to TFT3 are connected to the odd-numbered gate lines G1 and G3. The drain electrodes of the first TFTs TFT1 to TFT3 are connected to the data lines D1 to D6, and the source electrodes thereof are connected to the first pixel electrodes PIX1 to PIX3.

Each of the second subpixels includes second pixel electrodes PIX1 ′ to PIX3 ′, and second TFTs TFT1 ˜ TFT3 ′. The second TFTs TFT1 'to TFT3' receive data voltages from the data lines D1 to D6 in response to gate pulses from the even-numbered gate lines G2 and G4 to the second pixel electrodes PIX1 'to PIX3'. To feed. Gate electrodes of the second TFTs TFT1 'to TFT3' are connected to even-numbered gate lines G2 and G4. The drain electrodes of the second TFTs TFT1 'to TFT3' are connected to the data lines D1 to D6, and the source electrodes thereof are connected to the second pixel electrodes PIX1 'to PIX3'.

Data of the 2D image is written in the first and second subpixels. In contrast, data of the 3D image and the black data are written in the first and second subpixels by the time division and spatial division methods as shown in FIGS. 9A to 10B. The first and second subpixels alternately charge black data to serve as active black stripes. The active black stripe increases the vertical viewing angle of the 3D image in the 3D mode.

The vertical pitches P1 and P2 of the first and second subpixels should be appropriately designed in consideration of the vertical viewing angle of the 3D image and the brightness of the 3D image, and the vertical pitch P2 of the second subpixel is It should be less than or equal to the vertical pitch P1. For example, the vertical pitch P2 of the second subpixel may be smaller than the vertical pitch P1 of the first subpixel as shown in FIG. 5, or equal to the vertical pitch P1 of the first subpixel as shown in FIG. 6. Can be.

7 is a diagram illustrating left eye compensation image data generated by the resolution converter 120. 8 is a diagram illustrating right eye compensation image data generated by the resolution converter 120.

7 and 8, the resolution converting unit 120 interpolates left eye data of a 3D input image and performs left eye data L11 to L31 and R11 to R13 having twice the resolution of the 3D input image. Occurs.

The resolution converter 120 bypasses the first line data L1 input during the N-1 (N is a positive integer) frame period to the first left eye image data L11 and the N-1th frame. An average value of pixel data of the first line data L1 and pixel data of the second line data L2 input during the period is calculated and the average value is output as the first left eye compensation image data L12. In addition, the resolution converter 120 bypasses the second line data L2 input during the N-1th frame period to the second left eye image data L21 and inputs the second line data L2 during the N-1th frame period. An average value of the pixel data of the second line data L2 and the pixel data of the third line data L3 is calculated and the average value is output as the second left eye compensation image data L22. The resolution converter 120 bypasses the third line data L3 input during the N-1th frame period to the third left eye image data L31, and receives the third line data input during the N-1th frame period. An average value of pixel data of (L3) and pixel data of fourth line data (not shown) is calculated and the average value is output as third left eye compensation image data.

The resolution converting unit 120 bypasses the first line data R1 input during the Nth frame period to the first right eye image data R11 and stores the first line data R1 input during the Nth frame period. An average value of the pixel data and the pixel data of the second line data R2 is calculated and the average value is output as the first right eye compensation image data R12. In addition, the resolution converter 120 bypasses the second line data R2 input during the Nth frame period to the second right eye image data R21 and inputs the second line data R2 input during the Nth frame period. ) Is computed as the average value of the pixel data of the second data and the pixel data of the third line data R3, and the average value is output as the second right eye compensation image data R22. The resolution converter 120 bypasses the third line data R2 input during the Nth frame period to the third right eye image data R31 and receives the third line data R3 input during the Nth frame period. An average value of the pixel data of the pixel data and the pixel data of the fourth line data (not shown) is calculated and the average value is output as the third right eye compensation image data.

The 3D image data illustrated in FIGS. 7 and 8 are displayed on the pixel array of the display panel 10 by the time division and spatial division methods as shown in FIGS. 9A and 9B. 9A illustrates 3D image data written in a pixel array of a display panel during an Nth frame period. 9B illustrates 3D image data written to a pixel array of a display panel during an N + 1th frame period.

Referring to FIG. 9A, the left eye image data L11 and L21 are written in the first subpixel of the radix display lines LINE # 1 and LINE # 3 during the Nth frame period. The right eye image data R11 and R21 are written in the first subpixel of the even display lines LINE # 2 during the Nth frame period. The black data is written in the second subpixels of the display lines LINE # 1 to LINE # 4 during the Nth frame period. During the Nth frame period, the second subpixel of the display lines LINE # 1 to LINE # 4 serves as a black stripe to improve the vertical viewing angle. The user may view left eye image data L11 and L21 displayed on the first subpixel of the radix display lines LINE # 1 and LINE # 3 through the left eye flattening filter of the polarizing glasses 140 during the Nth frame period. At the same time, the right eye image data R11 and R21 displayed on the first subpixel of the even display lines LINE # 2 and LINE # 4 may be viewed through the right eye flatness filter of the polarizing glasses 140.

Referring to FIG. 9B, the left eye compensation image data L12 and L22 are written in the second subpixel of the odd number display lines LINE # 1 and LINE # 3 during the N + 1th frame period. The right eye compensation image data R12 and R22 are written in the second subpixel of the even display lines LINE # 2 during the N + 1th frame period. The black data is written in the first subpixels of the display lines LINE # 1 to LINE # 4 during the N + 1th frame period. During the N + 1th frame period, the first subpixel of the display lines LINE # 1 to LINE # 4 serves as a black stripe to improve the vertical viewing angle. The user performs left eye compensation image data L12 and L22 displayed on the second subpixel of the radix display lines LINE # 1 and LINE # 3 through the left eye flatness filter of the polarizing glasses 140 during the N + 1th frame period. At the same time, the right eye compensation image data R12 and R22 displayed on the second subpixel of the even display lines LINE # 2 and LINE # 4 may be viewed through the right eye flatness filter of the polarizing glasses 140. have.

FIG. 10A is a waveform diagram illustrating an output of a data driving circuit and an output of a gate driving circuit for writing 3D image data as shown in FIG. 9A on the display panel. FIG. 10B is a waveform diagram illustrating an output of a data driving circuit and an output of a gate driving circuit for writing 3D image data as shown in FIG. 9B. 10A and 10B, GSP is a gate start pulse, and D1 to D3 are data lines 105 to which a data voltage is supplied. G1 to G2n are gate lines 106 to which gate pulses are applied.

Referring to FIG. 10A, the data driving circuit 102 may include first left eye image data L11 to be written in the first subpixel of the first display line LINE # 1 during the first horizontal period of the Nth frame period. Black data to be written in the second subpixel of the first display line LINE # 1 is sequentially output to the data lines D1 to D3. The first left eye image data L11 is synchronized with the first gate pulse supplied to the first gate line G1. The black data is synchronized with the second gate pulse supplied to the second gate line G2.

Subsequently, the data driving circuit 102 may include the first right eye image data R11 and the second display line to be written in the first subpixel of the second display line LINE # 2 during the second horizontal period of the Nth frame period. Black data to be written in the second subpixel of LINE # 2 is sequentially output to the data lines D1 to D3. The first right eye image data R11 is synchronized with the third gate pulse supplied to the third gate line G3. The black data is synchronized with the fourth gate pulse supplied to the fourth gate line G4.

Subsequently, the data driving circuit 102 may include the second left eye image data L21 to be written in the first subpixel of the third display line LINE # 3 and the third display line during the third horizontal period of the Nth frame period. Black data to be written in the second subpixel of LINE # 3 is sequentially output to the data lines D1 to D3. The second left eye image data L21 is synchronized with the fifth gate pulse supplied to the fifth gate line G5. The black data is synchronized with the sixth gate pulse supplied to the sixth gate line G6.

Subsequently, the data driving circuit 102 may include the second right eye image data R21 to be written in the first subpixel of the fourth display line LINE # 4 and the fourth display line during the fourth horizontal period of the Nth frame period. Black data to be written in the second subpixel of LINE # 4 is sequentially output to the data lines D1 to D3. The second right eye image data R21 is synchronized with the seventh gate pulse supplied to the seventh gate line G7. The black data is synchronized with the eighth gate pulse supplied to the eighth gate line G8.

Referring to FIG. 10B, the data driving circuit 102 may include black data to be written in the first subpixel of the first display line LINE # 1 and the first display line during the first horizontal period of the N + 1th frame period. The first left eye compensation image data L12 to be written in the second subpixel of LINE # 1 is sequentially output to the data lines D1 to D3. The black data is synchronized with the first gate pulse supplied to the first gate line G1. The first left eye compensation image data L12 is synchronized with a second gate pulse supplied to the second gate line G1.

Subsequently, the data driving circuit 102 includes black data to be written in the first subpixel of the second horizontal line LINE # 2 and the second horizontal line LINE # 2 during the second horizontal period of the N + 1th frame period. The first right eye compensation image data R12 to be written in the second sub-pixel of) is sequentially output to the data lines D1 to D3. The black data is synchronized with the third gate pulse supplied to the third gate line G3. The first right eye compensation image data R12 is synchronized with the fourth gate pulse supplied to the fourth gate line G4.

Subsequently, the data driving circuit 102 includes black data to be written in the first subpixel of the third display line LINE # 3 and the third display line LINE # 3 during the third horizontal period of the N + 1th frame period. The second left eye compensation image data L22 to be written in the second subpixel of) is sequentially output to the data lines D1 to D3. The black data is synchronized with the fifth gate pulse supplied to the fifth gate line G5. The second left eye compensation image data L22 is synchronized with the sixth gate pulse supplied to the sixth gate line G6.

Subsequently, the data driving circuit 102 may include black data to be written in the first subpixel of the fourth line LINE # 4 and the fourth display line LINE # 4 during the fourth horizontal period of the Nth frame period. The second right eye compensation image data R22 to be written in the two subpixels is sequentially output to the data lines D1 to D3. The black data is synchronized with the seventh gate pulse supplied to the seventh gate line G7. The second right eye compensation image data R22 is synchronized with the eighth gate pulse supplied to the eighth gate line G8.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: pixel array 100: display panel
101: timing controller 102: data driving circuit
103: gate driving circuit 120: resolution conversion unit
130: pattern retarder 140: polarized glasses

Claims (10)

A display panel including pixels in which data lines intersect with gate lines and arranged in a matrix;
A pattern retarder including a first retarder transmitting first polarization from the odd display line of the display panel and a second retarder transmitting second polarization from the even display line of the display panel; And
Polarizing glasses including a first polarizing filter for transmitting the first polarized light from the first retarder and a second polarizing filter for transmitting the second polarized light from the second retarder,
Each of the display lines of the display panel includes pixels including red, green, and blue subpixels, each of the subpixels is divided into first and second subpixels.
In the 3D mode, after the left eye image data is written in the first subpixel of the radix display line and the right eye image data is written in the first subpixel in the even display line during the Nth (N is positive integer) frame period, And left eye image data is written in a second subpixel of the radix display line and a right eye image data is written in a second subpixel of the even display line during an N + 1th frame period. The method of claim 1,
In the 3D mode, black data is written in the second subpixel of each of the odd number display line and the even number display line during the Nth frame period, and the odd number display line and the even number display line during the N + 1th frame period. And the black data is written to each of the first subpixels. The method of claim 2,
A resolution converter for generating left eye compensation image data by signal interpolating left eye image data of a 3D input image and generating right eye compensation image data by signal interpolating the right eye image data of the 3D input image to increase the resolution of the 3D input image;
A data driving circuit for supplying a data voltage of data having a higher resolution by the resolution converter to the data lines; And
And a gate driving circuit which sequentially supplies gate pulses synchronized with the data voltage to the gate lines. The method of claim 3, wherein
The data written in the second subpixel of the radix display line during the N + 1 frame period includes the left eye compensation image data, and the right eye image data written in the second subpixel of the even display line is the right eye compensation. A stereoscopic image display device comprising image data. The method of claim 3, wherein
And a timing controller inserting the black data into the 3D input image and supplying the black data to the data driving circuit, and controlling an operation timing of the data driving circuit, the gate driving circuit, and the resolution converter. Video display. The method of claim 1,
The display panel includes a liquid crystal display device, a field emission display device, a plasma display panel, and a display panel of any one of an electroluminescent device and an electrophoretic display device. A display panel including pixels intersecting the data lines and the gate lines and arranged in a matrix form, a first retarder transmitting first polarized light from an odd display line of the display panel, and an even display line of the display panel A pattern retarder including a second retarder for transmitting a second polarization of the first polarization filter, a first polarizing filter for transmitting a first polarization from the first retarder, and a second polarization from the second retarder A driving method of a stereoscopic image display device having polarizing glasses including a second polarizing filter,
Dividing each of the red, green, and blue subpixels on each of the display lines of the display panel into first to third subpixels;
Writing left eye image data in a first subpixel of the radix display line and writing right eye image data in a first subpixel of the even display line during an Nth (N is positive integer) frame period in a 3D mode; And
And writing left eye image data in a second subpixel of the radix display line and writing right eye image data in a second subpixel of the even display line during the N + 1 frame period in the 3D mode. A driving method of a stereoscopic image display apparatus. The method of claim 7, wherein
Writing black data into the second subpixel of each of the odd display line and the even display line during the Nth frame period in the 3D mode; And
And writing the black data in the first subpixel of each of the odd display line and the even display line in the 3D mode during the N + 1th frame period. Way. The method of claim 8,
Generating left eye compensation image data by signal interpolating the left eye image data of the 3D input image and generating right eye compensation image data by signal interpolating the right eye image data of the 3D input image to increase the resolution of the 3D input image. A driving method of a stereoscopic image display device. The method of claim 9,
The data written in the second subpixel of the radix display line during the N + 1 frame period includes the left eye compensation image data, and the right eye image data written in the second subpixel of the even display line is the right eye compensation. A driving method of a stereoscopic image display device comprising image data.

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