KR20110102727A - Method of manufacturing buried gate semiconductor device - Google Patents

Method of manufacturing buried gate semiconductor device Download PDF

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Publication number
KR20110102727A
KR20110102727A KR1020100021889A KR20100021889A KR20110102727A KR 20110102727 A KR20110102727 A KR 20110102727A KR 1020100021889 A KR1020100021889 A KR 1020100021889A KR 20100021889 A KR20100021889 A KR 20100021889A KR 20110102727 A KR20110102727 A KR 20110102727A
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KR
South Korea
Prior art keywords
trench
forming
gate electrode
film
gate
Prior art date
Application number
KR1020100021889A
Other languages
Korean (ko)
Inventor
김형균
조호진
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100021889A priority Critical patent/KR20110102727A/en
Publication of KR20110102727A publication Critical patent/KR20110102727A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention discloses a method of manufacturing a buried gate type semiconductor device capable of preventing voids in the gate electrode material. A method of manufacturing a buried gate type semiconductor device may include forming a trench by etching a semiconductor substrate to a predetermined depth, forming a barrier film at a bottom of the trench, forming a gate electrode material to fill a trench in which the barrier film is formed; Etching the gate electrode material to form a gate electrode on the barrier layer.

Description

Method of manufacturing buried gate semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a buried gate type semiconductor device capable of preventing void defects of a buried gate electrode material.

As device size shrinks, the channel length of the transistor becomes shorter. As a result, high channel doping was performed to secure transistor characteristics. However, the refresh characteristics were deteriorated. In addition, due to the low storage capacitance (Cs) it is difficult to secure a sufficient sensing margin is making efforts to lower the parasitic capacitance (Cb).

In order to solve the above problem, a buried gate structure in which a gate is arranged under a bit line has been proposed. The buried gate structure grows a gate oxide layer in the trench of the substrate, deposits a barrier metal and a gate electrode material to fill the trench, and then etches it back to form a gate electrode.

However, as the size of the device becomes smaller, the size of the trench also becomes smaller, causing voids to occur in the gate electrode material embedded in the trench. These voids increase the resistance of the gate electrode. In addition, since the gate electrode is formed after the gate oxide film is grown in the trench, the trench size is reduced by the thickness of the gate oxide film, and the generation of voids becomes more serious.

An object of the present invention is to provide a method of manufacturing a buried gate type semiconductor device capable of preventing void generation of a gate electrode material.

In the method of manufacturing a buried gate type semiconductor device according to an embodiment of the present invention, forming a trench by etching a semiconductor substrate to a predetermined depth, forming a barrier layer on the bottom of the trench, and forming a gate in which the trench in which the barrier layer is formed is buried. Forming an electrode material and etching the gate electrode material to form a gate electrode on the barrier layer.

The method of manufacturing the buried gate type semiconductor device may further include forming a gate insulating layer on an inner surface of the trench between the trench forming step and the barrier film forming step.

The barrier material film may include TiN, and the gate electrode material may include a tungsten film.

The forming of the barrier layer may include forming a barrier material layer on the inner surface of the trench and the substrate, forming a sacrificial insulating layer on the barrier material layer to fill the trench, and wherein the sacrificial insulating layer is a bottom portion of the trench. And etching the sacrificial insulating layer so as to remain only, and removing the barrier material layer exposed by the etched sacrificial insulating layer.

The forming of the barrier layer may further include completely removing the sacrificial insulating layer remaining in the trench. The sacrificial insulating film may include an oxide film having excellent capfill characteristics.

The method of manufacturing the buried gate type semiconductor device may further include forming a gate capping layer on the gate electrode in the trench. The gate capping layer may include an oxide film.

According to the method of manufacturing a buried gate semiconductor device of the present invention, a barrier film is formed on a bottom of a trench in which a gate insulating film is formed using a sacrificial insulating film, and then a tungsten film is formed as a gate electrode material on the barrier film, thereby forming the tungsten film. Since it is deposited only on the remaining barrier film and is sequentially filled from the bottom of the trench, a tungsten film can be deposited without voids. Accordingly, an increase in gate resistance due to voids can be prevented.

1 to 6 are cross-sectional views illustrating a method of manufacturing a buried semiconductor device according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 6 are cross-sectional views illustrating a method of manufacturing a buried gate semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a pad oxide layer (not shown) and a hard mask layer (not shown) are sequentially formed on a semiconductor substrate 100, and then a predetermined portion of the semiconductor substrate 100, for example, a gate formation region, is formed. The hard mask layer and the pad oxide layer are etched using the gate mask (not shown) to form the pad oxide layer pattern 110 and the hard mask pattern 120. The hard mask pattern 120 may include a nitride film or polysilicon. The trench 130 is formed by etching the exposed portion of the semiconductor substrate 100 by a predetermined depth using the hard mask pattern 120 as an etching mask.

Subsequently, a gate insulating layer 140 is formed on the bottom and sidewalls of the trench 130. An oxide layer may be formed by oxidizing the bottom and sidewalls of the gate trench 130 with the gate insulating layer 140.

Referring to FIG. 2, a barrier material layer 150 is formed on the trench 130 on which the gate insulating layer 140 is formed and the hard mask pattern 120. The barrier material layer 150 may include TiN. A sacrificial insulating layer 160 is formed on the barrier material layer 150 to completely fill the trench 130. The sacrificial insulating layer 160 may include an oxide film having excellent capfill characteristics.

Referring to FIG. 3, the sacrificial insulating layer 160 may be first etched to remain only at the bottom of the trench 130, and the trench material layer 150 may be removed by removing the barrier material layer 150 exposed by the first etched sacrificial insulating layer 160. The barrier film 155 is formed at the bottom of the 130. In this case, the primary etching process may be etched using a wet dipping process. Alternatively, the first etching process may be etched through an etch back process.

Referring to FIG. 4, the sacrificial insulating layer 160 remaining in the trench 130 is completely removed through the secondary etching process to expose the barrier layer 155 remaining in the bottom of the trench 130. The secondary etching process may be etched using a wet dipping process. Alternatively, the secondary etching process may be etched through a dry etching process.

Referring to FIG. 5, a gate electrode material 170 is deposited to fill the trench 130. The gate electrode material 170 may include tungsten. Since the gate electrode material 170 is deposited only on the barrier layer 155, the gate electrode material 170 is sequentially deposited from the bottom surface of the trench 130, and thus generation of voids may be suppressed.

Referring to FIG. 6, the gate electrode material 170 is etched back to form a gate electrode 175 on the barrier layer 155 in the trench 130. Next, an insulating film is deposited on the gate electrode 175 and then etched back to form a gate capping layer 180 on the gate electrode 175 in the trench 130. The gate capping layer 180 may include an oxide layer.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, various modifications by those skilled in the art within the spirit and scope of the present invention And changes are possible.

100: substrate 110: pad oxide film pattern
120: hard mask pattern 130: trench
140: gate insulating film 150: barrier material film
155: barrier film 160: sacrificial insulating film
170: gate electrode material 175: gate electrode
180: gate capping film

Claims (8)

Etching the semiconductor substrate to a predetermined depth to form a trench;
Forming a barrier layer on the bottom of the trench;
Forming a gate electrode material to fill the trench in which the barrier layer is formed; And
Etching the gate electrode material to form a gate electrode on the barrier layer. The method of claim 1, further comprising forming a gate insulating film on an inner surface of the trench between the trench forming step and the barrier film forming step. The method of claim 1, wherein the barrier material film comprises TiN and the gate electrode material comprises a tungsten film. The method of claim 1, wherein the forming of the barrier layer is performed.
Forming a barrier material film on the inner side of the trench and on the substrate;
Forming a sacrificial insulating film on the barrier material film to fill the trench;
Etching the sacrificial insulating film so that the sacrificial insulating film remains only at the bottom of the trench; And
And removing the barrier material film exposed by the etched sacrificial insulating film. The method of claim 4, further comprising completely removing the sacrificial insulating film remaining in the trench. The method of claim 4, wherein the sacrificial insulating film includes an oxide film having excellent capfill characteristics. The method of claim 1, further comprising forming a gate capping layer on the gate electrode in the trench. The method of claim 7, wherein the gate capping layer comprises an oxide film.
KR1020100021889A 2010-03-11 2010-03-11 Method of manufacturing buried gate semiconductor device KR20110102727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100021889A KR20110102727A (en) 2010-03-11 2010-03-11 Method of manufacturing buried gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100021889A KR20110102727A (en) 2010-03-11 2010-03-11 Method of manufacturing buried gate semiconductor device

Publications (1)

Publication Number Publication Date
KR20110102727A true KR20110102727A (en) 2011-09-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100021889A KR20110102727A (en) 2010-03-11 2010-03-11 Method of manufacturing buried gate semiconductor device

Country Status (1)

Country Link
KR (1) KR20110102727A (en)

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