CN104425358A - Method for forming plug - Google Patents

Method for forming plug Download PDF

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Publication number
CN104425358A
CN104425358A CN201310382848.0A CN201310382848A CN104425358A CN 104425358 A CN104425358 A CN 104425358A CN 201310382848 A CN201310382848 A CN 201310382848A CN 104425358 A CN104425358 A CN 104425358A
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CN
China
Prior art keywords
layer
contact hole
etching
connector
formation method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310382848.0A
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Chinese (zh)
Inventor
韩秋华
黄敬勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201310382848.0A priority Critical patent/CN104425358A/en
Publication of CN104425358A publication Critical patent/CN104425358A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Provided is a method for forming a plug. The method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a contact hole in the dielectric layer; filling the contact hole with a sacrificial layer, the upper surface of the sacrificial layer being lower than the upper surface of the dielectric layer; etching the side walls of the contact hole which is not covered by the sacrificial layer; removing the sacrificial layer after etching the side walls of the contact hole which is not covered by the sacrificial layer; and filling the contact hole with a plug material after removing the sacrificial layer, so as to form a plug. No gap exists in the plug which is formed by the method.

Description

The formation method of connector
Technical field
The present invention relates to semiconductor applications, be related specifically to a kind of formation method of connector.
Background technology
Along with the development of semiconductor technology, the size of semiconductor device is constantly reducing, and traditional low aspect ratio trench develops into the groove of high-aspect-ratio gradually, these grooves of gapless filling to become more and more difficult.Wherein depth-to-width ratio is defined as the degree of depth of groove and the ratio of width, and the representative value of high-aspect-ratio is greater than 3:1.
To form W connector, its formation method comprises:
With reference to figure 1, provide substrate 1.
With reference to figure 2, described substrate 1 forms dielectric layer 2.
With reference to figure 3, in described dielectric layer 2, form contact hole 3, described contact hole 3 has high-aspect-ratio.
With reference to figure 4, in described contact hole 3, form barrier layer 4.
Described barrier layer 4 is double-decker, comprises the Ti layer being positioned at bottom, and is positioned at the TiN layer at top.Wherein the effect of Ti layer is the adhesiveness improving W and dielectric layer 2.The effect of TiN layer is the diffusion stoping W.
Because contact hole 3 has high-aspect-ratio, when filling formation barrier layer 4 in described contact hole 3, in barrier layer 4, hole 5 may be formed.
With reference to figure 5, in the contact hole 3 being formed with barrier layer 4, fill W, form connector 6.
Because W has corrosivity, if W directly contacts with dielectric layer 2, W can etching dielectric layer 2.Owing to forming hole 5 in barrier layer 4, hole 5 makes W directly contact with dielectric layer 2, and W etching dielectric layer 2, in dielectric layer 2, form etch pit 7.Etch pit 7 may cause connector 6 to be connected with contiguous device, causes whole chip failure.
With reference to figure 6, even if do not form hole 5 in barrier layer 4, because contact hole 3 has high-aspect-ratio, when filling W to form connector, also may cause forming gap in connector.
With reference to figure 7, form connector 6, in connector 6, have gap 8.
Be the SEM(Scanning Electron Microscope having gap 8 in connector 6 with reference to figure 8, Fig. 8) figure.
Gap 8 makes the resistance of connector 6 increase, and affects the performance of device.
Summary of the invention
The problem that the present invention solves there is gap in the connector formed in prior art.
For solving the problem, the invention provides a kind of formation method of connector, comprising: substrate is provided; Form dielectric layer on the substrate; Contact hole is formed in described dielectric layer; In described contact hole, fill sacrifice layer, described sacrifice layer upper surface is lower than described dielectric layer upper surface; Etching is not by contact hole sidewall that described sacrifice layer covers; After etching the contact hole sidewall do not covered by described sacrifice layer, remove described sacrifice layer; After removing described sacrifice layer, in described contact hole, fill plug material, form connector.
Optionally, described sacrifice layer upper surface is greater than 0.1nm to the spacing of described dielectric layer upper surface.
Optionally, the method etching the contact hole sidewall do not covered by described sacrifice layer is wet etching or dry etching.
Optionally, the etching agent of wet etching is the HF of dilution.
Optionally, dry etching is plasma etching.
Optionally, plasma etching is Ar plasma etching; Or plasma etching is fluorocarbon plasma and O 2plasma etching.
Optionally, after the contact hole sidewall that etching is not covered by described sacrifice layer, the size of the contact hole do not covered by described sacrifice layer increases 2-10nm.
Optionally, the method for filling sacrifice layer comprises: in described contact hole, form sacrificial material layer with described dielectric layer upper surface, described sacrificial material layer upper surface exceeds described dielectric layer upper surface; Etching removes the sacrificial material layer of segment thickness in sacrificial material layer and described contact hole that described dielectric layer upper surface formed, forms sacrifice layer.
Optionally, dielectric layer upper surface is 2-5nm to the spacing of sacrificial material layer upper surface.
Optionally, the method forming sacrificial material layer comprises chemical vapour deposition (CVD), physical vapour deposition (PVD), ald or spin-coating method.
Optionally, sacrifice layer is organic matter layer, amorphous carbon layer or metal level.
Optionally, the method removing described sacrifice layer is O 2plasma etching, or N 2and H 2plasma etching.
Optionally, described plug material is W, Al or Cu.
Optionally, described plug material is W, before filling plug material, also comprises in described contact hole: on sidewall and the formation barrier layer, bottom of described contact hole.
Optionally, described barrier layer comprises Ti layer, and is positioned at the TiN on described Ti layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
The technical program etching is not by the contact hole sidewall that described sacrifice layer covers, and the size of the contact hole do not covered by described sacrifice layer is increased, and after removing described sacrifice layer, the opening of contact hole is increased; When filling plug material in described contact hole, because the opening of contact hole increases, be conducive to filling plug material, and obtain seamless connector.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is the cross-sectional view of each production phase of W connector formation method in prior art;
Fig. 8 is the SEM figure of the W connector formed in prior art;
Fig. 9 to Figure 19 is the cross-sectional view of formation method each production phase of connector in specific embodiment.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The present embodiment provides a kind of formation method of connector, comprising:
With reference to figure 9, provide substrate 110.
Substrate 110 can be the conventional semiconductor base such as silicon base, silicon-Germanium base, silicon-on-insulator (silicon on insulator, SOI) substrate.
In a particular embodiment, in described substrate 110, be formed with semiconductor device (not shown), such as, there is the metal oxide semiconductor device of grid, source electrode and drain electrode.Described substrate 110 can also be formed with metal interconnect structure (not shown), as metal interconnecting wires or connector.
With reference to Figure 10, described substrate 110 forms dielectric layer 120.
The method forming dielectric layer 120 can be chemical vapour deposition (CVD) or physical vapour deposition (PVD), and described dielectric layer 120 can be the layer of dielectric material known in the art such as silicon oxide layer.
Then, in described dielectric layer 120, form contact hole, the method forming contact hole comprises:
With reference to Figure 11, described dielectric layer 120 forms patterned mask layer 101.
In a particular embodiment, patterned mask layer 101 is patterned photoresist.
In other embodiments, also bottom anti-reflection layer is formed with between described patterned photoresist and described dielectric layer 120.The effect of described bottom anti-reflection layer weakens the reflection produced when forming patterned photoresist, to realize the accurate transfer of fine pattern.
With reference to Figure 12, with described patterned mask layer 101 for mask, etch described dielectric layer 120, form contact hole 130.Then described patterned mask layer 101 is removed.
In a particular embodiment, the method etching described dielectric layer 120 is plasma etching, and described plasma is CF 4plasma.
In other embodiments, the method etching described dielectric layer 120 also can be other lithographic methods known in the art such as wet etching.
Then, in described contact hole 130, fill sacrifice layer, described sacrifice layer upper surface is lower than described dielectric layer 120 upper surface.The method of filling sacrifice layer comprises:
With reference to Figure 13, in described contact hole 130, form sacrificial material layer 102 with described dielectric layer 120 upper surface, described sacrificial material layer 102 upper surface exceeds described dielectric layer 120 upper surface.
The method forming sacrificial material layer 102 comprises chemical vapour deposition (CVD), physical vapour deposition (PVD), ald, spin-coating method or additive method known in the art.
In a particular embodiment, dielectric layer 120 upper surface is 2-5nm to the spacing H1 of sacrificial material layer 102 upper surface.
Wherein, sacrificial material layer 102 is organic matter layer, amorphous carbon layer, metal level or other materials layer known in the art.Sacrificial material layer 102 should ensure when etching described sacrificial material layer 102, and described sacrificial material layer 102 has very high etching selection ratio with described dielectric layer 120.
With reference to Figure 14, etching removes the sacrificial material layer 102 of segment thickness in sacrificial material layer 102 and described contact hole 130 that described dielectric layer 120 upper surface formed, forms sacrifice layer 103.In a particular embodiment, the method etching the sacrificial material layer 102 of segment thickness in the sacrificial material layer 102 removing the formation of described dielectric layer 120 upper surface and described contact hole 130 is O 2plasma etching, or N 2and H 2plasma etching.
Described sacrifice layer 103 upper surface is greater than 0.1nm to the spacing H2 of described dielectric layer upper surface.
With reference to Figure 15, etching is not by contact hole 130 sidewall that described sacrifice layer 103 covers.
The method etching contact hole 130 sidewall do not covered by described sacrifice layer 103 is wet etching or dry etching.
Wherein the etching agent of wet etching is the HF of dilution.
Wherein dry etching is plasma etching, as Ar plasma etching; Or, fluorocarbon plasma and O 2plasma etching.
In a particular embodiment, when using Ar plasma etching, power is 500-1500W.Use fluorocarbon plasma and O 2during plasma etching, power is 200-500W, and pressure is 70-200mTorr.
After contact hole 130 sidewall that etching is not covered by described sacrifice layer, the size of the contact hole 130 do not covered by described sacrifice layer increases 2-10nm, and the size W that namely every side increases is 1-5nm.
With reference to Figure 16, after etching contact hole 130 sidewall do not covered by described sacrifice layer 103, remove described sacrifice layer 103.
The method removing described sacrifice layer 103 is O 2plasma etching, or N 2and H 2plasma etching.
After removing described sacrifice layer 103, in described contact hole 130, fill plug material, form connector.In the present embodiment, before forming connector, also comprise:
With reference to Figure 17, on described contact hole 130 sidewall and formation barrier layer, bottom 140.
In a particular embodiment, described barrier layer 140 comprises Ti layer, and is positioned at the TiN layer on described Ti layer.
The method forming barrier layer 140 can be chemical vapour deposition (CVD), physical vapour deposition (PVD), ald or additive method known in the art.
Because the technical program etches not by contact hole 130 sidewall that described sacrifice layer 103 covers, the size of the contact hole 130 do not covered by described sacrifice layer 103 is increased, and after removing described sacrifice layer 103, the opening of contact hole 130 is increased.The opening size of contact hole 130 increases, and is conducive to forming barrier layer 140 in described contact hole 130, obtains imperforate barrier layer 140.
After forming barrier layer, in described contact hole 130, fill plug material, form connector.The method forming connector comprises:
With reference to Figure 18, in described contact hole 130, form plug material layer 151 with described dielectric layer 120 upper surface.
In a particular embodiment, the method forming plug material layer 151 can be chemical vapour deposition (CVD), physical vapour deposition (PVD), ald or additive method known in the art.
The material of described plug material layer 151 is W.The effect of the Ti layer in described barrier layer 140 is the adhesiveness improving W and dielectric layer 120, and the effect of the TiN layer in described barrier layer 140 is the diffusion stoping W, prevents W etching dielectric layer 120.
Because the technical program etches not by contact hole 130 sidewall that described sacrifice layer 103 covers, the size of the contact hole 130 do not covered by described sacrifice layer 103 is increased, and after removing described sacrifice layer 103, the opening of contact hole 130 is increased.The opening size of contact hole 130 increases, and is conducive to plug material layer 151 and fills described contact hole 130, obtain the plug material layer 151 in gap.
With reference to Figure 19, remove the plug material layer 151 that described dielectric layer 120 upper surface is formed, in described contact hole 130, form connector 150.
Gap is not formed in described connector 150.
Above embodiment, is described the formation method of connector 150 for W for described plug material.In other embodiments, described plug material also can be other plug material known in the art such as Al, Cu.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (15)

1. a formation method for connector, is characterized in that, comprising:
Substrate is provided;
Form dielectric layer on the substrate;
Contact hole is formed in described dielectric layer;
In described contact hole, fill sacrifice layer, described sacrifice layer upper surface is lower than described dielectric layer upper surface;
Etching is not by contact hole sidewall that described sacrifice layer covers;
After etching the contact hole sidewall do not covered by described sacrifice layer, remove described sacrifice layer;
After removing described sacrifice layer, in described contact hole, fill plug material, form connector.
2. the formation method of connector as claimed in claim 1, is characterized in that, described sacrifice layer upper surface is greater than 0.1nm to the spacing of described dielectric layer upper surface.
3. the formation method of connector as claimed in claim 1, is characterized in that, the method etching the contact hole sidewall do not covered by described sacrifice layer is wet etching or dry etching.
4. the formation method of connector as claimed in claim 3, is characterized in that, the etching agent of wet etching is the HF of dilution.
5. the formation method of connector as claimed in claim 3, it is characterized in that, dry etching is plasma etching.
6. the formation method of connector as claimed in claim 5, it is characterized in that, plasma etching is Ar plasma etching; Or,
Plasma etching is fluorocarbon plasma and O 2plasma etching.
7. the formation method of connector as claimed in claim 1, is characterized in that, after the contact hole sidewall that etching is not covered by described sacrifice layer, the size of the contact hole do not covered by described sacrifice layer increases 2-10nm.
8. the formation method of connector as claimed in claim 1, is characterized in that, the method for filling sacrifice layer comprises:
In described contact hole, form sacrificial material layer with described dielectric layer upper surface, described sacrificial material layer upper surface exceeds described dielectric layer upper surface;
Etching removes the sacrificial material layer of segment thickness in sacrificial material layer and described contact hole that described dielectric layer upper surface formed, forms sacrifice layer.
9. the formation method of connector as claimed in claim 8, it is characterized in that, dielectric layer upper surface is 2-5nm to the spacing of sacrificial material layer upper surface.
10. the formation method of connector as claimed in claim 8, is characterized in that, the method forming sacrificial material layer comprises chemical vapour deposition (CVD), physical vapour deposition (PVD), ald or spin-coating method.
The formation method of 11. connectors as claimed in claim 1, it is characterized in that, sacrifice layer is organic matter layer, amorphous carbon layer or metal level.
The formation method of 12. connectors as described in claim 1 or 11, it is characterized in that, the method removing described sacrifice layer is O 2plasma etching, or N 2and H 2plasma etching.
The formation method of 13. connectors as claimed in claim 1, it is characterized in that, described plug material is W, Al or Cu.
The formation method of 14. connectors as claimed in claim 13, it is characterized in that, described plug material is W, before filling plug material, also comprises in described contact hole:
On sidewall and the formation barrier layer, bottom of described contact hole.
The formation method of 15. connectors as claimed in claim 14, it is characterized in that, described barrier layer comprises Ti layer, and is positioned at the TiN on described Ti layer.
CN201310382848.0A 2013-08-28 2013-08-28 Method for forming plug Pending CN104425358A (en)

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Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107170708A (en) * 2017-05-08 2017-09-15 上海华力微电子有限公司 Beneficial to the via-hole fabrication process of filling

Citations (4)

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Publication number Priority date Publication date Assignee Title
US6426298B1 (en) * 2000-08-11 2002-07-30 United Microelectronics Corp. Method of patterning a dual damascene
US6465889B1 (en) * 2001-02-07 2002-10-15 Advanced Micro Devices, Inc. Silicon carbide barc in dual damascene processing
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
CN101996934A (en) * 2009-08-20 2011-03-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426298B1 (en) * 2000-08-11 2002-07-30 United Microelectronics Corp. Method of patterning a dual damascene
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
US6465889B1 (en) * 2001-02-07 2002-10-15 Advanced Micro Devices, Inc. Silicon carbide barc in dual damascene processing
CN101996934A (en) * 2009-08-20 2011-03-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107170708A (en) * 2017-05-08 2017-09-15 上海华力微电子有限公司 Beneficial to the via-hole fabrication process of filling

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Application publication date: 20150318