KR20110070172A

KR20110070172A - Liquid crystal display device and method of driving the same

Info

Publication number: KR20110070172A
Application number: KR1020090126895A
Authority: KR
Inventors: 김번영; 이상훈; 허동균
Original assignee: 엘지디스플레이 주식회사
Priority date: 2009-12-18
Filing date: 2009-12-18
Publication date: 2011-06-24
Also published as: KR101630340B1

Abstract

PURPOSE: A liquid crystal display device and a method of driving the same are provided to improve the deterioration of image quality due to temperature change by driving a liquid crystal panel under ambient temperature with an optimum timing. CONSTITUTION: In a liquid crystal display device and a method of driving the same, a liquid crystal panel(200) comprises a gate line and a data line. A gate driving unit(320) outputs a scan pulse to a gate line. A data driver(330) outputs a data voltage to the data line. A temperature detection part(500) detects an ambient temperature. A data storage module(400) varies timing data. The timing controller(310) varies the timing of the control signal. A control signal controls the gate driving unit and the data driver.

Description

Liquid crystal display device and method of driving the same

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diodes Various flat display devices such as OLEDs (organic light emitting diodes) are being utilized.

Among these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, light weight, thinness, and low power driving.

As the liquid crystal display device, an active matrix type liquid crystal display device in which a switching transistor is formed in each of the pixels arranged in a matrix form is commonly used.

In an active matrix type liquid crystal display device, when a gate wiring is scanned, a scan pulse is applied to turn on the switching transistor. In synchronization with this, the data voltage is transferred through the data wiring and applied to the corresponding pixel. As a result, a data voltage is applied to the pixel electrode of the pixel, and light corresponding thereto is emitted.

Recently, various technologies have been applied to such liquid crystal displays. For example, a method of reducing data wiring and the number of driving circuits thereof by providing neighboring pixels along the row direction to share data wiring has been proposed. In addition, a method of forming a storage wiring constituting a pixel electrode and a storage capacitor under the data wiring has been proposed.

However, in the case of displaying an image by applying these techniques to a liquid crystal display, it has been found that color difference occurs at low temperature and high temperature, thereby deteriorating image quality. For example, when displaying an image at a low temperature, it has been confirmed that vertical bands are generated along the direction in which the data wiring is extended. In the case of displaying an image at a high temperature, a pinkish phenomenon occurs in which a partial region, for example, an upper region of the image is pink.

Although the cause for such phenomena is not clearly identified, it appears to be due to the voltage charge variation between the pixels of the liquid crystal panel. That is, the low temperature color difference in which the vertical band is generated is caused by the influence of the resistance difference between the data wires and the voltage charge variation due to the coupling between the data wires and the storage wires. In addition, a high temperature color difference in which a pinky phenomenon occurs occurs due to an increase in the pixel voltage drop ΔVp at a high temperature, which is caused by a voltage charge variation caused by a decrease in an optimum common voltage felt by the liquid crystal panel.

At present, there is no effective improvement plan for image quality deterioration due to temperature change.

The present invention has a problem to provide a liquid crystal display device and a driving method thereof which can improve the image quality deterioration due to temperature change.

In order to achieve the above object, the present invention is a liquid crystal panel comprising a gate wiring and a data wiring crossing each other to define a pixel; A gate driver for outputting a scan pulse to the gate wiring of the liquid crystal panel; A data driver for outputting a data voltage to the data line of the liquid crystal panel; A temperature detector for measuring an ambient temperature; A data storage unit for changing and outputting timing data in response to the measured temperature change; In response to the change of the timing data, there is provided a liquid crystal display including a timing controller for changing the timing of the control signal for controlling the gate driver and the data driver.

Here, two pixels positioned adjacent to each other along the direction in which the gate wiring extends may share data wirings positioned between the two pixels, and may be connected to two neighboring gate wirings, respectively.

The storage wirings overlapping the pixel electrodes of the pixels and constituting the storage capacitors may overlap the data wirings.

The gate driver includes: a level shifter circuit for level shifting the gate clock signal included in the control signal; And a shift register circuit configured to receive the level shifted gate clock signal and output the scan pulse.

The shift register circuit may be directly formed on the array substrate of the liquid crystal panel.

In another aspect, the present invention includes the steps of measuring the ambient temperature; In response to the measured change in temperature, changing and outputting timing data; In the timing controller, changing and outputting a timing of a control signal in response to the change of the timing data; A gate driver and a data driver provide a method of driving a liquid crystal display, the method comprising driving a liquid crystal panel in response to the output control signal.

Here, the liquid crystal panel includes a gate wiring and a data wiring crossing each other to define pixels, and two pixels positioned adjacent to each other along a direction in which the gate wiring extends may include data positioned between the two pixels. The wiring may be shared and may be connected to two neighboring gate wirings, respectively.

The story dominant line constituting the storage capacitor overlapping with the pixel electrode of the pixel may overlap the data line.

In the present invention, the optimum drive timing according to the temperature is calculated in advance, and the timing data capable of implementing such an optimum drive timing is stored in the data storage unit.

Accordingly, even when the temperature is changed, it is possible to select timing data capable of implementing the optimum driving timing for the changed temperature. This makes it possible to drive the liquid crystal panel at the optimum timing for the temperature regardless of the temperature change. Therefore, it is possible to improve the image quality deterioration due to the temperature change.

Hereinafter, with reference to the drawings will be described embodiments of the present invention.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention, Figure 2 is an equivalent circuit diagram schematically showing the structure of a pixel according to an embodiment of the present invention.

As shown, the liquid crystal display device 100 according to the embodiment of the present invention includes a liquid crystal panel 200, a driving circuit, and a backlight 600. Here, the driving circuit includes a timing controller 310, a gate driver 320, a data driver 330, a gamma reference voltage generator 340, a data storage 400, and a temperature detector 500. It may include.

The liquid crystal panel 200 includes two substrates facing each other, for example, an array substrate and an opposing substrate, and a liquid crystal layer positioned between the two substrates.

The array substrate of the liquid crystal panel 200 includes a plurality of gate lines GL extending in a first direction, for example, a row direction, and a plurality of data lines DL extending in a second direction, for example, a column direction. In this crossing, a plurality of pixels P arranged in a matrix form is defined.

Referring to FIG. 2, in each pixel P, a switching transistor T connected to the gate line and the data line GL and DL is formed. The switching transistor T is connected to the pixel electrode. Meanwhile, a common electrode is formed corresponding to the pixel electrode. When voltage is applied to these pixel electrodes and the common electrode, an electric field is formed between these electrodes, thereby driving the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal positioned between these electrodes constitute a liquid crystal capacitor Clc.

Meanwhile, a storage capacitor Cst is further configured in each pixel P, which stores a data voltage applied to the pixel electrode until the next frame. Such a storage capacitor Cst may include a pixel electrode and a storage wiring portion overlapping each other.

Here, in the liquid crystal panel 200 according to the exemplary embodiment of the present invention, the pixels P adjacent to each other along the row direction may share the data wiring DL positioned between the pixels P. .

In this regard, referring to FIG. 1, among pixels P adjacent to each other in a row direction, a pixel located on one side of the data line DL, for example, the left side, is referred to as a first pixel P1. For example, the pixel located on the right side will be referred to as a second pixel P2. In this case, the first pixel P1 and the second pixel P2 are connected to the gate wiring GL adjacent to each other. That is, the first pixel P1 is connected to the gate wiring GL at the front end, and the second pixel P2 is connected to the gate wiring GL at the rear end.

As described above, as two pixels P adjacent to each other share the data line DL with respect to one data line DL, the number of data lines DL may be reduced by about half. It becomes possible. Furthermore, as the number of data lines DL can be reduced in this manner, the number of data ICs configured in the data driver circuit 300 for driving the data lines DL can also be reduced by about half. As such, as the number of data lines DL and the elements driving the same decrease, manufacturing costs thereof may be reduced.

Meanwhile, in the liquid crystal panel 200 according to the embodiment of the present invention, the storage wiring may be formed under the data wiring DL and overlap the data wiring DL. The storage wiring having such a configuration is formed to overlap the pixel electrode, so that the storage capacitor Cst can be configured as described above.

The timing controller 310 may include a data processor 311 and a control signal generator 312.

The data processor 311 sorts and outputs the input image data Data. The video data Data thus output is supplied to the data driver 330.

The control signal generator 312 may generate various control signals for controlling the driving circuit of the liquid crystal display device 100. For example, the data control signal DCCS for controlling the data driver circuit 330 and the gate control signal GCS for controlling the gate driver circuit 320 are generated.

Such control signals GCS and DCS are generated with reference to the timing data TDa. For example, the timing of the control signals GCS and DCS may be adjusted according to the timing data TDa. In this manner, the timing data TDa used to generate the control signals GCS and DCS is stored in the data storage 400. Accordingly, the timing controller 310 may receive the timing data TDa stored in the data storage 400 and output the control signals GCS and DCS corresponding to the input timing data TDa.

The timing data TDa input to the timing controller 310 may be changed according to a temperature sensed by the liquid crystal display device 100. For example, in response to the temperature measured by the temperature detector 500, corresponding timing data TDa may be output from the data storage 400.

When the timing data TDa is changed in accordance with the temperature change as described above, the timing of the output control signals GCS and DCS is also changed. Accordingly, the driving timing of the liquid crystal panel 200 is changed. As described above, a detailed description of a method of adaptively adjusting the timing of the control signals GCS and DCS according to the temperature change to adjust the driving timing of the liquid crystal panel 200 will be described later.

The gamma reference voltage generator 340 divides the high potential voltage and the low potential voltage to generate a plurality of gamma reference voltages Vgamma, and supplies them to the data driver 330.

The gate driver 320 sequentially applies scan pulses to the plurality of gate lines GL in response to the gate control signal GCS.

For example, a plurality of gate lines GL are sequentially scanned every frame, and scan pulses are output to the gate lines GL during each scan period. Accordingly, the switching transistor T is turned on in response to the turn-on voltage of the scan pulse, for example, the gate high voltage.

On the other hand, the turn-off voltage, for example, the gate low voltage is supplied to the gate wiring GL until the next frame is scanned. As such, during the period in which the gate low voltage is supplied, the switching transistor T is turned off.

As such, the gate driver 320 outputs the gate voltage to the gate wiring GL to drive the gate wiring GL.

The gate driver 320 may include a level shifter circuit 321 and a shift register circuit 322.

The level shifter circuit 321 level shifts the voltage level with respect to at least one gate clock signal CLK as the input gate control signal GCS. For example, the level shifter circuit 321 shifts the voltage level to the gate high voltage and the gate low voltage with respect to the low voltage and the high voltage of the input gate clock signal CLK.

On the other hand, as the gate control signal GCS to be input, for example, the level shift operation can be performed on the gate start pulse VST.

As described above, the gate clock signal CLK and the gate start pulse VST that are level-shifted and output through the level shifter circuit 321 may be input to the shift register circuit 322.

The shift register circuit 322 may include a plurality of shift register stages for outputting a gate voltage to each of the gate lines GL. For example, each shift register stage receives a gate voltage output from a shift register stage located at a previous stage and outputs a scan pulse in response thereto. Here, the shift register stage located in the first row line outputs the scan pulse to the corresponding gate wiring GL in response to the gate start pulse VST.

In outputting the scan pulse from the shift register stage, the gate pulse of the gate clock signal CLK input to the shift register stage is used. For example, in the case where the gate clock signal CLK having two different phases, that is, the two-phase gate clock signal CLK, is used, these two gate clock signals CLK are respectively arranged in odd-numbered row lines. It may be input to the shifter register stage positioned in the shifter register stage located in the even-numbered row line. In such a case, the shifter register stage can output a scan pulse having a waveform substantially the same as the gate pulse of the input gate clock signal CLK.

In the gate driver 320 having the above configuration, the shift register circuit 322 may be formed directly on the array substrate of the liquid crystal panel 200. Such a method is called a gate in panel (GIP) method. For example, in the process of forming an array element including the gate wiring GL, the data wiring DL, the switching transistor T, and the like on the array substrate, the shift register circuit 322 may not display the array substrate. It can be formed directly in the area.

On the other hand, the GIP method as described above, for example, the gate driver 320 may be manufactured in the form of an IC, and such an IC type gate driver 320 may be connected to the array substrate. In addition, the gate driver 320 may be configured in various ways.

The data driver 330 supplies the data voltage to the plurality of data wirings DL in response to the data control signal DCS supplied from the timing controller 310.

For example, the input gamma reference voltages Vgamma are divided by a voltage divider circuit to generate grayscale voltages. The gray voltages correspond to each of grays that image data may have.

Accordingly, the data driver 330 outputs the gray level voltage corresponding to the gray level of the input image data Data as the data voltage to the data line DL. The data voltage is output in synchronization with the scan of the gate line GL and input to the corresponding pixel P positioned in the scanned row line.

The backlight 600 serves to supply light to the liquid crystal panel 200. As the backlight 600, a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), and a light emitting diode (LED) may be used.

Hereinafter, a method of adjusting the driving timing of the liquid crystal panel 200 by adaptively adjusting the timing of the control signals GCS and DCS according to the temperature change sensed by the liquid crystal display device 100 will be further described with reference to FIG. 3. Reference will be made in detail.

3 is a diagram schematically illustrating a method of adjusting a timing of a control signal according to a temperature change according to an exemplary embodiment of the present invention.

3, the temperature detector 500 measures the temperature of the surroundings. To this end, a temperature sensor may be used as the temperature detector 500.

The information on the temperature detected by the temperature detector 500 is transmitted to the data storage 400.

The data storage unit 400 may store a plurality of timing data TDa1 to TDa3. As the data storage unit 400, for example, an EEPROM, which is a nonvolatile memory, may be used.

Here, the plurality of timing data TDa1 to TDa3 stored in the data storage unit 400 are matched to each of the plurality of temperature ranges.

For example, in an embodiment of the present invention, temperatures may be divided into first to third temperature ranges. In this case, the data storage unit 400 may include first to third timing data TDa1 to TDa3 corresponding to each of the first to third temperature ranges. Here, for convenience of description, it is assumed that the second temperature range is approximately room temperature range, the first temperature range is a low temperature range lower than the second temperature range, and the third temperature range corresponds to a high temperature range higher than the second temperature range. Can be.

Accordingly, the data storage unit 400 selects the corresponding timing data TDa in response to the temperature information transmitted from the temperature detector 500, and transmits the selected timing data TDa to the timing controller 310. do.

For example, when the measured temperature belongs to the first temperature range, the first timing data TDa1 corresponding to the first temperature range is selected and transmitted to the timing controller 310. On the other hand, when the measured temperature belongs to the second temperature range, the second timing data TDa2 corresponding to the second temperature range is selected and transmitted to the timing controller 310. When the measured temperature is in the third temperature range, the third timing data TDa corresponding to the third temperature range is selected and transmitted to the timing controller 310.

Here, the transmission of the timing data TDa between the timing controller 310 and the data storage 400 may be performed through, for example, I2C communication. As such, when timing data is transmitted through I2C communication, each of the timing controller 310 and the data storage 400 may include an SCL terminal and an SDA terminal for performing I2C communication. Here, the SCL terminal and the SDA terminal correspond to a terminal for clock and data transmission for I2C communication.

Through the SCL terminal and the SDA terminal, the data storage unit 400 can perform I2C communication with the timing controller 310. On the other hand, through such terminals, it is possible to perform I2C communication with a device such as a ROM writing device (not shown) for writing data to the data storage unit 400. In addition, an SCL channel and an SDA channel are provided between the above elements performing I2C communication.

As described above, when the selected timing data TDa is transmitted, the control signal generator 312 of the timing controller 310 receives the control signals GCS and DCS having a timing corresponding to the selected timing data TDa. It can be created.

In this regard, the timing of the gate control signal GCS, for example, the timing of the gate clock signal CLK can be adjusted. That is, the gate pulse output timing of the gate clock signal CLK can be adjusted. As a result, the output timing of the scan pulse output to the gate wiring GL can be adjusted.

On the other hand, the timing of the data control signal DCS, for example, the timing of the data output enable signal may be adjusted. As described above, according to the adjustment of the data output enable signal, the output timing of the data voltage may be adjusted as a result.

As such, by adjusting the timing of the control signals GCS and DCS, the output timing of the scan pulse and the data voltage can be adjusted, and as a result, the driving timing of the liquid crystal panel 200 can be adjusted.

As described above, in the embodiment of the present invention, by adjusting the driving timing of the liquid crystal panel according to the temperature, it is possible to improve the image quality deterioration such as color difference in the conventional low temperature and high temperature driving.

In this regard, in the related art, the liquid crystal panel was driven with the same driving timing regardless of the temperature. However, as a result of confirming through experiments, it was found that the optimum driving timing for improving image quality deterioration such as color difference varies with temperature. That is, when driving in a low temperature and a high temperature environment by the drive timing in a room temperature environment, the low temperature and high temperature color difference similar to a conventional thing generate | occur | produce. However, when the driving timing is changed in a low temperature and high temperature environment, it can be seen that such low temperature and high temperature color difference are significantly reduced.

Therefore, in the embodiment of the present invention, the optimum driving timing according to the temperature is calculated in advance, and the timing data capable of implementing such optimum driving timing is stored in the data storage unit. Accordingly, even when the temperature is changed, it is possible to select timing data capable of implementing the optimum driving timing for the changed temperature. This makes it possible to drive the liquid crystal panel at the optimum timing for the temperature regardless of the temperature change. Therefore, it is possible to improve image degradation such as low temperature and high temperature color difference in the related art.

Hereinafter, as an example of adjusting the timing of the control signal according to the temperature change, the timing of the gate clock signal will be described with reference to Tables 1 and 2 and FIG. 4.

Table 1.

GOE_E Vertical band 300 4 400 3.5 500 3 600 2 680 2

Table 2.

GOE_E Upper pinkish 200 2 300 2 400 2 500 2 600 3 680 3

In Tables 1 and 2, the item "GOE_E" is a gate output enable_end, which indicates the start of output of the gate pulse of the gate clock signal CLK. Here, as the value of "GOE_E" increases, the start point of the output of the gate pulse is delayed. As the value of "GOE_E" decreases, the start point of the gate pulse output starts. That is, referring to FIG. 4, as the value of "GOE_E" increases, the output start point of the gate pulse is pulled to the left. As the value of "GOE_E" decreases, the output start point of the gate pulse is pushed to the right.

Meanwhile, in Table 1, the term "vertical band" indicates a low temperature color difference, and the higher the value, the greater the low temperature color difference. In addition, in Table 2, the term "room temperature pinkish" indicates a high temperature color difference, and the higher the value, the greater the high temperature color difference.

Referring to Table 1, it can be seen that as the delayed start of output of the gate pulse decreases the low temperature color difference. That is, as the output of the scan pulse is delayed, the low temperature color difference is reduced. Therefore, at low temperatures, the low-temperature color difference can be improved by delaying the output timing of the gate pulses.

And, referring to Table 2, it can be seen that as the start of output of the gate pulse becomes faster, the high-temperature color difference decreases. That is, as the output of the scan pulse is faster, the high temperature color difference is reduced. Therefore, at high temperatures, the high-speed color difference can be improved by accelerating the output timing of the gate pulses.

As described above, it can be seen that it is advantageous to improve the image quality as the output of the scan pulse is relatively faster as the temperature is increased, and the output of the scan pulse is relatively late as the temperature is decreased.

On the other hand, the results of Tables 1 and 2 as described above were calculated at a driving frequency of 75 Hz.

In the above-described embodiment of the present invention, the temperature detection unit has been described as an example provided separately from the data storage unit. On the other hand, the temperature detector may be formed to be mounted in the data storage.

Embodiment of the present invention described above is an example of the present invention, it is possible to change freely within the scope included in the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and their equivalents.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.

2 is an equivalent circuit diagram schematically showing the structure of a pixel according to an embodiment of the present invention.

3 is a diagram schematically illustrating a method of adjusting the timing of a control signal according to a temperature change according to an embodiment of the present invention.

4 is a view schematically illustrating a state in which timing of a gate clock signal is adjusted as an example of timing adjustment of a control signal according to a temperature change according to an exemplary embodiment of the present invention.

Description of the Related Art

100: liquid crystal display device 200: liquid crystal panel

310: timing controller 311: data processor

312: control signal generator 320: gate driver

321: level shifter circuit 322: shift register circuit

330: data driver 340: gamma reference voltage generator

400: data storage unit 500: temperature detection unit

600: backlight

TDa: Timing data

Claims

A liquid crystal panel including a gate wiring and a data wiring crossing each other and defining pixels;

A gate driver for outputting a scan pulse to the gate wiring of the liquid crystal panel;

A data driver for outputting a data voltage to the data line of the liquid crystal panel;

A temperature detector for measuring an ambient temperature;

A data storage unit for changing and outputting timing data in response to the measured temperature change;

A timing controller for changing and outputting timings of control signals for controlling the gate driver and the data driver in response to the change of the timing data;

Liquid crystal display comprising a.

The method of claim 1,

Two pixels positioned adjacent to each other along the direction in which the gate wiring extends share data wirings positioned between the two pixels, and are connected to two neighboring gate wirings, respectively.

LCD display device.

The method of claim 2,

The storage wiring overlapping each other with the pixel electrode of the pixel to form a storage capacitor overlaps with the data wiring.

LCD display device.

The method of claim 1,

The gate driver,

A level shifter circuit for level shifting the gate clock signal included in the control signal;

And a shift register circuit configured to receive the level shifted gate clock signal and output the scan pulse.

LCD display device.

The method of claim 4, wherein

The shift register circuit is formed directly on the array substrate of the liquid crystal panel.

LCD display device.

Measuring the ambient temperature;

In response to the measured change in temperature, changing and outputting timing data;

In the timing controller, changing and outputting a timing of a control signal in response to the change of the timing data;

Driving the liquid crystal panel in the gate driver and the data driver in response to the output control signal;

Liquid crystal display device driving method comprising a.

The method of claim 6,

The liquid crystal panel includes a gate wiring and a data wiring crossing each other to define pixels.

Liquid crystal display driving method.

The method of claim 7, wherein

Liquid crystal display driving method.

The method of claim 6,

The gate driver,

Liquid crystal display driving method.

The method of claim 9,

Liquid crystal display driving method.