KR101601092B1 - Liquid crystal display device and method of driving the same - Google Patents

Abstract

According to the present invention, there is provided a liquid crystal display comprising: a gate wiring formed on a liquid crystal panel and extending along a row line; a data wiring crossing the gate wiring and defining a pixel; A gate clock signal generator for generating a gate clock signal; And a gate driver for outputting a scan pulse to the gate line in response to a gate pulse of the gate clock signal, wherein a value of a gate high voltage of the gate line is adapted to a maximum value among data voltages of a corresponding row line A liquid crystal display device is provided.

Description

[0001] The present invention relates to a liquid crystal display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

As a liquid crystal display device, an active matrix type liquid crystal display device in which switching transistors are formed in each of pixels arranged in a matrix form is widely used.

In such an active matrix type liquid crystal display device, when the gate wiring is scanned, a scan pulse is applied to turn on the switching transistor. In synchronism with this, the data voltage is transmitted through the data line and applied to the corresponding pixel. Accordingly, the data voltage is applied to the pixel electrode of the pixel, and the corresponding light is emitted.

On the other hand, in recent years, there is a tendency that a gate driver for outputting a scan pulse to the gate wiring is formed directly on the liquid crystal panel. The method of directly mounting the gate driver on the liquid crystal panel is called a so-called GIP (gate in panel) method.

In the GIP scheme, the gate clock signal is transmitted to the gate driver through the gate clock wiring. In response to the gate pulse of such a gate clock signal, a scan pulse is outputted to the gate wiring. Here, the voltage swing width of the scan pulse is substantially equal to the voltage swing width of the gate pulse.

The turn-on voltage of the scan pulse, for example, the high voltage that turns on the switching transistor of the pixel is determined in consideration of the data voltage charging capability of the switching transistor. In this regard, the range of the data voltage applied to the pixel is in the range of approximately 0.5 V to 10 V when the TN liquid crystal is used. In such a data voltage range, the gradation voltages corresponding to the respective gradations of the image data are distributed. Thus, the gradation voltage corresponding to the gradation of the input image data is output as the data voltage.

In such a case, the case of charging the data voltage of 10 V which is the maximum voltage will be the worst case in terms of the charging ability of the switching transistor. Therefore, it is necessary to set the high voltage of the scan pulse to be sufficiently large in consideration of such the worst case. Thus, for example, a voltage of 25 V can be used as the high voltage of the scan pulse. On the other hand, as the turn-off voltage of the scan pulse, that is, the low voltage, for example, -5V may be used.

In this way, considering the charging of the data voltage, the scan pulse has a large voltage swing width of about 30V. Accordingly, the gate clock signal GCLK is generated so that the gate pulse has a fixed voltage swing width of approximately 30 V, as shown in Fig.

However, the voltage swing width of the gate clock signal must be fixed at a large value, and the gate clock wiring for transferring the gate clock signal has a large RC load. This results in an increase in power consumption due to the output of the gate clock signal.

The present invention has a problem in providing a liquid crystal display device and a driving method thereof that can improve power consumption.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a gate line formed on a liquid crystal panel and extending along a row line; a data line crossing the gate line to define a pixel; A gate clock signal generator for generating a gate clock signal; And a gate driver for outputting a scan pulse to the gate line in response to a gate pulse of the gate clock signal, wherein a value of a gate high voltage of the gate pulse is set to a value corresponding to a maximum value among data voltages of a corresponding row line There is provided a liquid crystal display device adaptively controlled.

Here, the gate clock signal generator may include: a selection switch for selecting one of a plurality of gate high voltages; And a level shifter for generating the gate clock signal using the gate low voltage and the selected gate high voltage.

Wherein the image data of the row line is analyzed to detect a gray level corresponding to a maximum value among the data voltages of the row line and the detected gray level is divided into a plurality of gray levels corresponding to each of the plurality of gate high voltages And the selection switch may be controlled to select a gate high voltage corresponding to the gradation range to which the detected gradation belongs, in accordance with the determination result of the image analysis unit.

The gate driver may be formed on an array substrate of the liquid crystal panel in which the switching transistors of the pixels are formed.

Further comprising a power supply for supplying the plurality of gate high voltages, wherein the power supply includes a plurality of charge pumping portions for generating each of the plurality of gate high voltages, the plurality of charge pumping portions being connected in a cascade manner .

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display including a gate line extending along a row line and a data line crossing the gate line, the data line being formed in a liquid crystal panel and defining a pixel, Generating, at the generator, a gate clock signal; And outputting a scan pulse to the gate line at a gate driver in response to a gate pulse of the gate clock signal, wherein the step of generating the gate clock signal includes: And adaptively adjusting a value of a gate high voltage of the corresponding gate pulse.

Wherein generating the gate clock signal comprises: selecting one of a plurality of gate high voltages; And generating the gate clock signal at the level shifter using the gate low voltage and the selected gate high voltage.

Wherein the step of selecting one of the plurality of gate high voltages comprises the steps of: analyzing image data of the row line to detect a gray level corresponding to a maximum value among the data voltages of the row line; Determining whether the detected gradation falls within a plurality of gradation ranges corresponding to each of the plurality of gate high voltages; And selecting a gate high voltage corresponding to the gradation range to which the detected gradation belongs, according to the determination result.

The gate driver may be formed on an array substrate of the liquid crystal panel in which the switching transistors of the pixels are formed.

Generating the plurality of gate high voltages through each of the plurality of charge pumping portions of the power supply, wherein the plurality of charge pumping portions may be connected in a cascade manner.

In the present invention, the gate high voltage of the gate clock signal can be adaptively adjusted according to the value of the maximum data voltage of the row line. Therefore, power consumption can be improved as compared with the conventional method using a gate clock signal having a fixed voltage swing width regardless of the value of the data voltage.

Moreover, in an embodiment of the present invention, for gate high voltage regulation of the gate clock signal, the power supply has a plurality of charge pumping portions to generate a plurality of gate high voltages. As described above, since a plurality of gate high voltages (VGH1, VGH2) can be generated through a configuration in which a charge pumping section is added without adding a separate power supply element, a cost increase caused by adding a separate power supply element can be reduced .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a view schematically showing a liquid crystal display according to an embodiment of the present invention, FIG. 3 is a view schematically showing the structure of a pixel according to an embodiment of the present invention, FIG. 4 is a cross- FIG. 5 is a schematic diagram illustrating a gate clock signal generator according to an embodiment of the present invention. Referring to FIG.

As shown in the figure, a liquid crystal display 100 according to an embodiment of the present invention includes a liquid crystal panel 200, a driver, and a backlight 600. The driving unit includes a timing control unit 310, a gate driving unit 320, a data driving unit 330, a gamma reference voltage generating unit 340, a gate clock signal generating unit 400, and a power supply unit 500 .

The liquid crystal panel 200 includes two substrates facing each other, for example, an array substrate and an opposite substrate, and a liquid crystal layer positioned between these two substrates.

A plurality of gate lines GL extending in the first direction and a plurality of data lines DL extending in the second direction intersect with each other on the array substrate of the liquid crystal panel 200 to form a matrix A plurality of arranged pixels P are defined.

Referring to FIG. 3, a switching transistor TS connected to a gate line and data lines GL and DL is formed in each pixel P. The switching transistor TS is connected to the pixel electrode. On the other hand, a common electrode is formed corresponding to the pixel electrode, and an electric field is formed between the pixel electrode and the common electrode to drive the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal located between these electrodes constitute a liquid crystal capacitor Clc. Each pixel P further includes a storage capacitor Cst, which serves to store the data voltage applied to the pixel electrode until the next frame.

The timing controller 310 receives a control signal and image data Data from an external system such as a TV system or a video card.

The timing controller 310 generates a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using the input control signal.

The gamma reference voltage generator 340 divides the high voltage and the low voltage to generate a plurality of gamma reference voltages Vgamma and supplies the gamma reference voltages Vgamma to the data driver 330.

The gate driver 320 can sequentially apply the scan pulse to the plurality of gate lines GL in response to the gate control signal GCS supplied from the timing controller 310. [ For example, a plurality of gate lines GL are sequentially selected for each frame, and a scan pulse is output to the selected gate line GL. Accordingly, the switching transistor T located at the row line is turned on by the gate high voltage of the scan pulse. On the other hand, the gate line voltage is supplied to the gate line GL until the next frame scan.

The scan pulse is substantially the same as the gate pulse of the gate clock signal GCLK, which is transmitted from the gate clock signal supply unit 400. [ This will be described in more detail later.

Here, the gate driver 320 according to the embodiment of the present invention may correspond to the gate driver 320 of the GIP scheme. That is, the gate driver 320 may be formed in the process of forming the array elements of the array substrate, for example, the switching transistor TS, the gate line GL, and the data line DL.

The data driver 330 supplies the data voltages to the plurality of data lines DL in response to the data control signal DCS supplied from the timing controller 310. [ For example, for the input gamma reference voltages Vgamma, it divides through the voltage divider circuit to generate the gradation voltages. Such gradation voltages correspond to the respective gradations that the image data Data can have.

In this regard, for example, ²ⁿ gradations (i.e., 0th to ^2n-1 gradations) may be represented when the image data Data is n-bit, and accordingly, ²ⁿ gradation voltages Will be generated. Accordingly, the data driver 330 outputs the gradation voltage corresponding to the gradation of the input image data Data as the data voltage to the data line DL. The data voltage is output in synchronization with the scan of the gate line GL, and is input to the corresponding pixel P located in the scanned row line. Here, the gradation range that can be expressed by the image data (Data) can be called an available gradation range for convenience of explanation.

The backlight 600 serves to supply light to the liquid crystal panel 200. As the backlight 600, a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like can be used.

The power supply unit 500 generates and supplies driving voltages VDD, VGH1, VGH2, and VGL for driving the components of the liquid crystal display device 100 as power supply elements.

For example, in order to generate the gate clock signal GCLK according to the embodiment of the present invention, the gate clock signal generator 400 generates a gate low voltage VGL and a plurality of gate high voltages VGH1 and VGH2, Respectively. Here, for convenience of explanation, it is exemplified that first and second gate pre-charge voltages VGH1 and VGH2 having two different voltage levels are generated and supplied as a plurality of gate high voltages VGH1 and VGH2. The power supply unit 500 generates a driving voltage VDD for driving the data driver 330 and a high potential voltage and a low potential voltage for generating the gamma reference voltages Vgamma. As described above, the power supply unit 500 can generate and supply driving voltages for driving the components of the liquid crystal display device 100 to the corresponding components.

Here, as an example of a method by which the power supply unit 500 generates the first and second gate high voltages VGH1 and VGH2, the description will be made with reference to FIG.

Referring to FIG. 4, the power supply unit 500 may include a power accumulation element 510 and a plurality of charge-pumping units 511a and 511b. The power integrating device 510 receives the input voltage VIN and generates the driving voltage VDD. For example, the voltage output through the power accumulating element 510 passes through the diode D3 and is output as the driving voltage VDD.

The plurality of charge pumping units 511a and 511b, for example, the first and second charge pumping units 511a and 511b are connected in a cascade manner. The differential pumping units 511a and 511b perform a charging pumping operation on the output voltage of the inductor L and the driving voltage VDD to generate the first and second gate high voltages VGH1 and VGH2 do. In order to perform such a charge pumping operation, each of the first and second charge pumping units 511a and 511b includes diodes D1_1, D1_2 and D2_1 and D2_2 and capacitors C1_1, C1_2 and C2_1 and C2_2 can do. Here, the capacitors C1_2 and C2_2 of the first and second charge pumping units 511a and 511b function as charge pumping capacitors.

Each of the first and second charge pumping units 511a and 511b having such a configuration can output the first and second gate high voltages VGH1 and VGH2 at the output terminal. Here, since the first charge pumping unit 511a is located at the rear end in the cascade connection, it can output a higher output voltage VGH1 than the output voltage VGH2 of the second charge pumping unit 511b.

As described above, in the embodiment of the present invention, it is possible to generate a plurality of gate high voltages VGH1 and VGH2 through a configuration in which a charge pumping unit is added without adding a separate power supply element. Accordingly, it is possible to reduce a cost increase that may occur by adding a separate power supply element.

The gate clock signal generator 400 generates at least one gate clock signal GCLK and supplies the gate clock signal GCLK to the gate drive circuit 320. In the embodiment of the present invention, a process of adaptively adjusting the gate high voltage of the gate pulse through the analysis of the line line image in the image analyzing unit 311 will be described in more detail.

5, the gate clock signal generator 400 may include at least one level shifter 410. [ The level shifter 410 may include a level shifter 411 and a selection switch 412 to generate a gate clock signal GCLK.

The level shifter 411 shifts the level of the input clock signal CLK_IN input to the input terminal and outputs the gate clock signal GCLK. In order to perform the level shifting operation, the level shifter 411 receives the gate high voltages VGH1 and VGH2 at the first power input terminal and receives the gate low voltage VGL at the second power input terminal.

The input clock signal CLK_IN input to the input terminal has a form in which the low voltage and the high voltage alternate.

For this input clock signal CLK_IN, the level shifter 410 level shifts the low voltage of the input clock signal CLK_IN to the gate low voltage VGL.

On the other hand, the high voltage of the input clock signal CLK_IN is level-shifted to one of a plurality of gate high voltages, for example, the first and second gate high voltages VGH1 and VGH2. Here, the process of selecting one of the first and second gate high voltages VGH1 and VGH2 is performed through image analysis.

Such a gate high voltage selection will be described with further reference to FIGS. 6 and 7. FIG. 6 and 7 illustrate an example of a method for adjusting a gate high voltage of a gate clock signal according to an embodiment of the present invention.

For convenience of explanation, it is assumed that a liquid crystal display driven in a normally white mode is used. In the normally white mode liquid crystal display device, the voltage level of the gray scale voltage corresponding to the white gradation as the maximum gradation is the lowest, and the voltage level of the gray scale voltage corresponding to the black gradation as the minimum gradation is the highest. For convenience of explanation, the usable gradation range can be divided into a plurality of gradation ranges. For example, it is assumed that the gradation range is divided into a first gradation range GR1 and a second gradation range GR2. Here, it is assumed that the first gradation range GR1 is a relatively high gradation range and the second gradation range GR2 is a relatively low gradation range.

Referring to FIG. 7, among the entire area of the screen S displaying the image, the area A is entirely white. Then, the B region displays a part of black. Accordingly, a data voltage of white gradation is inputted to the pixels of the row lines belonging to the area A, and a data voltage of the black gradation is inputted to some of the pixels of the row lines belonging to the area B.

In such a case, the maximum data voltage of each row line belonging to the area A is the gradation voltage representing the white gradation, and the maximum data voltage of each row line belonging to the area B is the gradation voltage representing the black gradation.

Here, since the gradation voltage representing the black gradation has a relatively high voltage value, it is preferable that the gate high voltage of the scan pulse applied to the row line also has a relatively high value in consideration of the charging ability of the data voltage will be. On the other hand, since the gradation voltage representing the white gradation has a relatively low voltage value, even if the gate high voltage of the scan pulse applied to the corresponding row line has a relatively low value, charging of the data voltage is not much difficult .

Therefore, in the embodiment of the present invention, a scan pulse having a relatively high gate voltage, for example, the first gate high voltage VGH1, can be applied to a row line to which a relatively high data voltage is applied. On the other hand, for a row line to which a relatively low data voltage is applied, a scan pulse having a relatively low gate high voltage, for example, a second gate high voltage VGH2, may be applied.

Such adaptive adjustment of the gate high voltage of the scan pulse can be performed by adjusting the gate high voltage of the gate pulse of the gate clock signal GCLK that determines the scan pulse.

For this purpose, the image analyzing section 311 detects gradations corresponding to the maximum data voltages of the respective row lines, and determines whether the detected gradation falls within a certain gradation range, for example, in the first and second gradation ranges GR1 and GR2 Determine where you belong. The selection control signal SEL corresponding to the selection control signal SEL is output from the timing control unit 310 so that the selection switch 412 is turned on at the first gate high voltage VGH1). On the other hand, if it is determined to belong to the second gradation range GR2 as a result of the determination, the selection control signal SEL corresponding to the selected selection control signal SEL is outputted so that the selection switch 412 selects the second gate high voltage VGH2.

Accordingly, the gate pulse corresponding to the A region will have the second gate high voltage VGH2, and the gate pulse corresponding to the B region will have the first gate high voltage VGH1.

That is, the image analyzing unit 311 may analyze the image data for each of the row lines of the A region, and detect that the maximum data voltage of each row line is a white tone. It can be determined that such a white gradation belongs to the second gradation range GR2.

According to the analysis result of the image analysis unit 311, the timing control unit 310 will output the corresponding selection control signal SEL. Accordingly, the selection switch 412 will select the second gate high voltage VGH2. As a result, the output gate pulse will have the second gate high voltage VGH2 as the gate high voltage. Thus, for the row lines of the A region, a scan pulse having the second gate high voltage VGH2 will be output.

On the other hand, for the B region, the image analyzing unit 311 can analyze the image data for each of the row lines to detect that the maximum data voltage of each row line is a black tone. Then, it can be determined that such a black gradation belongs to the first gradation range GR1.

According to the analysis result of the image analysis unit 311, the timing control unit 310 will output the corresponding selection control signal SEL. Accordingly, the selection switch 412 will select the first gate high voltage VGH1. As a result, the output gate pulse will have the first gate high voltage VGH1. Thus, for the row lines of the B region, a scan pulse having the first gate high voltage VGH1 will be output.

As described above, the image data of each row line is analyzed, and the gate high voltage corresponding to the gradation range to which the gradation corresponding to the maximum data voltage of the row line belongs can be selected. As a result, the gate pulse corresponding to each row line has the selected gate pre-discharge pressure, so that the scan pulse having the selected gate high voltage can be outputted to the corresponding row line. Here, the selected gate high voltage corresponds to a voltage set so that the maximum data voltage of the corresponding row line can be sufficiently charged to the corresponding pixel.

As such, the gate high voltage of the gate clock signal can be adaptively adjusted according to the value of the maximum data voltage of the row line. That is, the voltage swing width of the gate pulse can be adaptively adjusted according to the value of the data voltage of the corresponding row line. Therefore, the liquid crystal display according to the embodiment of the present invention can improve the power consumption as compared with the conventional method using a gate clock signal having a fixed voltage swing width regardless of the value of the data voltage.

Moreover, in an embodiment of the present invention, for gate high voltage regulation of the gate clock signal, the power supply has a plurality of charge pumping portions to generate a plurality of gate high voltages. As described above, since a plurality of gate high voltages (VGH1, VGH2) can be generated through a configuration in which a charge pumping section is added without adding a separate power supply element, a cost increase caused by adding a separate power supply element can be reduced .

Hereinafter, an example of a method of outputting a scan pulse to gate wirings using a gate clock signal according to an embodiment of the present invention will be described with reference to FIG.

8 is a view schematically showing a gate driver according to an embodiment of the present invention.

Referring to FIG. 8, the gate driver 320 may include a shift register unit 321. The shift register unit 321 may include shift register stages SR1 to SR4 corresponding to a plurality of gate lines GL1 to GL4, respectively.

In this case, the first shift register stage SR1 outputs the scan pulse to the first gate line GL in response to the gate control signal GCS, for example, the gate start pulse GST. Thereafter, in response to the output of the shift register stages SR1 to SR3 located at the preceding stage, the shift register stages SR2 to SR4 positioned at the rear stage output scan pulses. In this way, the shift register stages SR1 to SR4 can sequentially output scan pulses to the gate lines GL1 to GL4.

In order to output the scan pulse in this way, an n-phase gate clock signal, for example, a two-phase gate clock signal, that is, first and second gate clock signals GCLK1 and GCLK2, may be used.

In such a case, the first and second gate clock signals GCLK1 and GCLK2 will have phases opposite to each other. For example, if the first gate clock signal GCLK1 is in a high state, the second gate clock signal GCLK will be in a low state.

In response to the gate pulse of the first gate clock signal GCLK1, the shift register stages SR1 and SR3 to which the first gate clock signal GCLK1 is input are supplied with a scan pulse substantially the same as the gate pulse, And output to the wirings GL1 and GL3. The shift register stages SR2 and SR4 to which the second gate clock signal GCLK2 is input are connected to the gate lines GL2 and GL4 in response to the gate pulse of the second gate clock signal GCLK. .

Here, the gate high voltages of the gate pulses of the first and second gate clock signals GCLK1 and GCLK2 may be adaptively adjusted according to the maximum value of the data high voltage of the corresponding row line, as described above . In generating the first and second gate clock signals GCLK1 and GCLK2, the gate clock signal generator 400 may include two level shifter units 410, for example.

On the other hand, when the gate driver 320 is formed directly on the liquid crystal panel 200, that is, in the case of the GIP method, the transistors provided in the shift register stages SR1 to SR4 are connected to the switching transistor TS of the pixel P Formation can be formed in the process. For example, in the case where the switching transistor TS is formed using amorphous silicon (a-Si), the transistors of the shift register stages SR1 to SR4 may also be formed using amorphous silicon. Of course, in forming these transistors, crystalline silicon (poly-Si) may also be used.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

1 shows a conventional gate clock signal roll.

2 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.

3 schematically illustrates the structure of a pixel according to an embodiment of the present invention.

Figure 4 schematically shows a power supply according to an embodiment of the invention;

5 is a schematic view of a gate clock signal generator according to an embodiment of the present invention;

Figures 6 and 7 illustrate an example of a method for adjusting a gate high voltage of a gate clock signal in accordance with an embodiment of the present invention.

8 is a schematic view of a gate driver according to an embodiment of the present invention;

Description of the Related Art

400: Gate clock signal generator 410: Level shifter

411: level shifter 412: selection switch

VGH1: first gate high voltage VGH2: second gate high voltage

VGL: Gate low voltage CLK_IN: Input clock signal

GCLK: Gate clock signal

Claims (10)

A gate wiring formed on the liquid crystal panel and extending along the row line; a data wiring crossing the gate wiring and defining a pixel; A gate clock signal generator for generating a gate clock signal; And a gate driver for outputting a scan pulse to the gate line in response to a gate pulse of the gate clock signal, The value of the gate high voltage of the gate pulse is adaptively adjusted according to the maximum value among the data voltages of the corresponding row line Liquid crystal display device. The method according to claim 1, Wherein the gate clock signal generator comprises: A selection switch for selecting one of a plurality of gate high voltages; A level shifter for generating the gate clock signal by using the gate low voltage and the selected gate high voltage, Containing Liquid crystal display device. 3. The method of claim 2, The image data of the row line is analyzed to detect a gray level corresponding to a maximum value of the data voltages of the row line, And determines whether the detected gradation falls within a plurality of gradation ranges corresponding to each of the plurality of gate high voltages Further comprising an image analysis unit, According to the determination result of the image analysis unit, the selection switch is controlled to select a gate high voltage corresponding to the gradation range to which the detected gradation belongs Liquid crystal display device. The method according to claim 1, Wherein the gate driver is formed on an array substrate of the liquid crystal panel in which the switching transistors of the pixels are formed Liquid crystal display device. 3. The method of claim 2, Further comprising a power supply for supplying the plurality of gate high voltages, Wherein the power supply comprises a plurality of charge pumping portions for generating each of the plurality of gate high voltages, The plurality of charge pumping units are connected in a cascade fashion Liquid crystal display device. A driving method of a liquid crystal display including a gate wiring formed on a liquid crystal panel and extending along a row line and a data wiring crossing the gate wiring and defining a pixel, Generating a gate clock signal at a gate clock signal generator; And outputting a scan pulse to the gate wiring in a gate driver in response to a gate pulse of the gate clock signal, Wherein generating the gate clock signal comprises: Adaptively adjusting the value of the gate high voltage of the corresponding gate pulse in accordance with the maximum of the data voltages of the row line A method of driving a liquid crystal display device. The method according to claim 6, Wherein generating the gate clock signal comprises: Selecting one of a plurality of gate high voltages; Further comprising generating the gate clock signal at a level shifter using a gate low voltage and the selected gate high voltage A method of driving a liquid crystal display device. 8. The method of claim 7, Wherein selecting one of the plurality of gate high voltages comprises: Analyzing image data of the row line to detect a gray level corresponding to a maximum value of the data voltages of the row line; Determining whether the detected gradation falls within a plurality of gradation ranges corresponding to each of the plurality of gate high voltages; And selecting a gate high voltage corresponding to a gradation range to which the detected gradation belongs, in accordance with the determination result A method of driving a liquid crystal display device. The method according to claim 6, Wherein the gate driver is formed on an array substrate of the liquid crystal panel in which the switching transistors of the pixels are formed A method of driving a liquid crystal display device. 8. The method of claim 7, Generating the plurality of gate high voltages through each of the plurality of charge pumping portions of the power supply, The plurality of charge pumping units are connected in a cascade fashion A method of driving a liquid crystal display device.

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