KR101630340B1 - Liquid crystal display device and method of driving the same - Google Patents

Abstract

The present invention relates to an image processing apparatus including a temperature detection unit for measuring a temperature around a subject, a data storage unit for changing timing data in response to a change in the measured temperature, and a control unit for controlling the gate drive unit and the data drive unit And a timing control section for changing the timing of the control signal to be supplied to the liquid crystal display device.

Description

[0001] The present invention relates to a liquid crystal display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

As a liquid crystal display device, an active matrix type liquid crystal display device in which switching transistors are formed in each of pixels arranged in a matrix form is widely used.

In the active matrix type liquid crystal display device, when the gate wiring is scanned, a scan pulse is applied to turn on the switching transistor. In synchronism with this, the data voltage is transmitted through the data line and applied to the corresponding pixel. Accordingly, the data voltage is applied to the pixel electrode of the pixel, and the corresponding light is emitted.

In recent years, various technologies have been applied to such a liquid crystal display device. For example, a method has been proposed in which neighboring pixels along the row direction share a data line, thereby reducing the number of data lines and driving circuits therefor. Further, a method has been proposed in which a storage wiring constituting a pixel electrode and a storage capacitor is formed under the data wiring.

However, when these technologies are applied to a liquid crystal display device to display an image, a color difference is generated at a low temperature and a high temperature, and image quality is deteriorated. For example, when images are displayed at a low temperature, it has been confirmed that vertical stripes occur along the direction in which the data lines extend. It has been confirmed that when an image is displayed at a high temperature, a pinkish phenomenon occurs in which some regions, for example, an upper region of the image are pink.

Although the cause of such phenomena is not clearly understood, it appears to be due to the voltage charge variation between the pixels of the liquid crystal panel. That is, the low-temperature color difference at which the vertical strips are generated is caused by the resistance difference between the data lines and the influence of the voltage charging deviation due to the coupling between the data lines and the storage lines. The high-temperature color difference at which the pink-key phenomenon occurs is caused by the influence of the voltage charge variation due to the decrease in the optimal common voltage sensed by the liquid-crystal panel, as the pixel voltage drop amount DELTA Vp increases at high temperature.

At present, there is no effective way to improve image quality due to the temperature change as described above.

The present invention has a problem in providing a liquid crystal display device and a driving method thereof capable of improving image quality deterioration caused by a temperature change.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel including gate wirings and data wirings crossing each other to define pixels; A gate driver for outputting a scan pulse to a gate wiring of the liquid crystal panel; A data driver for outputting a data voltage to a data line of the liquid crystal panel; A temperature detecting unit for measuring a temperature of the surroundings; A data storage unit for changing and outputting the timing data in response to the measured temperature change; And a timing controller for changing the timing of the control signal for controlling the gate driver and the data driver in response to the change of the timing data.

Here, two pixels positioned adjacent to each other along the extending direction of the gate line share a data line located between the two pixels, and may be connected to two neighboring gate lines, respectively.

The storage wiring which overlaps the pixel electrode of the pixel and constitutes the storage capacitor can overlap with the data wiring.

Wherein the gate driver includes: a level shifter circuit for receiving a gate clock signal included in the control signal to level shift the gate clock signal; And a shift register circuit receiving the level-shifted gate clock signal and outputting the scan pulse.

The shift register circuit may be formed directly on the array substrate of the liquid crystal panel.

In another aspect, the present invention provides a method comprising: measuring ambient temperature; Changing and outputting the timing data in response to the change in the measured temperature; Changing the timing of the control signal in response to the change of the timing data and outputting the timing data; And driving the liquid crystal panel in the gate driver and the data driver in response to the output control signal.

Here, the liquid crystal panel includes a gate wiring and a data wiring which intersect with each other to define a pixel, and two pixels located adjacent to each other along a direction in which the gate wiring extends extend the data between the two pixels And can be connected to two neighboring gate wirings, respectively.

The story main line that overlaps the pixel electrode of the pixel and constitutes a storage capacitor can overlap the data line.

Wherein the gate driver includes: a level shifter circuit for receiving a gate clock signal included in the control signal to level shift the gate clock signal; And a shift register circuit receiving the level-shifted gate clock signal and outputting the scan pulse.

The shift register circuit may be formed directly on the array substrate of the liquid crystal panel.

In the present invention, the optimal drive timing according to the temperature is calculated in advance, and the timing data capable of implementing such optimum drive timing is stored in the data storage unit.

Thereby, even when the temperature is changed, it becomes possible to select the timing data that can realize the optimum drive timing for the changed temperature. This makes it possible to drive the liquid crystal panel at the optimum timing with respect to the temperature regardless of the temperature change. Therefore, it is possible to improve the deterioration of the image quality due to the temperature change.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram schematically illustrating the structure of a pixel according to an embodiment of the present invention.

As shown in the figure, a liquid crystal display device 100 according to an embodiment of the present invention includes a liquid crystal panel 200, a driving circuit, and a backlight 600. Here, the driving circuit includes a timing control unit 310, a gate driving unit 320, a data driving unit 330, a gamma reference voltage generating unit 340, a data storage unit 400, a temperature detecting unit 500, . ≪ / RTI >

The liquid crystal panel 200 includes two substrates facing each other, for example, an array substrate and an opposite substrate, and a liquid crystal layer positioned between these two substrates.

A plurality of gate lines GL extending in the first direction, e.g., a row direction, and a plurality of data lines DL extending in the second direction, for example, in the column direction are formed on the array substrate of the liquid crystal panel 200, A plurality of pixels P arranged in a matrix form are defined.

Referring to FIG. 2, each pixel P is formed with a switching transistor T connected to a gate line and data lines GL and DL. The switching transistor T is connected to the pixel electrode. On the other hand, a common electrode is formed corresponding to the pixel electrode. When a voltage is applied to the pixel electrode and the common electrode, an electric field is formed between the pixel electrode and the common electrode, thereby driving the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal located between these electrodes constitute a liquid crystal capacitor Clc.

Each pixel P further includes a storage capacitor Cst, which serves to store the data voltage applied to the pixel electrode until the next frame. Such a storage capacitor Cst may be composed of a pixel electrode overlapping with the storage capacitor Cst and a storage wiring portion.

Here, in the liquid crystal panel 200 according to the embodiment of the present invention, the pixels P adjacent to each other along the row direction can share the data line DL located between the pixels P .

1, among pixels P adjacent to each other along the row direction, a pixel located on one side of the data line DL, for example, on the left side is referred to as a first pixel P1, For example, a pixel positioned on the right side is referred to as a second pixel P2. In this case, the first pixel P1 and the second pixel P2 are connected to the neighboring gate lines GL, respectively. That is, the first pixel P1 is connected to the gate line GL at the previous stage, and the second pixel P2 is connected to the gate line GL at the subsequent stage.

As described above, for one data line DL, as two neighboring pixels P share this data line DL, the number of data lines DL is reduced to about half . Furthermore, as the number of data lines DL can be reduced, the number of data ICs formed in the data driving circuit 300 driving the data lines DL can also be reduced to about half. As such, as the number of data lines DL and the number of elements driving the same decreases, the manufacturing cost for these data lines can be reduced.

In the liquid crystal panel 200 according to the embodiment of the present invention, a storage line may be formed under the data line DL and overlapped with the data line DL. The storage wiring having such a structure is formed so as to overlap with the pixel electrode so that the storage capacitor Cst can be formed as described above.

The timing control unit 310 may include a data processing unit 311 and a control signal generation unit 312.

The data processing unit 311 arranges and outputs the input image data Data. The image data Data output in this manner is supplied to the data driver 330.

The control signal generating unit 312 can generate various control signals for controlling the driving circuit of the liquid crystal display device 100. [ A data control signal DCS for controlling the data driving circuit 330 and a gate control signal GCS for controlling the gate driving circuit 320 are generated.

These control signals GCS and DCS are generated with reference to the timing data TDa. For example, the timing of the control signals GCS and DCS can be adjusted in accordance with the timing data TDa. The timing data TDa used for generating the control signals GCS and DCS is stored in the data storage unit 400 as described above. The timing control unit 310 receives the timing data TDa stored in the data storage unit 400 and can output the control signals GCS and DCS corresponding to the input timing data TDa.

The timing data TDa input to the timing control unit 310 can be changed according to the temperature sensed by the liquid crystal display device 100. [ For example, in response to the temperature measured through the temperature detection unit 500, the corresponding timing data TDa can be output from the data storage unit 400.

When the timing data TDa is changed in accordance with the temperature change, the timing of the output control signals GCS and DCS is also changed. Accordingly, the driving timing of the liquid crystal panel 200 is changed. As described above, a method for adaptively adjusting the timing of the control signals GCS and DCS in accordance with the temperature change and consequently adjusting the driving timing of the liquid crystal panel 200 will be described in detail later.

The gamma reference voltage generator 340 divides the high voltage and the low voltage to generate a plurality of gamma reference voltages Vgamma and supplies the gamma reference voltages Vgamma to the data driver 330.

The gate driver 320 sequentially applies scan pulses to the plurality of gate lines GL in response to the gate control signal GCS.

For example, a plurality of gate lines GL are sequentially scanned every frame, and scan pulses are output to the gate lines GL during each scan period. Accordingly, in response to the turn-on voltage of the scan pulse, for example, the gate high voltage, the switching transistor T is turned on.

On the other hand, a turn-off voltage, for example, a gate low voltage is supplied to the gate line GL until the next frame scan. As such, during a period in which the gate-low voltage is supplied, the switching transistor T is turned off.

Thus, the gate driver 320 outputs a gate voltage to the gate line GL to drive the gate line GL.

The gate driver 320 may include a level shifter circuit 321 and a shift register circuit 322.

The level shifter circuit 321 level shifts the voltage level of, for example, at least one gate clock signal CLK as an input gate control signal GCS. For example, the level shifter circuit 321 shifts the voltage level between the low voltage and the high voltage of the inputted gate clock signal (CLK) by the gate high voltage and the gate low voltage.

On the other hand, it becomes possible to perform a level shift operation for the gate start pulse VST, for example, as the input gate control signal GCS.

As described above, the gate clock signal CLK and the gate start pulse VST level-shifted and outputted through the level shifter circuit 321 can be input to the shift register circuit 322. [

The shift register circuit 322 may include a plurality of shift register stages for outputting a gate voltage to each of the gate lines GL. For example, each shift register stage receives a gate voltage output from the shift register stage located at the previous stage, and outputs a scan pulse in response to the gate voltage. Here, the shift register stage located on the first row line outputs a scan pulse to the gate wiring GL in response to the gate start pulse VST.

In outputting the scan pulse at the shift register stage, a gate pulse of the gate clock signal CLK input to the shift register stage is used. For example, in the case where a gate clock signal CLK having two different phases, that is, a two-phase gate clock signal CLK, is used, these two gate clock signals CLK are respectively connected to odd- And may be input to the shifter register stage located at the shifter register stage and the shifter register stage located at the even-numbered row line. In such a case, the shifter register stage can output a scan pulse having a waveform substantially the same as the gate pulse of the inputted gate clock signal (CLK).

In the gate driver 320 having the above structure, the shift register circuit 322 can be formed directly on the array substrate of the liquid crystal panel 200, which is called a GIP (gate in panel) scheme. For example, in the process of forming the array elements including the gate lines GL, the data lines DL, the switching transistors T, and the like on the array substrate, the shift register circuit 322 is used to display Region. ≪ / RTI >

As an example of the GIP method, the gate driver 320 may be formed in the form of an IC, and the gate driver 320 may be connected to the array substrate. In addition, the gate driver 320 can be configured in various ways.

The data driver 330 supplies the data voltages to the plurality of data lines DL in response to the data control signal DCS supplied from the timing controller 310. [

For example, for the input gamma reference voltages Vgamma, it divides through the voltage dividing circuit to generate gradation voltages. Such gradation voltages correspond to each of the gradations that the image data (Data) can have.

Accordingly, the data driver 330 outputs the gradation voltage corresponding to the gradation of the input image data Data as the data voltage to the data line DL. Such a data voltage is output in synchronization with the scan of the gate line GL, and is input to the corresponding pixel P located in the scanned row line.

The backlight 600 serves to supply light to the liquid crystal panel 200. As the backlight 600, a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), and a light emitting diode (LED) may be used.

Hereinafter, a method for adjusting the timing of the control signals GCS and DCS according to the temperature change sensed by the liquid crystal display device 100 and adjusting the driving timing of the liquid crystal panel 200 will be described with reference to FIG. 3 Will be described in detail with reference to FIG.

3 is a view schematically showing a method of adjusting the timing of a control signal according to a temperature change according to an embodiment of the present invention.

Referring to FIG. 3, the temperature detector 500 measures the temperature of its surroundings. For this purpose, a temperature sensor may be used as the temperature detector 500.

The information on the temperature detected through the temperature detector 500 is transmitted to the data storage unit 400.

The data storage unit 400 may store a plurality of timing data TDa1 to TDa3. As the data storage unit 400, for example, an EEPROM which is a nonvolatile memory may be used.

Here, the plurality of timing data TDa1 to TDa3 stored in the data storage unit 400 are matched to each of a plurality of temperature ranges.

For example, in embodiments of the present invention, temperatures can be divided into first to third temperature ranges. In such a case, the data storage unit 400 may be provided with first to third timing data TDa1 to TDa3 corresponding to the first to third temperature ranges, respectively. Here, for convenience of explanation, it is assumed that the second temperature range is approximately the room temperature range, the first temperature range is the low temperature range lower than the second temperature range, and the third temperature range corresponds to the high temperature range higher than the second temperature range .

The data storage unit 400 selects the corresponding timing data TDa in response to the temperature information transmitted from the temperature detector 500 and transmits the selected timing data TDa to the timing controller 310 do.

For example, when the measured temperature falls within the first temperature range, the first timing data TDa1 corresponding to the first temperature range is selected and transmitted to the timing control section 310. [ On the other hand, when the measured temperature belongs to the second temperature range, the second timing data TDa2 corresponding to the second temperature range is selected and transmitted to the timing control section 310. [ When the measured temperature belongs to the third temperature range, the third timing data TDa corresponding to the third temperature range is selected and transmitted to the timing control section 310. [

Here, the transmission of the timing data TDa between the timing controller 310 and the data storage unit 400 can be performed through, for example, I2C communication. In this manner, when the transmission of the timing data through the I2C communication is performed, the timing controller 310 and the data storage unit 400 may each have an SCL terminal and an SDA terminal for performing I2C communication. Here, the SCL terminal and the SDA terminal correspond to a clock for I2C communication and a terminal for data transmission.

Through the SCL terminal and the SDA terminal, the data storage unit 400 can perform I 2 C communication with the timing controller 310. Meanwhile, through such terminals, it is possible to perform I2C communication with devices such as a ROM writing device (not shown) for writing data in the data storage unit 400. [ In addition, an SCL channel and an SDA channel are provided between the above-described elements for performing I2C communication as described above.

As described above, when the selected timing data TDa is transmitted, the control signal generating unit 312 of the timing control unit 310 outputs the control signals GCS and DCS having the timings corresponding to the selected timing data TDa .

In this regard, it becomes possible to adjust the timing of the gate control signal GCS, for example, the timing of the gate clock signal CLK. That is, it is possible to adjust the gate pulse output timing of the gate clock signal CLK. As a result, the output timing of the scan pulse output to the gate line GL can be adjusted.

Meanwhile, the timing of the data control signal DCS, for example, the timing of the data output enable signal may be adjusted. As a result, the output timing of the data voltage can be adjusted in accordance with the adjustment of the data output enable signal.

As such, by adjusting the timing of the control signals GCS and DCS, the timing of outputting the scan pulse and the data voltage can be adjusted, and as a result, the driving timing of the liquid crystal panel 200 can be controlled.

As described above, in the embodiment of the present invention, by adjusting the driving timing of the liquid crystal panel in accordance with the temperature, it is possible to improve the image quality deterioration as in the case of the conventional color temperature difference during low temperature and high temperature driving.

In this regard, conventionally, the liquid crystal panel was driven at the same driving timing regardless of the temperature. However, as a result of checking through experiments, it has been found that the optimal driving timing for improving image quality deterioration such as color difference is different depending on the temperature. That is, when driving is performed in a low-temperature and high-temperature environment at a driving timing in a room-temperature environment, there occurs a low-temperature and high-temperature color difference as in the conventional case. However, when the driving timing is changed in a low-temperature and high-temperature environment, it has become clear that such difference in color temperature and high-temperature hue significantly decreases.

Therefore, in the embodiment of the present invention, the optimal drive timing according to the temperature is calculated in advance, and the timing data capable of implementing such optimum drive timing is stored in the data storage unit. Thereby, even when the temperature is changed, it becomes possible to select the timing data that can realize the optimum drive timing for the changed temperature. This makes it possible to drive the liquid crystal panel at the optimum timing with respect to the temperature regardless of the temperature change. Therefore, it is possible to improve the deterioration of the image quality as in the case of the conventional low-temperature and high-temperature color difference.

Hereinafter, with reference to adjusting the timing of the gate clock signal, as an example of timing adjustment of the control signal according to the temperature change, Tables 1 and 2 and FIG. 4 will be further described.

Table 1.

GOE_E Vertical band 300 4 400 3.5 500 3 600 2 680 2

Table 2.

GOE_E Upper pinkish 200 2 300 2 400 2 500 2 600 3 680 3

In Table 1 and 2, the item "GOE_E" indicates the start of output of the gate pulse of the gate clock signal (CLK) as Gate Output Enable_End. Here, as the value of "GOE_E" increases, the output start timing of the gate pulse is delayed. As the value of "GOE_E" decreases, the output start timing of the gate pulse becomes faster. That is, referring to FIG. 4, as the value of "GOE_E" increases, the output start point of the gate pulse is pulled to the left. As the value of "GOE_E" decreases, the output start point of the gate pulse is pushed to the right.

On the other hand, in Table 1, the item "vertical band" indicates the difference in low temperature color difference, and the higher the value, the larger the difference in low temperature color difference. In Table 2, the item "normal temperature pinkish" indicates the difference in the high temperature color difference, and the higher the value, the larger the difference in the high temperature color difference.

Referring to Table 1, it can be seen that as the start of the output of the gate pulse is delayed, the difference in low-temperature color difference decreases. That is, as the output of the scan pulse is delayed, the difference in low-temperature color difference decreases. Therefore, at a low temperature, by delaying the output timing of the gate pulse, it becomes possible to improve the low-temperature color difference.

Referring to Table 2, it can be seen that as the start of the output of the gate pulse becomes faster, the difference in high-temperature color difference decreases. That is, as the output of the scan pulse increases, the difference in the high-temperature color difference decreases. Therefore, at a high temperature, the output timing of the gate pulse is made faster, whereby the high-temperature color difference can be improved.

As described above, it can be seen that the output of the scan pulse relatively increases as the temperature increases and that the output of the scan pulse becomes relatively slow as the temperature decreases.

On the other hand, the results shown in Tables 1 and 2 above were calculated at a driving frequency of 75 Hz.

In the embodiment of the present invention, the temperature detector is provided separately from the data storage. On the other hand, the temperature detection unit may be formed to be mounted in the data storage unit.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.

2 is an equivalent circuit diagram schematically showing the structure of a pixel according to an embodiment of the present invention.

3 schematically shows a method of adjusting the timing of a control signal according to a temperature change according to an embodiment of the present invention.

FIG. 4 is a view schematically showing a timing of a gate clock signal as an example of timing adjustment of a control signal according to a temperature change according to an embodiment of the present invention; FIG.

Description of the Related Art

100: liquid crystal display device 200: liquid crystal panel

310: timing control unit 311: data processing unit

312: control signal generator 320: gate driver

321: Level shifter circuit 322: Shift register circuit

330: Data driver 340: Gamma reference voltage generator

400: Data storage unit 500: Temperature detection unit

600: Backlight

TDa: timing data

Claims (10)

A liquid crystal panel including a gate wiring and a data wiring crossing each other and defining a pixel; A gate driver for outputting a scan pulse to a gate wiring of the liquid crystal panel; A data driver for outputting a data voltage to a data line of the liquid crystal panel; A temperature detecting unit for measuring a temperature of the surroundings; A data storage unit for changing and outputting the timing data in response to the measured temperature change; A timing controller for changing timing of a control signal for controlling the gate driver and the data driver in response to the change of the timing data, And the liquid crystal display device. The method according to claim 1, Two pixels located adjacent to each other along the extending direction of the gate line share a data line located between the two pixels and are connected to two neighboring gate lines Liquid crystal display device. 3. The method of claim 2, Wherein the storage wiring that overlaps the pixel electrode of the pixel and constitutes a storage capacitor overlaps with the data wiring Liquid crystal display device. The method according to claim 1, Wherein the gate driver comprises: A level shifter circuit for receiving a gate clock signal included in the control signal and level shifting the gate clock signal; And a shift register circuit receiving the gate clock signal output from the level shifter circuit and outputting the scan pulse Liquid crystal display device. 5. The method of claim 4, Wherein the shift register circuit is formed directly on the array substrate of the liquid crystal panel Liquid crystal display device. Measuring the ambient temperature; Changing and outputting the timing data in response to the change in the measured temperature; Changing the timing of the control signal in response to the change of the timing data and outputting the timing data; In the gate driver and the data driver, driving the liquid crystal panel in response to the output control signal And driving the liquid crystal display device. The method according to claim 6, Wherein the liquid crystal panel includes a gate wiring and a data wiring which cross each other to define a pixel, Two pixels located adjacent to each other along the extending direction of the gate wiring share a data wiring located between the two pixels and are connected to two neighboring gate wirings A method of driving a liquid crystal display device. 8. The method of claim 7, Wherein the storage wiring that overlaps the pixel electrode of the pixel and constitutes a storage capacitor overlaps with the data wiring A method of driving a liquid crystal display device. The method according to claim 6, Wherein the gate driver comprises: A level shifter circuit for receiving a gate clock signal included in the control signal and level shifting the gate clock signal; And a shift register circuit receiving the gate clock signal output from the level shifter circuit and outputting a scan pulse to the gate wiring A method of driving a liquid crystal display device. 10. The method of claim 9, Wherein the shift register circuit is formed directly on the array substrate of the liquid crystal panel A method of driving a liquid crystal display device.

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