KR20110066490A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to appropriately modulate a gate signal to an optimum value by storing a set table which is set by different value each case. CONSTITUTION: In a liquid crystal display device, an LCD panel(100) defines a plurality of pixels. A gate driver(110) supplies a gate signal to a gate lines. A data driver supplies a data signal to the data lines. A timing controller(130) drives a gate driver and a data driver. A power supply unit(140) generates a driving voltage for the LCD panel. A memory device(160) comprises modulation data information which is obtained by modulating a gate signal into an optimum gate signal.

Description

Liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that can be easily adjusted by software in the process of setting values optimized for gate signal modulation.

In general, among the screen display devices for displaying image information on the screen, the thin-film flat panel display device is a target of intensive development in recent years because of the light weight and easy use in any place, in particular, the liquid crystal display device has a high resolution It is a product that is actively researched because it is high and the reaction speed is fast enough to realize a moving picture.

Such a liquid crystal display device (LCD) displays an image corresponding to a video signal on a liquid crystal display panel in which liquid crystal cells are arranged in a matrix by adjusting light transmittance of liquid crystal cells according to a video signal. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and a driving circuit for driving the liquid crystal display panel.

The driving circuit may include a gate driver for supplying a gate signal to a gate line of the liquid crystal display panel, a data driver for supplying a data signal to a data line of the liquid crystal display panel, a timing controller for controlling the gate and the data driver; And a power supply unit for providing a driving voltage to the gate and data driver.

The power supply unit may include various driving voltages for driving the liquid crystal display panel, for example, a gate signal (gate low voltage and gate high voltage), a gamma voltage (or gray voltage), and a common voltage based on a reference voltage. Vcom).

Meanwhile, the driving circuit is integrated into a single integrated chip (IC) and includes a plurality of circuit components (eg, an amplifier, a gate signal modulator, a logic element, etc.). Each signal (voltage and control signal) generated by the driving circuit is adjusted according to a specification of a model and a product to which a delay time and an enable are enabled.

In particular, in the case of gate pulse modulation (GPM), an engineer changes a resistor and a capacitor located at a gate signal modulation input terminal of the integrated chip (IC) from time to time and sets an optimized value for each product. In addition, even when a defect related to the gate signal modulation (GPM) occurs, the engineer changes the resistor and capacitor located at the gate signal modulation input terminal to solve the defect.

As such, the adjustment of the gate signal modulation (GPM) is inconvenient because it is set by the engineer to the optimized value by changing the resistance and capacitor.

An object of the present invention is to provide a liquid crystal display device capable of performing a gate signal modulation to a value that is appropriately optimized through I2C communication with the memory device by storing a table set to a different value in each case in a memory device. There is this.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a liquid crystal display panel in which gate lines and data lines intersect to define a plurality of pixels, a gate driver sequentially supplying gate signals to the gate lines, and the data lines. I2C communication with a data driver for supplying a data signal to the device, a timing controller for driving the gate driver and the data driver, a power supply for generating a driving voltage for driving the liquid crystal display panel, and the power supply. And a memory device including modulated data information modulated by the signal to an optimized gate signal satisfying a condition.

The liquid crystal display according to the present invention presets various adjustment values of gate pulse modulation (GMP) to a memory device and presets the gate signal modulation (GPM) value through I2C communication with the memory device. This allows for simple software adjustments.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other, and a liquid crystal cell Clc is disposed at an intersection thereof. A liquid crystal display panel 100 having a thin film transistor TFT for driving a light source, a gate driver 110 for supplying a scan signal to the gate lines GL1 to GLn, and a data line DL1 to DLm. A data driver 120 for supplying data, a timing controller 130 for controlling the gate driver 110 and the data driver 120, the gate driver 110, the data driver 120, and a liquid crystal display panel. The power supply unit 140 provides a voltage required for driving the 100 and the memory device 160 performing I2C communication with the gate signal modulator 150 of the power supply unit 140.

The liquid crystal display panel 100 has a liquid crystal formed between two glass substrates, and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other on the lower glass substrate. The thin film transistor TFT formed at the intersection of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm is in response to a gate signal from the gate lines GL1 to GLn. The data signal from DLm is supplied to the liquid crystal cell Clc.

To this end, the gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, the source electrode is connected to the data lines DL1 to DLm, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. do.

In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line, or may be formed between the liquid crystal cell Clc and a separate common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to each pixel area in which the thin film transistors TFT are formed, and the gate lines GL1 to GLn border each other. And a black matrix covering the data lines DL1 to DLm, the thin film transistor TFT, and the like, and a common electrode covering all of them.

The gate driver 110 supplies a plurality of gate signals to the plurality of gate lines GL1 to GLm in response to the gate control signal GCS from the timing controller 130. These multiple gate signals cause the multiple gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronization signal.

The data driver 120 generates a plurality of pixel data voltages whenever any one of the gate lines GL1 to GLn is enabled in response to the data control signals DCS from the timing controller 130. And a plurality of data lines DL1 to DLm on the liquid crystal display panel 100.

The timing controller 130 may enable data synchronization and synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown). The gate control signal GCS for controlling the gate driver 110 and the data control signal DCCS for controlling the data driver 120 are generated by using the (DE) signal and the clock signal CLK.

In addition, the timing controller 130 arranges the image data V-data input from an external system and supplies the sorted data Data to the data driver 120.

The power supply unit 140 is composed of one unified chip (IC) and includes a plurality of circuit elements to generate a driving voltage for driving the data driver 120 and the gate driver 110, and a common voltage ( Vcom) is generated and provided as a common electrode of the liquid crystal display panel 100.

In addition, the power supply unit 140 includes a gate signal modulator 150 that is responsible for modulating the gate signals provided to the gate lines GL1 to GLn of the liquid crystal display panel 100. The gate signal modulator 150 provides an optimized gate signal to the gate lines GL1 to GLn through I2C communication with the memory device 160.

The memory device 160 stores data information obtained by modulating the gate signal according to various conditions (environment, model, product information, etc.). The memory device 160 selects data information corresponding to a condition using I2C communication and provides it to the power supply unit 140. The memory device 160 and the gate signal modulator 150 of the power supply 140 operate based on I2C communication.

Specifically, the data information stored in advance in the memory device 160 is optimal information that can satisfy various conditions (environment, model, product information, etc.), and sets the operation of the gate signal modulation and charges the gate signal modulation. Adjusting the Charging Time, setting the low voltage level of the gate signal modulation, and the like.

The memory device 160 determines whether an input of a gate signal modulation enable signal provided from the gate signal modulator 150 of the power supply unit 140 is input. When the gate signal modulation enable signal is input, the memory device 160 provides prestored data information to the gate signal modulator 150 through I2C communication.

Here, the I2C (Inter-IC) refers to an interface for transmitting information through a signal line of a serial clock (SCL) and a serial data (SDA).

The data information stored in the memory device 160 includes low voltages divided to 0 to a reference voltage level according to a reference voltage (gate high voltage or power supply voltage). In addition, as illustrated in FIG. 2, the memory device 160 also includes values for a gate signal modulation (GPM) polling time point for gate signal modulation (GPM). At this time, the gate signal modulation (GPM) polling time points are different from each other according to the level of the low voltage voltage divided up from 0V to the reference voltage level.

In addition, the memory device 160 also includes information about a delay time of a gate signal modulation (GPM) according to the level of the low voltage divided by the voltage from 0V to the reference voltage level. In addition, the memory device 160 includes information on different gate signal modulation slew rates according to the level of the low voltage divided by the voltage from 0V to the reference voltage level.

The memory device 160 may be an EEPROM that is a nonvolatile memory device.

The gate signal modulator 150 of the power supply unit 140 applies a gate signal modulation enable signal to the memory device 160 when the gate signal modulation is required through I 2 C communication with the memory device 160. The data information stored in the device 160 is read.

Since the memory device 160 stores a gate signal optimized to satisfy various conditions (environment, model, product information, etc.), the gate signal modulator 160 is provided to the gate signal modulator 160 through I2C communication. can do. The gate signal modulator 160 may provide an optimized gate signal to the gate driver 110 of FIG. 1.

In the liquid crystal display according to the exemplary embodiment described above, the gate driver is selected by selecting an optimal gate signal using I2C communication between the gate signal modulator 150 and the memory device 160 embedded in the power supply 140. By driving 110, the circuit components for modulating the gate signal in the general liquid crystal display may be eliminated, thereby improving the cost.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention can eliminate the inconvenience of the operator having to change the resistor and capacitor to modulate the gate signal by software modulating the gate signal.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary and will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram simulated based on data information stored in the memory device of FIG. 1. FIG.

<Brief description of the main parts of the drawing>

100: liquid crystal display panel 110: gate driver

120: data driver 130: timing controller

140: power supply unit 150: gate signal modulator

160: memory device

Claims (5)

A liquid crystal display panel in which gate lines and data lines cross each other to define a plurality of pixels; A gate driver sequentially supplying gate signals to the gate lines; A data driver for supplying a data signal to the data lines; A timing controller driving the gate driver and the data driver; A power supply unit generating a driving voltage for driving the liquid crystal display panel; And And a memory device performing I2C communication with the power supply and including modulated data information modulated by the gate signal into an optimized gate signal satisfying a condition. The method according to claim 1, And the condition includes product environment, model and product information. The method according to claim 1, The data information stored in the memory device may include information on gate low voltages divided from 0V to a reference voltage level according to a reference voltage, information on timing of modulation polling of the gate signal according to the voltage divided gate low voltage, and the gate. A liquid crystal display comprising information on the modulation delay time of the signal. The method of claim 3, The gate signal modulation polling time point is different from each other according to the level of the voltage-divided low voltage. The method according to claim 1, And the memory device is an EEPROM, which is a nonvolatile memory.

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