KR20110065695A - Semiconductor package and stacked semiconductor package using the same - Google Patents

Abstract

PURPOSE: A semiconductor package and a stacked semiconductor package including the same are provided to secure high capacitance to the stacked semiconductor package by forming a thin semiconductor package. CONSTITUTION: A semiconductor chip includes one side, and another side or a lateral side facing one side. A bonding pad is formed at one side of the semiconductor chip. A wiring film(20) includes a film body(21) and a rewiring(22). The film body includes a first side and a second side facing the first side. The first side of the film body is attached to the semiconductor chip. The wiring rewires the bonding pad to another side of the semiconductor chip.

Description

Semiconductor package and laminated semiconductor package having the same {SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a laminated semiconductor package having the same, and more particularly, to a semiconductor package having a light and simple structure having a reduced thickness and a laminated semiconductor package having the same.

The packaging technology for semiconductor integrated devices is continuously developed in accordance with the demand for miniaturization and high capacity, and recently, various technologies for stacked semiconductor packages are developed to satisfy miniaturization, high capacity, and mounting efficiency. have.

In the semiconductor industry, "stacking" refers to a technology in which at least two semiconductor chips or packages are stacked vertically. In the case of a memory device, a product having a memory capacity larger than the memory capacity that can be realized in a semiconductor integration process may be implemented. It can increase the efficiency of use.

In the case of a laminated semiconductor package using a semiconductor chip, there is a disadvantage in that processability is lowered and yield is lowered as a thin processed semiconductor chip is handled. Therefore, in terms of processability and yield improvement, it is advantageous to manufacture a laminated semiconductor package using a semiconductor package formed by mounting a semiconductor chip on a substrate and molding the upper surface of the substrate.

Lamination using semiconductor packages In order to increase the capacity of semiconductor packages, semiconductor packages must be stacked in multiple layers. However, since the semiconductor package has a thicker thickness than the semiconductor chip, when the semiconductor package is stacked in multiple layers, the height becomes excessively high, and the module-to-module gap when the laminated semiconductor package is mounted on a mother board and modularized ) Is limited.

Thus, there is a need for the development of a new, thinner, thinner package with reduced thickness.

It is an object of the present invention to provide a thin and compact semiconductor package having a reduced thickness and a laminated semiconductor package having the same.

According to an aspect of the present invention, a semiconductor package includes a semiconductor chip having one surface, the other surface and a side surface facing the one surface, and a bonding pad formed on the surface thereof, and a first chip formed to surround the semiconductor chip and attached to the semiconductor chip. And a wiring film including a film body having a surface and a second surface opposite to the first surface, and a wiring line integrally formed with the film body and repositioning the bonding pad to the other surface of the semiconductor chip. It is done.

The redistribution may include a first connection pad formed to be electrically connected to the bonding pad, a second connection pad formed to contact the other surface of the semiconductor chip, and the first connection pad and the second connection pad to be electrically connected to each other. It characterized in that it comprises a circuit wiring to connect.

The first connection pad and the second connection pad may be formed to penetrate the first surface at the second surface of the film body.

The first connection pad and the second connection pad may be formed to protrude from the second surface of the film body.

The circuit wiring is formed on the second surface of the film body.

The circuit wiring is characterized in that formed inside the film body.

A connecting member is formed between the bonding pad and the first connection pad.

The connecting member may be formed of any one of a bump, an anisotropic conductive film, and a solder ball.

According to another aspect of the present invention, a multilayer semiconductor package includes a semiconductor chip having one surface, the other surface and a side surface facing the one surface, and a bonding pad formed on the one surface, and formed to surround the semiconductor chip and attached to the semiconductor chip. A plurality of wiring films including a film body having one surface and a second surface facing the first surface, and a wiring film integrally formed with the film body and including a redistribution line for repositioning the bonding pad to the other surface of the semiconductor chip. And semiconductor packages, wherein the semiconductor packages are stacked such that adjacent semiconductor packages are electrically connected through the redistribution.

The redistribution may pass through the first surface and the second surface of the film body so that one end thereof is electrically connected to the bonding pad and the other end opposite to the one end portion is formed on the second surface of the film body. A first connection pad formed to protrude, and one end of the film body penetrating the first and second surfaces of the film body to be in contact with the other surface of the semiconductor chip, and the other end of the film body facing the one end of the film body; And a second connection pad formed to protrude from the second surface, and circuit wiring for electrically connecting the first connection pad and the second connection pad.

The semiconductor packages may be electrically connected to a first connection pad protruding from the second surface of the film body of the lower semiconductor package and a second connection pad protruding from the second surface of the film body of the upper semiconductor package. It is characterized by being stacked.

A conductive connection member is formed between the first connection pad of the lower semiconductor package and the second connection pad of the upper semiconductor package.

The conductive connecting member is formed of any one of bump, anisotropic conductive film, solder ball.

A gap fill member may be formed between the adjacent semiconductor packages.

The gap fill member is formed of any one of an anisotropic conductive paste and a nonconductive paste.

According to the present invention, as described in detail above, since the semiconductor package is formed to a thin thickness of the semiconductor chip level, it is possible to overcome the limitation of the high capacity of the laminated semiconductor package formed by stacking the semiconductor packages and to manufacture a high capacity multilayer semiconductor package. It is possible.

In addition, since a high-capacity laminated semiconductor package can be configured by using a semiconductor package that is advantageous in terms of processability and yield compared to a semiconductor chip, the processability and yield of the laminated semiconductor package are improved.

Furthermore, since no molding process is performed without using a substrate, cost is reduced and mass productivity is improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a semiconductor package according to an embodiment of the present invention, Figure 2 is a view showing a semiconductor chip used in the semiconductor package according to an embodiment of the present invention, Figure 3 is an embodiment of the present invention 4 is a cross-sectional view taken along line II ′ of FIG. 3, and FIG. 5 is a diagram for describing a process of fabricating a semiconductor package using a semiconductor chip and a wiring film.

1 to 5, a semiconductor package 100 according to an embodiment of the present invention includes a semiconductor chip 10 and a wiring film 20.

In the present embodiment, the semiconductor chip 10 may have a rectangular parallelepiped shape.

The semiconductor chip 10 having a rectangular parallelepiped shape has one surface A, the other surface B facing the one surface A, and the side surface C. As shown in FIG. The semiconductor chip 10 having a rectangular parallelepiped shape has four side surfaces C. FIG.

Bonding pads 11 are formed on one surface A of the semiconductor chip 10.

Although not shown, the semiconductor chip 10 includes a circuit portion. The circuit portion includes, for example, a data storage portion for storing data and a data processing portion for processing the data. The bonding pad 11 corresponds to an electrical contact of a circuit part for connection with the outside.

The wiring film 20 includes a film body 21 and a rewiring 22.

The film body 21 is attached to an outer surface of the semiconductor chip 10, that is, one surface A, the other surface B, and four side surfaces C of the semiconductor chip 10 so as to surround the semiconductor chip 10.

The film body 21 has the 1st surface E attached to the semiconductor chip 10, and the 2nd surface F facing the 1st surface E. As shown in FIG.

In this embodiment, the redistribution 22 includes a first connection pad 22A, a second connection pad 22B and a circuit wiring 22C.

The first connection pad 22A penetrates the first surface E from the second surface F of the film body 21 attached to one surface A of the semiconductor chip 10 to bond the semiconductor chip 10. It is formed to be electrically connected to the pad (11).

A conductive connection member (not shown) may be formed between the first connection pad 22A and the bonding pad 11 to electrically connect the first connection pad 22A and the bonding pad 11.

The conductive connection member may be formed of any one of a bump, an anisotropy conductive film, and a solder ball.

The second connection pad 22B penetrates the first surface E from the second surface F of the film body 21 attached to the other surface B of the semiconductor chip 10, and the other surface of the semiconductor chip 10. It is formed to contact with (B).

The first and second connection pads 22A and 22B may protrude from the second surface F of the film body 21 by a predetermined height.

The circuit wiring 22C electrically connects the first connection pad 22A and the second connection pad 22B.

The circuit wiring 22C may be formed on the second surface F of the film body 21. Alternatively, the circuit wiring 22C may be formed inside the film body 21.

6 and 7 illustrate a multilayer semiconductor package having a semiconductor package according to an embodiment of the present invention.

6 and 7, the stacked semiconductor package having the semiconductor package 100 described above has a stacked structure such that adjacent semiconductor packages 100 are electrically connected through the redistribution line 22.

For example, the first connection pads 22A of the semiconductor package positioned below the adjacent semiconductor packages 100 and the second connection pads 22B of the upper semiconductor package are stacked to be electrically connected to each other.

Although not shown, a conductive connection member may be further formed between the first connection pad 22A of the semiconductor package located below and the second connection pad 22B of the semiconductor package located above.

The conductive connection member may be formed of any one of bump, anisotropic conductive film, and solder ball.

In addition, a gap fill member 30 is formed between the semiconductor packages 100, and an external connection terminal (not shown) such as a borland is attached to the semiconductor package positioned at the lowermost portion.

The gapfill member 30 may be formed of any one of an anisotropic conductive paste (ACP) and a non-conductive paste (NCP).

As described in detail above, since the semiconductor package is formed to have a thin thickness of the semiconductor chip level, it is possible to overcome the limitation of increasing the capacity of the laminated semiconductor package formed by stacking the semiconductor packages and to manufacture a high capacity laminated semiconductor package. In addition, since a high-capacity laminated semiconductor package can be configured by using a semiconductor package that is advantageous in terms of processability and yield compared to a semiconductor chip, the processability and yield of the laminated semiconductor package are improved. Furthermore, since no molding process is performed without using a substrate, cost is reduced and mass productivity is improved.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 illustrates a semiconductor package according to an embodiment of the present invention.

2 illustrates a semiconductor chip used in a semiconductor package according to an embodiment of the present invention.

3 is a view showing a wiring film used in a semiconductor package according to an embodiment of the present invention.

4 is a cross-sectional view taken along the line II ′ of FIG. 3.

5 is a view showing a semiconductor package manufacturing process using a semiconductor chip and a wiring film.

6 and 7 illustrate a multilayer semiconductor package using a semiconductor package according to an embodiment of the present invention.

<Description of main parts of drawing>

100: semiconductor package

10: semiconductor chip

20: wiring film

21: film body

22: redistribution

22A, 22B: 1st, 2nd connection wiring

22C: circuit wiring

Claims (15)

A semiconductor chip having one surface, the other surface and a side surface facing the one surface, and a bonding pad formed on the one surface; and A film body formed to surround the semiconductor chip and having a first surface attached to the semiconductor chip and a second surface facing the first surface and the film body and integrally formed with the film body, wherein the bonding pad is formed on the semiconductor chip. A wiring film including redistribution for rearrangement to the other side; A semiconductor package comprising a. The method of claim 1, The redistribution is, A first connection pad configured to be electrically connected to the bonding pad; A second connection pad formed to contact the other surface of the semiconductor chip; and Circuit wiring for electrically connecting the first connection pad and the second connection pad; A semiconductor package comprising a. 3. The method of claim 2, And the first connection pad and the second connection pad are formed to penetrate the first surface at the second surface of the film body. The method of claim 3, And the first and second connection pads protrude from the second surface of the film body. 3. The method of claim 2, The circuit wiring is formed on the second surface of the film body. 3. The method of claim 2, The circuit wiring is formed in the film body, characterized in that the semiconductor package. 3. The method of claim 2, And a conductive connection member is formed between the bonding pad and the first connection pad. The method of claim 7, wherein The conductive connection member is a semiconductor package, characterized in that formed of any one of bump, anisotropic conductive film, solder ball. One side, the semiconductor chip having the other surface and the side opposite to the one surface and the bonding pad is formed on the one surface, the first surface formed to surround the semiconductor chip and attached to the semiconductor chip and the second surface facing the first surface A plurality of semiconductor packages including a film body having a face and a wiring film formed integrally with the film body, the wiring film including a redistribution for repositioning the bonding pad to the other surface of the semiconductor chip, And the semiconductor packages are stacked such that adjacent semiconductor packages are electrically connected through the redistribution. The method of claim 9, The redistribution is, A first end penetrating the first and second surfaces of the film body such that one end thereof is electrically connected to the bonding pad and the other end opposite to the one end protrudes from the second surface of the film body; Connection pads; A first end formed through the first surface and the second surface of the film body, the one end of which is in contact with the other surface of the semiconductor chip, and the other end facing the one end of the film body protrudes from the second surface of the film body; 2 connection pads; and A circuit wiring for electrically connecting the first connection pad and the second connection pad; Laminated semiconductor package comprising a. The method of claim 10, The semiconductor packages may include a first connection pad protruding from a second surface of a film body of a lower semiconductor package positioned below one of the adjacent semiconductor packages, and a second protrusion protruding from a second surface of a film body of an upper semiconductor package positioned above. 2. A laminated semiconductor package, wherein the connection pads are stacked to be electrically connected to each other. The method of claim 11, And a conductive connection member is formed between the first connection pad of the lower semiconductor package and the second connection pad of the upper semiconductor package. The method of claim 12, The conductive connecting member is a semiconductor package, characterized in that formed of any one of bump, anisotropic conductive film, solder ball. The method of claim 10, And a gapfill member is formed between the adjacent semiconductor packages. 15. The method of claim 14, The gapfill member is formed of any one of an anisotropic conductive paste and a nonconductive paste.

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