KR20110063242A - Liquid crytal display device and driving method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a driving method thereof are provided to reduce power consumption by varying a driving mode according to the property of an image which is divided by a frame or line. CONSTITUTION: In a liquid crystal display device and a driving method thereof, a liquid crystal panel(112) comprises a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells A source driving unit(114) supplies data and gate control signals and power signal to the data lines and gate lines. A storage unit(130) receives a power reference and a share reference of a power control circuit and a chare share circuit respectively. A drive mode selection circuit(120) receives a digital video data. The drive mode selection circuit compares the number of gray fault pixel of a digital video data corresponding to first and second gray period with a reference respectively.

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display and a driving method thereof which can reduce power consumption by driving a source driver in a normal mode or a low power mode according to an attribute of an image divided into frames or lines.

With the development of information technology (IT), the importance of the flat panel display device as a visual information transmission medium is further emphasized, and low power consumption, thinness, light weight, and high quality are required to secure an improved competitiveness. A typical flat panel display device is a liquid crystal display (LCD) that displays an image by using optical anisotropy of liquid crystals. The liquid crystal display device has advantages such as thin, small size, low power consumption and high quality.

The liquid crystal display may display a desired image by individually supplying image information to a plurality of pixels arranged in a matrix, and adjusting light transmittance of the liquid crystal layer corresponding to each of the plurality of pixels. Accordingly, the liquid crystal display includes a liquid crystal panel in which a plurality of pixels, which are the smallest unit for implementing an image, is arranged in a matrix form, and a driving unit for driving the liquid crystal panel. In addition, since the LCD does not emit light by itself, a backlight unit for supplying light to the LCD is provided. The driver includes a source controller as well as a timing controller.

Hereinafter, a liquid crystal display of the prior art will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a liquid crystal display according to the prior art, and FIG. 2 is a relation diagram of a timing controller and a source driver according to the prior art.

As shown in FIG. 1, the LCD 10 according to the related art includes a liquid crystal panel 12, a source driver 14, and a timing controller 18. The liquid crystal panel 12 includes a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, a plurality of thin film transistors, a plurality of data lines D1 to Dm, and a gate line G1 to Gn. A plurality of m × n liquid crystal cells Clc are arranged in a matrix formed by a crossover structure, and the source driver 14 is provided on each of the data lines D1 to Dm and the gate lines G1 to Gn. A data control signal, a power signal, a gate control signal, and a power signal are applied.The source driver 14 includes a power control circuit (PWRC) and a charge share circuit (CSC).

Although not shown in detail in the drawing, the liquid crystal panel 12 includes upper and lower substrates, and a black matrix, a color filter, and a common electrode are formed on the upper substrate. The common electrode is formed on the upper substrate in the case of a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is horizontal such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. In the case of the electric field driving method, it is formed on the lower substrate together with the pixel electrode.

As shown in FIG. 2, the timing controller 18 that receives data enable and vertical / horizontal synchronization signals Vsync and Hsync from a system (not shown) may include a gate start pulse (GSP). , Common voltage (VST). A first signal generator 18a for generating a gate clock signal GCLK and a gate output enable signal (GOE), a source output enable signal (SOE), and a polarity control signal (Polarity) The second signal generator 18b for generating a POL and the third signal generator 18c for rearranging the input digital video data RGB to the liquid crystal panel 112 and supplying the source driver 14 to the source driver 14. It includes.

The driving method of the source driver 14 is generally divided into a normal mode and a low voltage driving mode. In general, the source driver 14 is set to the normal mode as shown in FIG. 2 at the beginning of manufacturing to prevent image defects from occurring. In other words, the power control circuit PWRC and the charge share circuit of the source driver 14 are set to be applied with high, and the polarity control signal POL is two dot inversion. ) Mode is set to drive.

The power control circuit PWRC includes first and second power control circuits PWRC1 and PWRC2, and the source driver 14 according to a combination of voltages applied to the first and second power control circuits PWRC1 and PWRC2. Determine the power consumption applied by. If necessary, "HH", "HL", "LH", and "LL" may be applied to each of the first and second power control circuits PWRC1 and PWRC2. "HH", "HL", and "LH" are defined as High, and "LL" is defined as Low. Typically, "HL" or "LH" is set to be applied to the first and second power control circuits PWRC1 and PWRC2.

Set each of the power control circuit PWRC and the charge shade circuit CSC of the source driver 14 to Low, and set the polarity control signal POL to column inversion instead of two dot inversion. inversion), the power consumption of the source driver 14 can be reduced to the maximum. However, in a specific pattern, the vertical dim and the vertical line are even / odd. And a vertical band defect in which a band having a thickness of about 2 pixels is perceived differently depending on left and right reciprocation of the liquid crystal panel may occur.

Since the normal driving mode of the source driving unit 14 is used at the beginning of manufacturing in the liquid crystal display device according to the related art as described above, it is difficult to flexibly respond to the change of the image. In other words, unnecessary power can be consumed by applying the normal driving mode to an image that can be sufficiently operated in the low power consumption driving mode.

In order to solve the above problems, the present invention provides a liquid crystal display and a driving method thereof, which can reduce power consumption by converting the source driving unit to low power all or normal mode according to the property of the image divided by frame or line. The purpose is to provide.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells; A source driver which supplies data and gate control signals and power signals to each of the plurality of data lines and the plurality of gate lines, and includes a power control circuit and a charge share circuit; When the source driver operates the power control circuit and the charge share circuit in a low power mode, the power that is allowed in each of the first and second gray periods in which a failure occurs and the first and second gray periods, respectively. A storage unit to which a power reference value and a share reference value, which are the number of gray defective pixels, for each of the control circuit and the charge share circuit are input; The digital video data is input, and the number of gray defective pixels of the digital video data corresponding to the first and second gray periods is compared with the power reference value and the share reference value, respectively, so that each of the power control circuit and the charge share circuit is determined. And a driving mode selection circuit for setting to "H" or "L".

In the liquid crystal display as described above, the storage unit may include a third gray period in which a defect occurs when the source driver operates in a column inversion, and the number of gray defective pixels that may be allowed in the third gray period. An inversion reference value is input, and the driving mode selection circuit compares the number of gray defective pixels of the digital video data generated in the third gray period with the inversion reference value, and inverts the polarity control signal to the source driving unit as a polarity control signal. Or applying a 2 dot inversion signal.

In the above liquid crystal display device, the drive mode selection circuit includes a first selection circuit for selecting the power control circuit as "H" or "L", and the charge share circuit as "H" or "L". And a second selection circuit for selecting, and a third selection circuit for selecting the polarity control signal as column inversion or two dot inversion.

In the liquid crystal display device as described above, the first selection circuit is configured to analyze the digital video data input in real time, wherein the first and second reference values between the first and second reference values, which are lower and upper limits of the first gray section, in which a defect occurs. A calculator for calculating the number of gray defective pixels; The third reference value, which is the allowable amount of the gray defective pixels of the digital video data and the gray defective pixels, is compared, and "H" or "L" is applied to the power control circuit according to the gray defective pixels of the digital video data. Mode determination unit for determining the application of; characterized in that it comprises a.

In the liquid crystal display device as described above, the second selection circuit is configured to analyze the digital video data input in real time, wherein the second value between the first and second reference values, which is a lower limit and an upper limit, of the second gray section in which a defect occurs. A calculator for calculating the number of gray defective pixels; A third reference value, which is an allowable amount of the gray defective pixels of the digital video data and the number of gray defective pixels, is compared, and according to the gray defective pixels of the digital video data, an "H" or "L" value is assigned to the charge share circuit. It is characterized in that it includes a mode determination unit for determining the application of ".

In the liquid crystal display device as described above, the third selection circuit is configured to analyze the digital video data input in real time, wherein the third value between the first and second reference values, which is a lower limit and an upper limit, of the third gray section in which a defect occurs. A calculator for calculating the number of gray defective pixels; A third reference value, which is an allowable amount of the gray defective pixels and the gray defective pixels of the digital video data, is compared and the polarity control signal is column inversion or two dot inversion according to the gray defective pixels in the digital video data. It characterized in that it comprises a; mode determination unit to set to.

In the above liquid crystal display device, the storage unit is characterized in that using the EEPROM.

In the liquid crystal display device as described above, the digital video data input to the driving mode selection circuit is characterized in that the frame unit or line unit.

A driving method of a liquid crystal display device according to the present invention for achieving the above object, a liquid crystal panel comprising a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells and the plurality of data lines and the plurality of A method of driving a liquid crystal display device, comprising: a source driver for supplying data and gate control signals and a power signal to gate wirings, and including a power control circuit and a charge share circuit, each of the power control circuit and the charge share circuit; A first reference value and a second reference value corresponding to the number of defective gray pixels in the first and second gray periods are set in the storage unit by applying “L” to the storage unit. Inputting; In the digital video data inputted to the driving mode selection circuit, the number of defective gray pixels corresponding to the gray section is compared with the first and second reference values, so that the power control circuit and the charge share circuit are each “L” or “H”. Set to; characterized in that it comprises a.

In the driving method of the liquid crystal display device as described above, the third gray period in which a failure occurs is set by applying a column inversion signal as a polarity control signal, and the allowable amount of defect for the number of defective gray pixels in the third gray period. Inputting a third reference value into a storage unit, and comparing the number of defective gray pixels corresponding to the gray interval in the digital video data input to the driving mode selection circuit with the third reference value, to obtain the polarity control signal. And selecting the column inversion or the two dot inversion.

In the driving method of the liquid crystal display device as described above, the digital video data input to the driving mode selection circuit is characterized in that the frame unit or line unit.

The liquid crystal display and the driving method thereof according to the present invention can reduce power consumption by automatically varying the driving mode of the source driving unit according to the attribute of the image divided by frame or line. In other words, in the case of an image having a medium brightness, the source is set in the normal mode in which the power control circuit PWRC and the charge share circuit CSC are set high and the polarity control signal POL is set to 2 dot inversion. In the low voltage driving mode in which the driving unit is driven but the brightness or the dark image is set, the power control circuit PWRC and the charge share circuit CSC are set low, and the polarity control signal POL is set to column inversion. The power consumption may be reduced by driving the source driver. Therefore, in the case of the liquid crystal display device used in the notebook, it is possible to increase the use time of the battery by reducing the power consumption.

1 is a schematic view of a liquid crystal display according to the prior art
2 is a diagram illustrating a relationship between a timing controller and a source driver according to the related art.
3 is a schematic view of a liquid crystal display according to the present invention;
4 is a relationship diagram of a timing controller and a source driver according to the present invention;
5 is a detailed view of a drive mode selection circuit according to the present invention.
6 and 7 are histograms of one frame of digital video data according to the present invention.
8 is a flowchart illustrating a method of driving a liquid crystal display according to the present invention.
9A and 9B are schematic diagrams of images analyzed on a frame basis according to a first embodiment of the present invention.
10 is a schematic diagram of an image according to a second embodiment of the present invention;
11A and 11B are histograms of digital video data obtained by analyzing the image of FIG. 10 line by line.
12 is a flowchart illustrating a method of driving a liquid crystal display according to a second embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Example

3 is a schematic diagram of a liquid crystal display according to a first embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display 110 according to the first exemplary embodiment of the present invention includes a liquid crystal panel 112, a source driver 114, and a timing controller 118. The timing controller 118 includes a driving mode selection circuit 120 and a storage unit 130.

The liquid crystal panel 112 includes a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, a plurality of thin film transistors, a plurality of data lines D1 to Dm, and a gate line G1 to Gn. A plurality of m × n liquid crystal cells Clc are arranged in a matrix form formed by an intersecting structure, and the source driver 114 is provided on each of the data lines D1 to Dm and the gate lines G1 to Gn. A data control signal, a power signal, a gate control signal, and a power signal are applied.

Although not shown in detail in the drawing, the liquid crystal panel 112 includes upper and lower substrates, and a black matrix, a color filter, and a common electrode are formed on the upper substrate. The common electrode is formed on the upper substrate in the case of a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is horizontal such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. In the case of the electric field driving method, it is formed on the lower substrate together with the pixel electrode.

4 is a relationship diagram of a timing controller and a source driver according to the first embodiment of the present invention.

Referring to FIG. 4, the source driver 114 includes a power control circuit (PWRC) and a charge share circuit (CSC). The power control circuit PWRC includes first and second power control circuits PWRC1 and PWRC2. The source driver 114 determines a combination of voltages applied to the first and second power control circuits PWRC1 and PWRC2. "HH", "HL", "LH", and "LL" may be applied to each of the first and second power control circuits PWRC1 and PWRC2. When "HH", "HL", and "LH" are applied to the first and second power control circuits PWRC1 and PWRC2, the definition is high, and when "LL" is applied, the definition is low. .

As shown in FIG. 4, the timing controller 118 that receives data enable and vertical / horizontal synchronization signals Vsync and Hsync from a system (not shown) includes a gate start pulse (GSP). , Common voltage (VST). The first signal generator 118a for generating the gate clock signal GCLK, the gate output enable signal GOE, the source output enable signal SOE, and the polarity control signal Polarity. A second signal generator 118b for generating a POL, and a third signal generator 118c for rearranging the input digital video data to match the liquid crystal panel 112 and supplying it to the source driver 114. .

The source driver 114 applies "LL" to the power control circuit PWRC, applies "L" to a charge share circuit, and applies a column inversion signal to the polarity control signal POL. In the low voltage mode, "HL" or "LH" is applied to the power control circuit PWRC, "H" is applied to the charge share circuit, and the 2-dot inversion (POL) is applied to the polarity control signal POL. Normal mode using dot inversion can be selected and driven.

The driving mode selection circuit 120 analyzes the input digital video data for each frame to classify image attributes, and selects the power control circuit PWRC as high or low based on the analysis result. A first selection signal, a second selection circuit for selecting the charge share circuit CSC high or low, and a polarity control signal POL for selecting column inversion or two dot inversion A driving mode selection signal including a third selection circuit is generated.

The reference value of the image information stored in the storage unit 130 can be obtained from the measured data when the source driver 114 is set to the low voltage mode. In other words, the low voltage modes "LL" and "L" are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114 and set to the column inversion. After driving, the displayed image is analyzed to determine a defective generation range of the gary scale and an acceptable amount of defective pixels. The storage unit 130 may use an EEPROM.

The driving mode selection circuit 120 analyzes the input digital video data for each frame to classify image attributes, and sets a reference value input to the storage unit 130 to determine the number of defective pixels in the gray scale defect generation range based on the analysis result. In comparison, when the number of defective pixels of the image information is higher than the reference value, the source driver 114 is driven in the normal mode, and when the number of defective pixels of the image information is lower than the reference value, the source driver 114 is driven in the low voltage mode.

The low voltage mode “LL” and “L” are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, and the inversion mode is used as a column. By setting to inversion, the allowable amount of the defective generation range and the number of defective pixels of the gary scale can be determined. For example, when the low voltage mode " LL " is applied to each of the first and second power control circuits PWRC1 and PWRC2, the defective generation range of the gray scale and the allowable amount of the defective pixels are each 15 to 40 gray, and You can decide with 1000 pixels. At this time, in the defective generation range of gray scales 15 to 40, the lower limit and the upper limit 15 and 40 gray, respectively, are set as the first and second power reference values PR1 and PR2, and 1000, which is the allowable amount of defective pixels, is set. 3 Set the power reference value (PR3).

When the low voltage mode " L " is applied to the charge share circuit CSC, the allowable amount of the defective color generation range and the number of defective pixels on the gray scale can be determined to be 15 to 35 gray and 1200 pixels, respectively. At this time, in the range of 15 to 35 which is the defective generation range of gray scale, the lower limit and the upper limit of 15 and 35 gray are respectively set as the first and second share reference values SR1 and SR2, and 1200, which is the allowable amount of defective pixels, is set. 3 Set to share reference value SR3.

In the case of setting to column inversion, the allowable amount of the defective generation range of the gray scale and the number of defective pixels can be determined to be 15 to 35 gray and 900 pixels, respectively. At this time, in the defective generation range of gray scales 15 to 35, the lower limit and the upper limit 15 and 35 gray, respectively, are set as the first and second inversion reference values IR1 and IR2, and 900, which is an allowable amount of defective pixels, is set. The third inversion reference value IR3 is set.

The low voltage mode “LL” and “L” are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, and the inversion mode is used as a column. The first to third power reference values PR1, PR2, and PR3, the first to third share reference values SR1, SR2, and SR3, and the first to third inversion reference values IR1 which are set to the inversion, are experimental results. , IR2, IR3) are input to the storage 130. The first to third power reference values PR1, PR2 and PR3, the first to third share reference values SR1, SR2 and SR3, and the first to third inversion reference values IR1, IR2, and IR3, which are experimental results. ) Are only examples, and other values may be used as necessary.

The driving mode selection circuit 120 includes a first selection circuit 120a and a charge share circuit CSC for selecting the first and second power control circuits PWRC1 and PWRC2 as "HL / LH" or "LL". Includes a second selection circuit 120b for selecting " H " or " L " and a third selection circuit 120c for selecting the polarity control signal POL as column inversion or two dot inversion. It is composed.

5 is a detailed view of a drive mode selection circuit according to the first embodiment of the present invention.

Referring to FIG. 5, the first selection circuit 120a analyzes digital video data input in real time on a frame-by-frame basis for failures between the first and second power reference values PR1 and PR2 which are the lower and upper limits of the gray defect generation range. A calculator 122 that calculates the number of gray pixels and a mode for comparing the number of defective gray pixels of the digital video data with the third power reference value PR3 which is the allowable gray allowance and determining the normal mode or the low voltage mode according to the comparison result. The decision unit 124 is configured.

The calculating unit 122 compares the gray level of each pixel of the digital video data of one frame with the first power reference value PR1, and calculates the gray level of each pixel of the digital video data of one frame. Outputs the pixels corresponding to the occurrence of gray defects in the digital video data RGB by receiving the outputs of the second comparator 122b and the first and second comparators 122a and 122b for comparing the two power reference values PR2. An AND gate 122d and a counter 122c for counting the number of defective gray pixels between the first and second power reference values PR1 and PR2 are included. The mode determiner 124 determines the normal mode or the low voltage mode according to a comparison result between the third comparator 124a and the third comparator 124a for comparing the number of defective gray pixels with the third power reference value PR3. It comprises a mux 124b.

The second selection circuit 120b for selecting the charge share circuit CSC as " H " or " L " is compared with the third share reference value CSC, which is the number of defective gray pixels and the allowable gray allowance amount of the digital video data. Except that the comparison result is applied to the charge share circuit CSC, it has the same configuration as the first selection circuit 120a.

The third selection circuit 120c for selecting the polarity control signal POL as column inversion or two dot inversion is compared with the number of defective gray pixels of the digital video data and the third inversion reference value IR3 which is the allowable gray allowance. According to the comparison result, it is set to the column inversion or the two dot inversion, and has the same configuration as the first selection circuit 120a except for applying it to the source driver 114.

6 and 7 are histograms of digital video data of one frame according to the first embodiment of the present invention.

For example, the digital video data of one frame may correspond to the histograms of FIGS. 6 and 7. 6 is a pixel value of a gray scale having a value of 0 to 63, for example, and the vertical axis represents the number of pixels of the corresponding gray scale. When the low voltage mode is applied to the power control circuit PWRC, when digital video data having a histogram distribution as shown in FIG. 6 is input to the driving mode selection circuit 120, the first and second power reference values PR1 and PR2 may be used. Since the number of gray defective pixels is equal to or larger than the third power reference value PR3 which defines the defective tolerance amount of 1000, the power control circuit PWRC is driven in the normal mode. At this time, each of the first and second power control circuits PWRC1 and PWRC2 is applied as "HL" or "LH".

When digital video data having a histogram as shown in FIG. 7 is input to the driving mode selection circuit 120, the third power reference value in which the number of gray defective pixels between the first and second power reference values PR1 and PR2 is defined as 1000 allowable defects is determined. Since it is equal to or less than PR3, the power control circuit PWRC is driven in the low voltage mode. At this time, each of the first and second power control circuits PWRC1 and PWRC2 is applied as "LL".

According to the driving mode selection circuit 120 of the present invention, in the case of a bright or dark image, the power control circuit PWRC and the charge share circuit CSC are set low, and the polarity control signal POL is converted into a column. The source driver 114 can be driven in a low voltage driving mode set to inversion, and in the case of an image having a medium brightness, the power control circuit PWRC and the charge share circuit CSC are set to high, and the polarity is maintained. The source driver 114 may be driven in the normal mode in which the control signal POL is set to 2 dot inversion.

8 is a flowchart illustrating a method of driving a liquid crystal display according to a first embodiment of the present invention. The driving method of the liquid crystal display device 110 according to the first embodiment of the present invention will be described with reference to FIGS. 3 to 8 as follows.

As in the first step S01, the low voltage modes “LL” and “L” are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114. , The inversion mode is set to column inversion, and the allowable amount of the defective generation range of the gary scale and the number of defective pixels is extracted and stored in the storage unit 130.

As in the second step SO2, through the histogram analysis of the digital video data input to the driving mode selection circuit, the power control circuit is compared with the reference range stored in the storage unit 130 by comparing the defective generation range and the number of defective pixels in the gray scale. Is set to "HL / LH" or "LL", the charge share circuit is "H" or "L", and the polarity control signal (POL) is set to column inversion or two dot inversion, and the source driver is operated in the low voltage mode or the normal mode. Drive 114.

In the liquid crystal display according to the first exemplary embodiment of the present invention, power consumption may be reduced by automatically changing the driving mode of the source driver 114 according to the attributes of the images divided in units of frames. However, in general, a frame-based image may be a mixture of a bright or dark image and an image having a medium brightness. In other words, a combination pattern of black and white and a gray pattern may be mixed in one frame.

9A and 9B are schematic diagrams of images analyzed in units of frames according to the first embodiment of the present invention.

The image in a frame unit includes a case where the combination pattern 152 of black and white is divided as shown in FIG. 9A and a case where the combination pattern 152 and the gray pattern 154 of black and white are divided as shown in FIG. 9B. can do.

As shown in FIG. 9A, when the combination pattern 152 of black and white is used, since the number of defective pixels of the pixel information is generally lower than or equal to the reference value, the first and second power control circuits of the source driver 114 shown in FIG. The low voltage modes "LL 'and" L "are applied to each of the PWRC1 and PWRC2 and the charge share circuit CSC, and the power consumption can be reduced by setting the column inversion mode.

As shown in FIG. 9B, when the black and white combination pattern 152 and the gray pattern 154 are divided into each other, even if the number of defective pixels in the pixel information as a whole is greater than or equal to the reference value, or the number of defective pixels in the pixel information as a whole is less than the reference value, The defect may be out of range. Even in this case, the portion of the black and white combination pattern 152 may have a defective pixel number of pixel information or less. However, in the case of FIG. 9B, since the attributes of the image are analyzed in units of frames, the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit of the source driver 114 shown in FIG. The low voltage modes "HL / LH 'and" H "shall be applied to each of the (CSC).

2nd Example

Unlike the first embodiment of the present invention, in which digital video data is divided in units of frames to analyze an attribute of an image, in the second embodiment of the present invention, the source driving unit is configured according to the attributes of an image in which digital video data is divided in units of lines. A liquid crystal display device capable of reducing power consumption by automatically changing a driving mode is proposed. For convenience of description, the drawings of the first embodiment that overlap with the second embodiment of the present invention are referred to, and the same reference numerals are used for the same components.

The liquid crystal display device of the second embodiment of the present invention has the same configuration as that of Figs. 3 to 5 of the first embodiment, except that the driving mode selection circuit 120 of Fig. 4 is digital. In the second embodiment of the present invention, the driving mode selection circuit 120 of FIG. 4 analyzes the digital video data in units of horizontal lines to classify the attributes of the image. There is a difference in that.

Referring to FIG. 4, the driving mode selection circuit 120 analyzes input digital video data in line units to classify image attributes, and sets the power control circuit PWRC high or low based on the analysis result. A first selection signal for selecting to (Low), a second selection circuit for selecting the charge share circuit (CSC) to High or Low, and a column inversion or two for the polarity control signal (POL). A drive mode selection signal is generated that includes a third selection circuit for selecting with dot inversion.

The reference value of the image information stored in the storage unit 130 can be obtained from the measured data when the source driver 114 is set to the low voltage mode. In other words, the low voltage modes "LL" and "L" are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114 and set to the column inversion. After driving, the image on a line-by-line basis is analyzed to determine a defective generation range of the gray scale and a defective pixel allowance.

The driving mode selection circuit 120 analyzes the input digital video data on a line-by-line basis to classify image properties, and sets a reference value input to the storage unit 130 to determine the number of defective pixels in a gray scale defect generation range based on the analysis result. In comparison, when the number of defective pixels of the image information is greater than or equal to the reference value, the source driver 114 is driven in the normal mode, and when the number of defective pixels of the image information is less than the reference value, the source driver 114 is driven to the low voltage mode.

The low voltage mode “LL” and “L” are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, and the inversion mode is used as a column. By setting to inversion, the allowable amount of the defective generation range and the number of defective pixels of the gary scale can be determined.

For example, when " LL " which is a low voltage mode is applied to each of the first and second power control circuits PWRC1 and PWRC2, the defective generation range of gray scale and the allowable amount of defective pixels in the line-by-line image are respectively determined. 15 to 40 gray, and 20 pixels. At this time, in the defective generation range of gray scale 15 to 40, the lower limit and the upper limit 15 and 40 gray, respectively, are set as the first and second power reference values PR1 and PR2, and 20, which is the allowable amount of defective pixels, is set. 3 Set the power reference value (PR3).

When the low voltage mode " L " is applied to the charge share circuit CSC, the allowable amount of the defective color generation range and the number of defective pixels on the gray scale can be determined to be 15 to 35 gray and 20 pixels, respectively. At this time, in the defective generation range of gray scales 15 to 35, the lower limit and the upper limit of 15 and 35 grays are respectively set as the first and second share reference values SR1 and SR2, and 20, which is an allowable amount of defective pixels, is set. 3 Set to share reference value SR3.

When the column inversion is set, the allowable amount of the defective generation range of the gray scale and the number of defective pixels can be determined to be 15 to 35 gray and 20 pixels, respectively. At this time, in the defective generation range of gray scale 15 to 35, the lower limit and the upper limit 15 and 35 gray, respectively, are set as the first and second inversion reference values IR1 and IR2, and 20, which is the allowable amount of defective pixels, is set. The third inversion reference value IR3 is set.

The low voltage mode “LL” and “L” are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, and the inversion mode is used as a column. The first to third power reference values PR1, PR2, and PR3, the first to third share reference values SR1, SR2, and SR3, and the first to third inversion reference values IR1 which are set to the inversion, are experimental results. , IR2, IR3) are input to the storage 130. The first to third power reference values PR1, PR2 and PR3, the first to third share reference values SR1, SR2 and SR3, and the first to third inversion reference values IR1, IR2, and IR3, which are experimental results. ) Are only examples, and other values may be used as necessary.

FIG. 10 is a schematic diagram of an image according to a second embodiment of the present invention, and FIGS. 11A and 11B are histograms of digital video data obtained by analyzing the image of FIG. 10 on a line basis.

As illustrated in FIG. 10, an image implemented on one screen may include a combination pattern 252 and a gray pattern 254 of black and white. The digital video data in line units corresponding to the combination pattern 252 shown in FIG. 10 corresponds to the histogram of FIG. 11A, and the digital video data in line units corresponding to the gray pattern 254 shown in FIG. 10 is illustrated in FIG. 11B. This may correspond to the histogram of.

In FIG. 11A, the horizontal axis is a pixel value of a gray scale having a value of, for example, 0 to 63, and the vertical axis represents the number of pixels of the corresponding gray level. When the low voltage mode is applied to the power control circuit PWRC in the line unit image corresponding to the combination pattern 152 of black and white, digital video data having a histogram distribution as shown in FIG. 11A is applied to the driving mode selection circuit 120. When input, the power control circuit PWRC is driven in the low voltage mode because the number of gray defective pixels between the first and second power reference values PR1 and PR2 is less than or equal to the third power reference value PR3 which defines the defective tolerance amount to 20. . At this time, each of the first and second power control circuits PWRC1 and PWRC2 is applied as "LL" to implement an image in a line unit corresponding to the combination pattern 252 of black and white.

When digital video data having a histogram as shown in FIG. 11B is input to the driving mode selection circuit 120, the third power reference value in which the number of gray defective pixels between the first and second power reference values PR1 and PR2 is defined as 20 defective tolerances is defined. Since it is above PR3, the power control circuit PWRC is driven in the normal mode. At this time, each of the first and second power control circuits PWRC1 and PWRC2 is applied as "HL" or "LH" in order to implement an image of a line unit corresponding to the gray pattern 254.

In the second embodiment of the present invention, the drive mode selection circuit 120 for dividing the attributes of the image by analyzing the digital video data on a line-by-line basis, the power control circuit (PWRC) ) And the charge share circuit CSC are set low, and the source driver 114 can be driven in a low voltage driving mode in which the polarity control signal POL is set to column inversion. In this case, the source driver 114 may be driven in the normal mode in which the power control circuit PWRC and the charge share circuit CSC are set high and the polarity control signal POL is set to 2 dot inversion. Therefore, in the second embodiment of the present invention, the power consumption can be reduced by automatically changing the driving mode of the source driver according to the attribute of the image in which the digital video data is divided into lines.

12 is a flowchart illustrating a method of driving a liquid crystal display according to a second embodiment of the present invention. The driving method of the liquid crystal display device 110 according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 5 and 10 to 11b as follows.

As in the first step S01, the low voltage modes “LL” and “L” are applied to each of the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114. By setting the column inversion, the image is divided into units of lines to extract the defective generation range of the gray scale and the allowable amount of the defective pixels, and store them in the storage unit 130.

As in the second step SO2, through the histogram analysis of the digital video data input to the driving mode selection circuit, the generation range of the gray scale and the number of the defective pixels are compared with the reference value stored in the storage unit 130 in line units. Set the power control circuit to "HL / LH" or "LL", the charge share circuit to "H" or "L", and the polarity control signal (POL) to column inversion or 2 dot inversion, To drive the source driver 114.

Claims (11)

A liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells;
A source driver which supplies data and gate control signals and power signals to each of the plurality of data lines and the plurality of gate lines, and includes a power control circuit and a charge share circuit;
When the source driver operates the power control circuit and the charge share circuit in a low power mode, the power that is allowed in each of the first and second gray periods in which a failure occurs and the first and second gray periods, respectively. A storage unit to which a power reference value and a share reference value, which are the number of gray defective pixels, for each of the control circuit and the charge share circuit are input;
The digital video data is input, and the number of gray defective pixels of the digital video data corresponding to the first and second gray periods is compared with the power reference value and the share reference value, respectively, so that each of the power control circuit and the charge share circuit is determined. A drive mode selection circuit which sets to "H" or "L";
Liquid crystal display comprising a.
The method of claim 1,
In the storage unit, a third gray period in which a failure occurs when the source driver operates in a column inversion, and an inversion reference value, which is the number of gray defective pixels that can be allowed in the third gray period, is input, and the driving is performed. The mode selection circuit compares the number of gray defective pixels of the digital video data generated in the third gray period with the inversion reference value, and applies a column inversion or two dot inversion signal as a polarity control signal to the source driver. Liquid crystal display device characterized in that.
The method of claim 2,
The drive mode selection circuit,
A first selection circuit for selecting the power control circuit as "H" or "L", a second selection circuit for selecting the charge share circuit as "H" or "L", and a column control version of the polarity control signal Or a third selection circuit for selecting with 2 dot inversion.
The method of claim 3, wherein
The first selection circuit,
An operation unit configured to analyze the digital video data input in real time and calculate the number of gray defective pixels between first and second reference values, which are a lower limit and an upper limit of the first gray section in which a defect occurs;
The third reference value, which is the allowable amount of the gray defective pixels of the digital video data and the gray defective pixels, is compared, and "H" or "L" is applied to the power control circuit according to the gray defective pixels of the digital video data. A mode determination unit to determine whether to apply;
Liquid crystal display comprising a.
The method of claim 3, wherein
The second selection circuit,
A calculator configured to analyze the digital video data input in real time and calculate the number of gray defective pixels between first and second reference values, which are a lower limit and an upper limit of the second gray section in which a defect occurs;
A third reference value, which is an allowable amount of the gray defective pixels of the digital video data and the number of gray defective pixels, is compared, and according to the gray defective pixels of the digital video data, an "H" or "L" value is assigned to the charge share circuit. A mode determination unit for determining the application of "
Liquid crystal display comprising a.
The method of claim 3, wherein
The third selection circuit,
An operation unit configured to analyze the digital video data input in real time and calculate the number of gray defective pixels between first and second reference values, which are a lower limit and an upper limit of the third gray section in which a defect occurs;
A third reference value, which is an allowable amount of the gray defective pixels and the gray defective pixels of the digital video data, is compared and the polarity control signal is column inversion or two dot inversion according to the gray defective pixels in the digital video data. A mode determination unit to set to;
Liquid crystal display comprising a.
The method of claim 1,
And the storage unit uses EEPROM.
The method according to any one of claims 1 to 7,
And the digital video data input to the driving mode selection circuit is in units of frames or lines.
A liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells, and supplying control signals and power signals of data and gates to the plurality of data lines and the plurality of gate lines, respectively, A driving method of a liquid crystal display device comprising a source driver including a charge share circuit,
"L" is applied to each of the power control circuit and the charge share circuit to set first and second gray sections in which a defect occurs, and is a defective allowance for the number of defective gray pixels in the first and second gray sections. Inputting the first and second reference values into the storage;
In the digital video data inputted to the driving mode selection circuit, the number of defective gray pixels corresponding to the gray section is compared with the first and second reference values, so that the power control circuit and the charge share circuit are each “L” or “H”. Setting to;
Method of driving a liquid crystal display device comprising a.
The method of claim 9,
Applying a column inversion signal as a polarity control signal to set the third gray period in which a failure occurs, and inputting a third reference value, which is a defective allowance for the number of defective gray pixels in the third gray period, to a storage unit; And comparing the number of defective gray pixels corresponding to the gray interval in the digital video data input to the driving mode selection circuit with the third reference value and selecting the column inversion or the two dot inversion as the polarity control signal. Method of driving a liquid crystal display device further comprising.
The method according to claim 9 or 10,
And the digital video data input to the driving mode selection circuit is in units of frames or lines.

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