KR101624513B1 - Liquid crytal display device and Driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of variably supplying power to a source driver and reducing power consumption, and a driving method thereof. The liquid crystal display device includes a plurality of data lines, a plurality of gate lines, A liquid crystal panel including a liquid crystal cell; A source driving part supplying a control signal and a power supply signal of data and a gate to each of the plurality of data lines and the plurality of gate lines and including a power control circuit and a charge share circuit; Wherein the source driver controls the first and second gray intervals in which a failure occurs when the power control circuit and the charge share circuit operate in a low power mode, A storage unit to which a power reference value and a share reference value, which is the number of gray defective pixels for each of the control circuit and the charge share circuit, are input; Digital video data is input and the number of gray defective pixels of the digital video data corresponding to the first and second gray intervals is compared with each of the power reference value and the SHARE reference value to determine whether the power control circuit and the charge- Quot; H "or" L ".

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof that can reduce power consumption by driving a source driver in a normal mode or a low-power mode according to an attribute of an image divided into a frame or a line.

As information technology (IT) develops, flat panel displays are becoming more and more important as visual information delivery media. In order to secure more advanced competitiveness, low power consumption, thinness, light weight, and high image quality are required. There is a liquid crystal display (LCD) that displays an image using optical anisotropy of liquid crystal by a typical flat panel display. The liquid crystal display device has advantages such as thinness, small size, low power consumption and high image quality.

The liquid crystal display device can display a desired image by separately supplying image information to a plurality of pixels arranged in a matrix form and adjusting the light transmittance of the liquid crystal layer corresponding to each of the plurality of pixels. Accordingly, a liquid crystal display device includes a liquid crystal panel in which a plurality of pixels, which is a minimum unit for realizing an image, are arranged in a matrix form, and a driver for driving the liquid crystal panel. Since the liquid crystal display device can not emit light by itself, a backlight unit for supplying light to the liquid crystal display device is provided. The driving unit includes a timing controller and a source driving unit.

Hereinafter, a conventional liquid crystal display device will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of a conventional liquid crystal display device, and FIG. 2 is a diagram showing a relationship between a timing controller and a source driver according to the related art.

1, the liquid crystal display 10 according to the related art includes a liquid crystal panel 12, a source driver 14, and a timing controller 18. The liquid crystal panel 12 is provided with a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, a plurality of thin film transistors, a plurality of data lines D1 to Dm and gate lines G1 to Gn A plurality of m × n liquid crystal cells Clc are arranged in the form of a matrix formed by a cross structure. The source driver 14 includes a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn, A data control signal, a power supply signal, a gate control signal, and a power supply signal to the source driver 14. The source driver 14 includes a power control circuit (PWRC) and a charge share circuit (CSC).

Although not shown in detail in the figure, the liquid crystal panel 12 includes upper and lower substrates, and a black matrix, a color filter, and a common electrode are formed on the upper substrate. The common electrode is formed on the upper substrate in the case of a vertical field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) In the case of the electric field driving method, it is formed on the lower substrate together with the pixel electrode.

2, the timing controller 18 receiving data enable and vertical / horizontal synchronizing signals Vsync and Hsync from a system (not shown) receives a gate start pulse (GSP) , Starting voltage (VST). A first signal generator 18a for generating a gate clock signal GCLK and a gate output enable signal GOE, a source output enable signal SOE and a polarity control signal Polarity A second signal generator 18b for generating digital video data RGB according to the liquid crystal panel 112 and a third signal generator 18c for supplying the digital video data RGB to the source driver 14 according to the liquid crystal panel 112, .

The driving method of the source driver 14 is generally divided into a normal mode and a low voltage driving mode. In general, the source driver 14 sets the normal mode to the normal mode as shown in FIG. 2 at the beginning of fabrication in order to prevent image defects from occurring. In other words, the power control circuit PWRC and the charge share circuit of the source driver 14 are set to be High respectively, and the polarity control signal POL is set to a dot inversion ) Mode.

The power control circuit PWRC includes first and second power control circuits PWRC1 and PWRC2 and supplies power to the source driver 14 according to a combination of voltages applied to the first and second power control circuits PWRC1 and PWRC2. And determines the power consumption to be applied. "HH", "HL", "LH", and "LL" can be applied to the first and second power control circuits PWRC1 and PWRC2, respectively. "HH", "HL", and "LH" are defined as High and "LL" is defined as Low. Normally, it is set that "HL" or "LH" is applied to the first and second power control circuits PWRCl and PWRC2.

The power control circuit PWRC and the charge shute circuit CSC of the source driver 14 are set to Low and the polarity control signal POL is set to a column inversion inversion in which a vertical line is visually perceived differently can be used to reduce the power consumption of the source driver 14 to the maximum. However, in a specific pattern, a vertical dimming (DIM) And a vertical band defect in which a band having a thickness of about 2 pixels is visually perceived differently due to the reciprocating motion of the liquid crystal panel in the left and right direction may be generated.

Since the normal driving mode of the source driver 14 is set and used at the initial stage of manufacture in the liquid crystal display device according to the related art as described above, it is difficult to flexibly respond to the image change. In other words, unnecessary power can be consumed by applying the normal drive mode to an image which can sufficiently operate in the low consumption drive mode.

In order to solve the above problems, the present invention provides a liquid crystal display device capable of reducing power consumption by converting a source driver into a low power mode or a normal mode according to an attribute of an image divided into frames or lines, and a driving method thereof And to provide the above objects.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells; A source driving part supplying a control signal and a power supply signal of data and a gate to each of the plurality of data lines and the plurality of gate lines and including a power control circuit and a charge share circuit; Wherein the source driver controls the first and second gray intervals in which a failure occurs when the power control circuit and the charge share circuit operate in a low power mode, A storage unit to which a power reference value and a share reference value, which is the number of gray defective pixels for each of the control circuit and the charge share circuit, are input; Digital video data is inputted and the number of gray defective pixels of the digital video data corresponding to the first and second gray intervals is compared with each of the power reference value and the SHARE reference value to determine the power control circuit and the charge share circuit, Quot; H "or" L ".

In the above-described liquid crystal display device, the storage section may further include a third gray section in which a defect occurs when the source driver operates in a column-inversion version, and a third gray section in which a defective gray- And the drive mode selection circuit compares the number of gray defective pixels of the digital video data generated in the third gray interval with the reference value of inversion to determine whether the polarity control signal is a column inversion Or a 2-dot version signal is applied.

In the liquid crystal display device as described above, the drive mode selection circuit may include a first selection circuit for selecting the power control circuit as "H" or "L ", and the charge- And a third selection circuit for selecting the polarity control signal as a column-inversion or a two-dot-inversion.

In the liquid crystal display device as described above, the first selection circuit may analyze the digital video data input in real time, and determine the difference between the first and second reference values, which are the lower limit value and the upper limit value of the first gray interval, An arithmetic unit for calculating the number of gray defective pixels; H "or" L "to the power control circuit according to the number of gray defective pixels of the digital video data, and compares the number of gray defective pixels of the digital video data with a third reference value, And a mode determining unit for determining an application of the voltage.

In the above-described liquid crystal display device, the second selection circuit may analyze the digital video data input in real time, and determine the difference between the first and second reference values, which are the lower limit value and the upper limit value of the second gray interval, An arithmetic unit for calculating the number of gray defective pixels; H "or" L " to the charge share circuit in accordance with the number of gray defective pixels of the digital video data, and compares the number of gray defective pixels of the digital video data with a third reference value, &Quot; and a mode decision unit for deciding the application of "

In the liquid crystal display device as described above, the third selection circuit may analyze the digital video data input in real time, and determine the difference between the first and second reference values, which are the lower limit value and the upper limit value of the third gray interval, An arithmetic unit for calculating the number of gray defective pixels; Comparing the number of gray defective pixels of the digital video data with a third reference value which is a tolerable amount of the number of gray defective pixels and outputting the polarity control signal as a column inversion version or a 2 dot inversion version in accordance with the gray defective pixel number of the digital video data And a mode determining unit for determining a mode to be set.

In the liquid crystal display device as described above, the storage unit may use an EEPROM.

In the liquid crystal display device as described above, the digital video data input to the drive mode selection circuit is frame-by-frame or line-by-line.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device including a liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells, And a source driver which supplies a control signal and a power supply signal of data and a gate to each of the gate wirings and includes a power control circuit and a charge share circuit, the driving method comprising: The first and second gray intervals in which defects are generated by applying "L" to the first and second gray intervals are set, and the first and second reference values, which are the defective tolerances for the number of defective gray pixels in the first and second gray intervals, Inputting; Quot; L "or" H "level of the power control circuit and the charge share circuit by comparing the number of defective gray pixels corresponding to the gray section with the first and second reference values, And a step of setting the value of the parameter.

In the method of driving a liquid crystal display device as described above, the third gray section in which a failure is generated by applying a version signal as a column to a polarity control signal is set, and a defect tolerance to the number of defective gray pixels in the third gray section And comparing the number of defective gray pixels corresponding to the gray section with the third reference value in the digital video data input to the drive mode selection circuit, Column inversion or two dot inversion. ≪ Desc / Clms Page number 12 >

In the driving method of a liquid crystal display device as described above, the digital video data input to the driving mode selection circuit is a frame unit or a line unit.

The liquid crystal display device and the driving method thereof according to the present invention can automatically change the driving mode of the source driver according to the attribute of an image divided into a frame or a line to reduce power consumption. In other words, in the case of an image having a medium brightness, the power control circuit PWRC and the charge share circuit CSC are set to high and the source is set to the normal mode in which the polarity control signal POL is set to the two- Voltage drive mode in which the power control circuit PWRC and the charge share circuit CSC are set to a low level and the polarity control signal POL is set to a column inversion mode in the case of a bright or dark image, The power source can be reduced by driving the source driver. Therefore, in the case of a liquid crystal display device used in a notebook computer, the use time of the battery can be increased by reducing the power consumption.

1 is a schematic view of a conventional liquid crystal display
2 is a diagram showing a relationship between a timing controller and a source driver according to the prior art.
3 is a schematic view of a liquid crystal display device according to the present invention
4 is a diagram showing the relationship between the timing controller and the source driver according to the present invention.
5 is a detailed view of the drive mode selection circuit according to the present invention
6 and 7 are histograms of digital video data of one frame according to the present invention
8 is a flow chart of a driving method of a liquid crystal display according to the present invention
9A and 9B are schematic diagrams of images analyzed on a frame-by-frame basis according to the first embodiment of the present invention
10 is a schematic diagram of an image according to the second embodiment of the present invention
FIGS. 11A and 11B are histograms of digital video data obtained by analyzing the image of FIG. 10 on a line-
12 is a flow chart of a method of driving a liquid crystal display according to a second embodiment of the present invention

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1st Example

3 is a schematic view of a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display 110 according to the first embodiment of the present invention includes a liquid crystal panel 112, a source driver 114, and a timing controller 118. The timing controller 118 includes a drive mode selection circuit 120 and a storage unit 130.

The liquid crystal panel 112 is provided with a plurality of data lines D1 to Dm, a plurality of gate lines G1 to Gn, a plurality of thin film transistors, a plurality of data lines D1 to Dm and gate lines G1 to Gn A plurality of m × n liquid crystal cells Clc are arranged in the form of a matrix formed by a cross structure. The source driver 114 includes a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn, A data control signal, a power supply signal, a gate control signal, and a power supply signal.

Although not shown in detail in the drawings, the liquid crystal panel 112 includes upper and lower substrates, and a black matrix, a color filter, and a common electrode are formed on the upper substrate. The common electrode is formed on the upper substrate in the case of a vertical field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) In the case of the electric field driving method, it is formed on the lower substrate together with the pixel electrode.

4 is a diagram showing the relationship between the timing controller and the source driver according to the first embodiment of the present invention.

Referring to FIG. 4, the source driver 114 includes a power control circuit (PWRC) and a charge share circuit (CSC). The power control circuit PWRC includes first and second power control circuits PWRC1 and PWRC2. The source driver 114 determines a combination of voltages applied to the first and second power control circuits PWRC1 and PWRC2. "HH", "HL", "LH", and "LL" may be applied to the first and second power control circuits PWRC1 and PWRC2, respectively. HIGH "is defined when" HH "," HL ", and" LH "are applied to the first and second power control circuits PWRC1 and PWRC2, and is defined as Low when" LL " .

4, a timing controller 118 receiving data enable and vertical / horizontal synchronizing signals Vsync and Hsync from a system (not shown) receives a gate start pulse (GSP) , Starting voltage (VST). A first signal generator 118a for generating a gate clock signal GCLK and a gate output enable signal GOE, a source output enable (SOE) and a polarity control signal Polarity And a third signal generating unit 118c for supplying the digital video data to the source driver 114 by rearranging the input digital video data according to the liquid crystal panel 112 .

The source driver 114 applies a "LL" to the power control circuit PWRC, applies "L" to the charge share circuit, applies a version signal that is a column to the polarity control signal POL A low voltage mode and a mode in which "HL" or "LH" is applied to the power control circuit PWRC, "H" is applied to the charge share circuit, dot inversion) can be selected and driven.

The drive mode selection circuit 120 analyzes input digital video data frame by frame to distinguish the attributes of the image and to select the power control circuit PWRC as high or low based on the analysis result A first selection signal, a second selection circuit for selecting the charge share circuit CSC as High or Low and a second selection circuit for selecting the polarity control signal POL as a column inversion or a two dot inversion And generates a drive mode selection signal including the third selection circuit.

The reference value of the image information stored in the storage unit 130 can be obtained from the actual data when the source driver 114 is set to the low voltage mode. In other words, "LL" and "L", which are the low voltage modes, are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, And analyzes the displayed image to determine the defect occurrence range of the gray scale and the defective pixel tolerance. The storage unit 130 may use an EEPROM.

The driving mode selection circuit 120 analyzes the input digital video data on a frame-by-frame basis to classify the attributes of the image, and outputs the number of defective pixels in the defective occurrence range of the gray scale based on the analysis result to the reference value The source driver 114 is driven in the normal mode when the number of defective pixels in the image information is not less than the reference value and the source driver 114 is driven in the low voltage mode when the number of defective pixels in the image information is not more than the reference value.

LL "and" L "which are the low voltage modes are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, The allowable range of the defective occurrence range of the gray scale and the defective pixel number can be determined. For example, when the low voltage mode "LL" is applied to each of the first and second power control circuits PWRC1 and PWRC2, the gray scale defective generation range and the tolerable number of defective pixels are 15 to 40 gray, 1000 pixels can be determined. At this time, the first and second power reference values PR1 and PR2 are set as the lower limit value and the upper limit value of 15 and 40 gray, respectively, in the defective occurrence range of gray scale of 15 to 40, 3 Set the power reference value (PR3).

When the low voltage mode "L" is applied to the charge sharing circuit CSC, it is possible to determine the defective occurrence range of the gray scale and the tolerable amount of the defective pixel to 15 to 35 gray and 1200 pixels, respectively. At this time, the lower limit value and the upper limit value of 15 and 35 gray are set as the first and second share reference values (SR1 and SR2), respectively, in the failure occurrence range of gray scale of 15 to 35, 3 SHARE reference value (SR3).

Column, it is possible to determine the defective occurrence range of the gray scale and the tolerable amount of the defective pixel to 15 to 35 gray and 900 pixels, respectively. At this time, the lower limit value and the upper limit value of 15 and 35 gray are set to the first and second inversion reference values IR1 and IR2, respectively, in the defective occurrence range of gray scale of 15 to 35, The third inversion reference value IR3 is set.

LL "and" L "which are the low voltage modes are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, The first to third power reference values PR1 to PR3 and the first to third share reference values SR1 to SR3 and the first to third inversion reference values IR1 to SR3, , IR2, and IR3 to the storage unit 130. The first to third power reference values PR1 to PR3 and the first to third share reference values SR1 to SR3 and the first to third inversion reference values IR1 to IR3 ) Is only an example of an abbreviated example, and can be used as a different value if necessary.

The drive mode selection circuit 120 includes a first selection circuit 120a for selecting the first and second power control circuits PWRC1 and PWRC2 as "HL / LH" or "LL", a charge sharing circuit CSC, And a third selection circuit 120c for selecting the polarity control signal POL as a column inversion or a 2-dot version, and a second selection circuit 120b for selecting a column selection signal "H" .

5 is a detailed view of a drive mode selection circuit according to the first embodiment of the present invention.

Referring to FIG. 5, the first selector 120a analyzes the digital video data input in real time on a frame-by-frame basis to determine whether the first and second power reference values PR1 and PR2, which are the lower limit and the upper limit of the gray defect occurrence range, A calculation unit 122 for calculating the number of gray pixels, and a mode determining unit 122 for comparing the number of defective gray pixels of the digital video data with the third power reference value PR3 which is the defective gray allowable amount and determining a normal mode or a low voltage mode And a determination unit 124. [

The arithmetic operation unit 122 includes a first comparator 122a for comparing the gray level of each pixel of one frame of digital video data with a first power reference value PR1, A second comparator 122b for comparing the first and second power reference values PR2 and PR2 and a second comparator 122b for receiving the output of the first and second comparators 122a and 122b and outputting a pixel corresponding to the gray defect of the digital video data RGB And a counter 122c for counting the number of defective gray pixels between the first and second power reference values PR1 and PR2. The mode determining unit 124 determines the normal mode or the low voltage mode according to the comparison result between the third comparing unit 124a and the third comparing unit 124a that compares the number of defective gray pixels with the third power reference value PR3 And a mux 124b.

The second selecting circuit 120b for selecting the charge sharing circuit CSC as "H" or "L " compares the number of defective gray pixels of the digital video data with the third share reference value CSC, And has the same configuration as the first selecting circuit 120a except that the comparison result is applied to the charge sharing circuit CSC.

The third selection circuit 120c for selecting the polarity control signal POL as a column inversion or a 2 dot inversion compares the number of defective gray pixels of the digital video data with the third inverted reference value IR3 which is the defective gray tolerance And has the same configuration as that of the first selecting circuit 120a except that it is set as a column-inversion or a two-dot-inversion according to the comparison result and applies it to the source driver 114. [

6 and 7 are histograms of digital video data of one frame according to the first embodiment of the present invention.

For example, one frame of the digital video data may correspond to the histograms of Figs. 6 and 7. The horizontal axis in FIG. 6 is a pixel value of a gray scale having a value of, for example, 0 to 63, and the vertical axis indicates the number of pixels of the corresponding gray scale. When the low voltage mode is applied to the power control circuit PWRC, when the digital video data having the histogram distribution as shown in FIG. 6 is input to the drive mode selection circuit 120, the first and second power reference values PR1 and PR2 The power control circuit PWRC is driven in the normal mode since the number of gray defective pixels is equal to or larger than the third power reference value PR3 defined as 1000 defective amount. At this time, each of the first and second power control circuits PWRCl and PWRC2 is applied with "HL" or "LH ".

7, when the digital video data having the histogram shown in FIG. 7 is input to the drive mode selection circuit 120, the third power reference value defining the number of gray defective pixels between the first and second power reference values PR1 and PR2 is 1000 (PR3), the power control circuit PWRC is driven in the low voltage mode. At this time, each of the first and second power control circuits PWRC1 and PWRC2 is applied with "LL ".

The drive mode selection circuit 120 according to the present invention sets the power control circuit PWRC and the charge share circuit CSC to low and outputs the polarity control signal POL to the column The power source control circuit PWRC and the charge share circuit CSC are set to high in the case of an image having medium brightness and the polarity of the polarity It is possible to drive the source driver 114 in the normal mode in which the control signal POL is set to the 2-dot version.

8 is a flowchart illustrating a method of driving a liquid crystal display according to a first embodiment of the present invention. A driving method of the liquid crystal display device 110 according to the first embodiment of the present invention will now be described with reference to FIGS. 3 to 8. FIG.

LL "and" L "which are the low voltage modes are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114 as in the first step S01 , An inversion mode is set as a column inversion to extract a tolerable range of the defective generation range of the gary scale and the defective pixel count and stores it in the storage unit 130. [

The defective generation range of the gray scale and the number of defective pixels are compared with the reference value stored in the storage unit 130 through the histogram analysis of the digital video data input to the drive mode selection circuit as in the second step SO2, Is set to a column inversion or a 2-dot inversion to set the charge control circuit to "HL / LH" or "LL", the charge share circuit to "H" (Not shown).

The liquid crystal display according to the first embodiment of the present invention can automatically reduce the power consumption by automatically varying the driving mode of the source driver 114 according to the attribute of the image divided in frame units. However, in general, a frame-by-frame image may have a mixture of bright or dark brightness images and a mixture of medium brightness brightness. In other words, a combined pattern of black and white and a gray pattern may exist in one frame.

9A and 9B are schematic diagrams of images analyzed on a frame-by-frame basis according to the first embodiment of the present invention.

The image in the frame unit includes a case of being composed of a combination pattern 152 of black and white as shown in Fig. 9A and a case of being divided into a combination pattern 152 of black and white and a gray pattern 154 as shown in Fig. 9B can do.

As shown in FIG. 9A, in the case of the black / white combination pattern 152, since the number of defective pixels in the pixel information is usually smaller than the reference value, the first and second power control circuits LL "and" L ", which are the low voltage modes, to the charge sharing circuits PWRC1 and PWRC2 and the charge share circuit CSC, respectively.

9B, when the number of defective pixels in the pixel information is equal to or larger than the reference value as a whole, or the number of defective pixels in the pixel information as a whole is equal to or smaller than the reference value, the gray- The defective occurrence range may be exceeded. Even in this case, the portion constituted by the combination pattern 152 of black and white may have the number of defective pixels in the pixel information equal to or less than the reference value. However, in the case of Fig. 9B, since the attribute of the image is analyzed on a frame-by-frame basis, the first and second power control circuits PWRC1 and PWRC2 of the source driver 114 shown in Fig. HL / LH " and "H" should be applied to the respective CSCs.

Second Example

The second embodiment of the present invention differs from the first embodiment of the present invention in that the digital video data is divided into frames and the attributes of the images are analyzed. In the second embodiment of the present invention, A liquid crystal display device capable of automatically changing a driving mode and reducing power consumption is proposed. For convenience of explanation, the drawings of the first embodiment overlapping with the second embodiment of the present invention are referred to, and the same reference numerals are used for the same components.

The liquid crystal display device according to the second embodiment of the present invention has the same configuration as that of the first embodiment shown in Figs. 3 to 5 except that in the first embodiment of the present invention, the drive mode selection circuit 120 of Fig. In the second embodiment of the present invention, the drive mode selection circuit 120 of FIG. 4 analyzes the digital video data on a horizontal line basis to classify the attributes of the image by analyzing the video data frame by frame. There is a difference.

4, the driving mode selection circuit 120 analyzes input digital video data on a line-by-line basis to classify attributes of an image, and outputs a power control circuit PWRC as a high or low A second selection circuit for selecting the charge sharing circuit CSC as High or Low and a second selection circuit for selecting the polarity control signal POL as a column inversion or 2 And generates a drive mode selection signal including a third selection circuit for selecting the dot inversion.

The reference value of the image information stored in the storage unit 130 can be obtained from the actual data when the source driver 114 is set to the low voltage mode. In other words, "LL" and "L", which are the low voltage modes, are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, And then analyzes the displayed image in line units to determine the defect occurrence range of the gray scale and the defective pixel tolerance.

The drive mode selection circuit 120 analyzes the inputted digital video data in units of lines to classify the attributes of the image and outputs the number of defective pixels in the defective occurrence range of the gray scale based on the analysis result to the reference value The source driver 114 is driven in the normal mode when the number of defective pixels in the image information is not less than the reference value and the source driver 114 is driven in the low voltage mode when the number of defective pixels in the image information is not more than the reference value.

LL "and" L "which are the low voltage modes are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, The allowable range of the defective occurrence range of the gray scale and the defective pixel number can be determined.

For example, when the low voltage mode "LL" is applied to each of the first and second power control circuits PWRC1 and PWRC2, the tolerance of the gray scale defect occurrence range and the defective pixel count 15 to 40 gray, and 20 pixels. At this time, the first and second power reference values PR1 and PR2 are set as the lower limit value and the upper limit value of 15 and 40 gray, respectively, in the failure occurrence range of gray scale of 15 to 40, 3 Set the power reference value (PR3).

When the low voltage mode "L" is applied to the charge sharing circuit CSC, it is possible to determine the defective occurrence range of the gray scale and the tolerable amount of the defective pixel to 15 to 35 gray and 20 pixels, respectively. At this time, the lower limit value and the upper limit value of 15 and 35 gray are respectively set as the first and second share reference values (SR1 and SR2) in the defective occurrence range of gray scale of 15 to 35, 3 SHARE reference value (SR3).

Column, it is possible to determine the defective occurrence range of the gray scale and the tolerable amount of the defective pixel to 15 to 35 gray and 20 pixels, respectively. At this time, the lower and upper limit values of 15 and 35 gray are set as the first and second inversion reference values IR1 and IR2, respectively, in the defective occurrence range of gray scale of 15 to 35, The third inversion reference value IR3 is set.

LL "and" L "which are the low voltage modes are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114, The first to third power reference values PR1 to PR3 and the first to third share reference values SR1 to SR3 and the first to third inversion reference values IR1 to SR3, , IR2, and IR3 to the storage unit 130. The first to third power reference values PR1 to PR3 and the first to third share reference values SR1 to SR3 and the first to third inversion reference values IR1 to IR3 ) Is only an example of an abbreviated example, and can be used as a different value if necessary.

FIG. 10 is a schematic diagram of an image according to a second embodiment of the present invention, and FIGS. 11A and 11B are histograms of digital video data obtained by analyzing the image of FIG. 10 line by line.

As shown in FIG. 10, an image to be formed on one screen may be composed of a combination pattern 252 of black and white and a gray pattern 254. Digital video data corresponding to the combination pattern 252 shown in Fig. 10 corresponds to the histogram of Fig. 11A, and digital video data corresponding to the gray pattern 254 shown in Fig. As shown in FIG.

In Fig. 11A, the horizontal axis represents a pixel value of a gray scale having a value of, for example, 0 to 63, and the vertical axis represents the number of pixels of the corresponding gray scale. When the low-voltage mode is applied to the power control circuit PWRC for the line-by-line image corresponding to the combination pattern 152 of black and white, the digital video data having the histogram distribution shown in FIG. 11A is supplied to the drive mode selection circuit 120 The power control circuit PWRC is driven in the low voltage mode since the number of gray defective pixels between the first and second power reference values PR1 and PR2 is equal to or less than the third power reference value PR3 which defines the defective tolerance as 20 . At this time, the first and second power control circuits PWRC1 and PWRC2 are respectively applied with "LL" to implement an image in a line unit corresponding to the combination pattern 252 of black and white.

When digital video data having a histogram as shown in FIG. 11B is input to the drive mode selection circuit 120, the number of gray defective pixels between the first and second power reference values PR1 and PR2 is set to a third power reference value (PR3), the power control circuit PWRC is driven in the normal mode. At this time, each of the first and second power control circuits PWRC1 and PWRC2 is applied with "HL" or "LH" to implement an image in a line unit corresponding to the gray pattern 254.

In the second embodiment of the present invention, the driving mode selection circuit 120 for analyzing the digital video data line by line and classifying the attributes of the image, ) And the charge sharing circuit CSC to a low level and to drive the source driver 114 in a low voltage driving mode in which the polarity control signal POL is set to a column inversion, The power control circuit PWRC and the charge share circuit CSC can be set high and the source driver 114 can be driven in the normal mode in which the polarity control signal POL is set to the two dot version. Therefore, according to the second embodiment of the present invention, the driving mode of the source driver can be automatically changed according to the attribute of the image obtained by dividing the digital video data line by line, thereby reducing power consumption.

12 is a flowchart of a method of driving a liquid crystal display according to a second embodiment of the present invention. A driving method of the liquid crystal display device 110 according to the second embodiment of the present invention will now be described with reference to FIGS. 3 to 5 and FIGS. 10 to 11B.

LL "and" L "which are the low voltage modes are applied to the first and second power control circuits PWRC1 and PWRC2 and the charge share circuit CSC of the source driver 114 as in the first step S01 , And columns, and divides the images in units of lines to extract the defective occurrence range of the gray scale and the allowable amount of the defective pixels, and stores them in the storage unit 130.

The defective occurrence range of the gray scale and the number of defective pixels are compared with the reference value stored in the storage unit 130 on a line-by-line basis through the histogram analysis of the digital video data input to the drive mode selection circuit as in the second step SO2 Voltage mode or normal mode by setting the power control circuit to "HL / LH" or "LL", the charge share circuit to "H" or "L", the polarity control signal To drive the source driver 114.

Claims (11)

A liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells;
A source driving part supplying a control signal and a power supply signal of data and a gate to each of the plurality of data lines and the plurality of gate lines and including a power control circuit and a charge share circuit;
A power reference value including a first gray section in which a failure occurs when the power control circuit of the source driver operates in a low power mode and a gray defect pixel number acceptable in the first gray section, A SHARE reference value including a second gray interval in which a defect occurs when the circuit operates in a low power mode and a number of gray defective pixels acceptable in the second gray interval and a defect when the source driver operates in a column version A storage unit for storing an inversion reference value including a gray defect pixel number acceptable in the third gray interval;
The digital video data is input and the power control circuit is set to "H" or "L" by comparing the number of gray defective pixels of the digital video data corresponding to the first gray section with the allowable number of gray defective pixels of the power reference value, Quot ;, and sets the charge share circuit to "H" or "L" by comparing the number of gray defective pixels of the digital video data corresponding to the second gray section with the allowable number of gray defective pixels of the share reference value And comparing the number of gray defective pixels of the digital video data corresponding to the third gray interval with the allowable number of gray defective pixels of the inversion reference value to output a column inversion or two dots A drive mode selection circuit for applying an inversion signal;
And the liquid crystal display device.
delete The method according to claim 1,
Wherein the drive mode selection circuit comprises:
A first selection circuit for selecting said power control circuit to "H" or "L ", a second selection circuit for selecting said charge share circuit for" H "or" L " And a third selection circuit for selecting one of the two-dot-inversion versions.
The method of claim 3,
Wherein the first selection circuit comprises:
An arithmetic unit for analyzing the digital video data input in real time to calculate the number of gray defective pixels between the first and second reference values which are the lower limit value and the upper limit value of the first gray interval in which defects occur;
H "or" L "to the power control circuit according to the number of gray defective pixels of the digital video data, and compares the gray defect pixel count of the digital video data with a third reference value which is the allowable gray defective pixel count, A mode determining unit for determining an application of the voltage;
And the liquid crystal display device.
The method of claim 3,
Wherein the second selection circuit comprises:
An arithmetic unit for analyzing the digital video data input in real time to calculate the number of gray defective pixels between the first and second reference values which are the lower limit and the upper limit of the second gray interval in which defects occur;
H "or" L "in the charge sharing circuit in accordance with the number of gray defective pixels of the digital video data, and compares the gray defect pixel count of the digital video data with the third reference value which is the allowable gray defective pixel count ≪ / RTI >
And the liquid crystal display device.
The method of claim 3,
Wherein the third selection circuit comprises:
An arithmetic unit for analyzing the digital video data input in real time to calculate the number of gray defective pixels between the first and second reference values which are the lower limit and the upper limit value of the third gray interval in which defects occur;
Comparing the number of gray defective pixels of the digital video data with a third reference value which is the allowable number of gray defective pixels and outputting the polarity control signal as a column inversion or a 2 dot inversion A mode determining unit for determining a mode to be set;
And the liquid crystal display device.
The method according to claim 1,
Wherein the storage unit uses an EEPROM.
8. The method according to any one of claims 1 to 7,
Wherein the digital video data input to the drive mode selection circuit is frame-by-frame or line-by-line.
A liquid crystal panel including a plurality of data lines, a plurality of gate lines, and a plurality of liquid crystal cells, and a control circuit for supplying data and gate control signals and power supply signals to the plurality of data lines and the plurality of gate lines, A driving method of a liquid crystal display including a source driver including a charge sharing circuit,
A first gray level in which a failure occurs is set by applying "L" to the power control circuit, a first reference value which is a defective tolerable level with respect to the number of gray defective pixels in the first gray interval is input to the storage unit, A second gray section in which a failure occurs by applying "L" to the circuit, and a second reference value which is a defective tolerable amount to the number of gray defective pixels in the second gray section is input to the storage section, Setting a third gray interval in which a failure occurs by applying an inversion signal and inputting a third reference value, which is a defective allowable amount to the number of gray defective pixels in the third gray interval, to the storage unit;
The power control circuit sets the power control circuit to "L" or "H" by comparing the number of gray defective pixels corresponding to the first gray section with the first reference value in the digital video data input to the drive mode selection circuit, Wherein said charge sharing circuit is set to "L" or "H" by comparing the number of gray defective pixels corresponding to said second gray section with said second reference value in said digital video data input to said selection circuit, Comparing the number of gray defective pixels corresponding to the third gray interval with the third reference value in the digital video data input to the circuit, and applying a column inversion or a 2 dot inversion signal to the polarity control signal;
And a driving method of the liquid crystal display device.
delete 10. The method of claim 9,
Wherein the digital video data input to the drive mode selection circuit is frame-by-frame or line-by-line.

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