KR20140047299A - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device. According to one embodiment of the present invention, the liquid crystal display device includes a data driver which applies a data signal to a liquid crystal panel; a gate driver which applies a gate signal to the liquid panel; a timing controller including a power control part; and a gray scale modulation part. According to one embodiment of the present invention, the liquid crystal display device further includes an information signal. [Reference numerals] (2) Data drive; (21) Power control circuit; (22) Charge share circuit; (5) Power control part; (51) Power control signal generator; (52) Charge share control signal generator; (53) Inversion control signal generator; (54) Tone modulation part; (6) Storage part; (AA) First control signal; (BB) Second control signal; (CC) Third control signal

Description

[0001] Liquid crystal display device [0002]

The present invention relates to a liquid crystal display device.

Recently, various display devices have been developed. Examples of display devices include a cathode ray tube, a liquid crystal display device, a plasma display device, an organic light emitting display device, and a field emission display device. Of these, the liquid crystal display device can be made light and thin with less power consumption than conventional CRTs. BACKGROUND ART LCDs are widely used in small display devices suitable for portable use, such as notebooks, smartphones, and tablet computers. However, as the liquid crystal display device becomes more portable, the problem of reducing the power consumption of the liquid crystal display device has emerged as an important factor, and research on the power consumption is being actively conducted as an important research task.

The present invention provides a liquid crystal display device that reduces power consumption.

The present invention provides a liquid crystal display that solves the problem of increased power consumption when using various power consumption reduction functions at the same time.

According to the present invention, a liquid crystal display device controls a liquid crystal panel, a data driver for applying a data signal to the liquid crystal panel, a gate driver for applying a gate signal to the liquid crystal panel, the data driver and the gate driver, A timing controller including; a power controller included in the timing controller; a power control unit including a gradation modulation unit; and a storage unit storing a first information signal including an unknown gradation region for supplying to the gradation modulation unit. Determining whether the gray level of each pixel of the video data is included in the unknown gray level area, and modulating the gray level of the pixel according to the result, wherein the modulated pixel is applied to the data driver as the data signal.

The present invention can reduce the power consumption through the power control circuit, charge share circuit and inversion driving. According to the present invention, when the gray level of the input data is in an unrecognized (region where the human visually does not recognize), for example, in the range of 242 to 255 gray levels, the power consumption can be reduced by modulating to 242 gray levels, which is the minimum gray level of the recognition range. .

1 is a block diagram of a liquid crystal display according to the present invention.
2A and 2B are column inversion driving schemes.
3A and 3B show a 2-dot inversion driving method
4 is a circuit diagram related to a charge share circuit.
5 is an operation waveform diagram of a charge share circuit.
6 is a graph showing an unrecognized range according to gradation modulation
7 is a block diagram of a gray scale modulation unit;
8 is a block diagram of a power control unit according to the present invention.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to the present invention.

Referring to FIG. 1, a liquid crystal display according to the present invention may include a liquid crystal panel 1, a gate driver 3, a data driver 2, and a timing controller 4. The liquid crystal panel 1 includes a plurality of data wires D1 to Dn, a plurality of gate wires G1 to Gn, a plurality of thin film transistors, a plurality of data wires D1 to Dn, and a gate wire G1 to Gn. A plurality of M × N liquid crystal cells may be formed in a matrix formed by a cross structure.

Although not shown in detail in the drawing, the liquid crystal panel 1 includes an upper substrate and a lower substrate, and a black matrix, a color filter, and a common electrode are formed on the upper substrate. The common electrode is formed on the upper substrate in the case of a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode. In the case of the same horizontal electric field driving method, it may be formed on the lower substrate together with the pixel electrode.

The timing controller 4 receives timing signals such as vertical / horizontal synchronization signals Vsync and Hsync, data enable, and clock signal CLK from a system (not shown). And control signals DDC and GDC for controlling the operation timing of the gate driver 3. The gate control signals GDC may include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. have. The data control signals DDC include a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and a polarity control signal. POL) and the like. The timing controller 4 may rearrange the digital video data RGB input from the system to match the resolution of the liquid crystal panel 1 and supply the digital video data RGB to the data driver 2. In addition, the timing controller 4 may include a power control unit 5 for analyzing digital video data RGB input from the system and performing power control based on the analysis result.

The gate driver 3 includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn. A plurality of gate ICs are configured to sequentially output scan pulses having a pulse width of approximately one horizontal period. The scan pulse is supplied to the gate lines G1 to Gn to select a corresponding gate horizontal line to which a data voltage is applied.

The data driver 2 latches the digital video data RGB under the control of the timing controller 4, and converts the digital video data RGB into an analog positive / negative gamma compensation voltage to positive / negative polarity. A data voltage is generated and the data voltage is supplied to the data lines D1 to Dn. In addition, the data driver 2 may include a power control circuit 21 (a power control circuit) and a charge share circuit 22 (a charge share circuit). The power control circuit and the charge share circuit may be operated by a control signal generated from the power control unit 5 in the timing controller 4.

By the power control circuit 21, the data driver 2 may be a low voltage driving method or a normal driving method. That is, the power consumption of the liquid crystal display when the data driver 2 is a low voltage driving method can be reduced. However, in a specific pattern, when the data driver 2 operates in a low voltage driving method, a problem such as poor image quality such as a block dim phenomenon may appear on the screen. In order to solve this problem, the data driver 2 can be operated in a normal driving manner. At this time, the poor image quality can be prevented, but there is a problem that power consumption increases.

Meanwhile, a method of reducing power consumption of the liquid crystal display device is to change an inversion driving method from a two dot inversion method to a column inversion method.

Inversion driving method is to invert data polarity in unit of excell.

2A, 2B, and 3A and 3B illustrate an inversion driving method. Referring to FIGS. 1, 2A, 2B, and 3A and 3B, first, a video supplied to the liquid crystal panel 1 in the column inversion driving method is shown. As shown in FIGS. 2A and 2B, the polarities of the signals are reversed according to the data lines D1 to Dn and the frame on the liquid crystal panel 1. At this time, the polarity of the polarity control signal POL is inverted in units of the data lines D1 to Dn. In the case of the 2-dot inversion method, the driving method of the liquid crystal panel 1 is provided with a video signal having a polarity opposite to that of all adjacent liquid crystal cells in the horizontal direction in units of 2 dots as shown in FIGS. 3A and 3B. The polarity of is reversed. At this time, the polarity of the polarity control signal POL is inverted every two horizontal periods. The column inversion driving method may reduce power consumption, but there is a problem in that flicker such as a stripe pattern occurs between vertical lines due to the presence of crosstalk between the pixels in the vertical direction. However, the two-dot inversion driving method consumes a lot of power because the polarity of the video signal is inverted every two horizontal periods. However, the flicker generated between frames cancels each other, thereby providing an image having higher image quality than the column inversion method. can do.

The data driver 2 may be provided with a charge share circuit. The charge share circuit may be used as one of methods for reducing power consumption of the liquid crystal display, and the charge share circuit may be used even in a 2-dot inversion driving method having a large power consumption.

4 shows a circuit diagram relating to a charge share circuit.

Referring to FIG. 4, the charge share circuit includes a plurality of first switching devices SW1 connected between the output buffer and the data lines D1 to Dn, and a plurality of connected between the data lines D1 to Dn. A second switching device SW2. The charge share circuit supplies a voltage between the positive video signal and the negative video signal to control the voltage supplied to the data lines D1 to Dn so that the voltage fluctuation range of the data lines D1 to Dn is not large. In other words, the charge share circuit minimizes the voltage fluctuation of the data lines D1 to Dn to reduce power consumption.

5 shows an operation waveform diagram of the charge share circuit.

The operation of the charge share circuit will be described in detail with reference to FIG. 5. First, the charge share circuit turns on the first switching device SW1 in a low section (a section in which a video signal is supplied) of the source output signal SOE. Let's do it. When the first switching device SW1 is turned on, a positive video signal is supplied from the output buffer to the data lines D1 to Dn to display a predetermined image corresponding to the video signal on the liquid crystal panel 1. The charge share circuit turns on the second switching device SW2 in the high section of the source output signal SOE (a period in which no video signal is supplied). When the second switching device SW2 is turned on, all the data lines D1 to Dn are electrically connected to each other. In this case, the average value of the positive video signal supplied to the row section of the previous source output signal SOE appears in the data lines D1 to Dn. Thus, voltages are induced between the data lines D1 to Dn between the positive and negative video signals. Thereafter, when the source output signal SOE is inverted low, the first switching device SW1 is turned on and the second switching device SW2 is turned off. When the first switching device SW1 is turned on, a negative video signal is supplied to the data lines D1 to Dn to display a predetermined image on the liquid crystal panel 1. At this time, since the voltage is induced between the positive and negative video signals in the data lines D1 to Dn, the voltage fluctuation level can be minimized, thereby reducing power consumption. After the image is displayed on the liquid crystal panel 1, the source output signal SOE is inverted high. When the source output signal SOE is inverted high, the first switching device SW1 is turned off and the second switching device SW2 is turned on. When the second switching device SW2 is turned on, the average value of the negative video signal supplied in the previous horizontal period (low section of the SOE) appears in the data lines D1 to Dn. Accordingly, the voltage between the positive and negative video signals is induced in the data lines D1 to Dn. That is, the charge share circuit corresponds to the source output signal SOE to control the turn-on and turn-off of the first switching element SW1 and the second switching element SW2 while reducing power consumption. However, although the charge share circuit is operated, power consumption can be reduced, but even / even defects, which are poor image quality, may appear visually in a specific pattern. In this case, image quality defects can be eliminated by disabling the charge share circuit, but power consumption is increased.

As another method of reducing power consumption, power consumption can be reduced by lowering the corresponding gradation value to the minimum value within the unknown gradation range within the gradation range (human gradation range) that is not recognized by the human among the gradations of the input data. .

Experimental data of Table 1 and Figure 6 below shows the experimental data of Table 1 in a graph.

Referring to Table 1 and FIG. 6 below, for example, a human-recognized area is evaluated when white gray modulation is performed based on a 27 inch full high definition. In Table 1 below, three experiments were conducted on five evaluators. The average of the areas where each evaluator could not detect the luminance change was 242, 241, 238, 245, and 245, respectively, and the average was 242. Table 1 below shows that on average, when there is a modulation of the white tone in the 242 to 255 gradation region, an undetected region that does not recognize the modulation appears. However, the non-sensing area may vary depending on the resolution of the liquid crystal display, and thus is not limited thereto.

division Undetected Area Gray 1 time Episode 2 3rd time Average Evaluator 1 239 243 244 242 Evaluator 2 240 241 241 241 Evaluator 3 244 244 245 238 Evaluator 4 239 238 236 245 Evaluator 5 245 246 245 245 Average 242

7 is a block diagram of a gray scale modulation unit.

Referring to FIG. 7, video data RGB is input to a gray value calculator 7, and the gray value calculator 7 calculates a gray value of the input video data RGB to the modulation unit 8. Output The gray level of the video data RGB input from the modulator 8 is modulated to a gray level corresponding to a minimum value within a region where the gray level modulation is not recognized by human vision, that is, an unrecognized range, to the image alignment unit 9. Export. The video data R'G'B 'modulated by the image aligning unit 9 is aligned and output to the data driver 2.

When the image aligning unit 9 lowers the gray level of the input video data RGB and outputs the modulated data R'G'B 'to the data driver 2, the digital-to-analog converter DAC in the data driver 2 is output. The data R'G'B 'modulated by the data is converted into an analog voltage and applied to the pixel electrode (not shown) through the data lines D1 to Dn. As a result, the gray level of the input data RGB is lowered, so that the value of the analog voltage converted by the converter is also lowered, thereby reducing power consumption.

Table 2 below shows the experiments on the reduction of power consumption and the reduction of power consumption during white gray level modulation when the LCD panel is driven by the column inversion method using the power control function and the charge share function according to each pattern. .

Referring to Table 2 below, the power control function, charge share function, column inversion, white gradation modulation function do not work, and the power consumption, power control function, charge share function, column inversion, and white color in the LCD. The case where each of the gradation modulation functions is operated is compared in terms of power consumption.

4.6% in the white pattern, 3.3% in the black pattern, 4.0% in the mosaic pattern when applying the power control function 3.9% in the pattern where white and black data are alternately displayed in one image (hereinafter referred to as H1 by 1 pattern) Effect. When the charge share function is applied, the power saving effect is 1.3% in the white pattern, 11.9% in the black pattern, 7.4% in the mosaic pattern, and 7.4% in the H1 by 1 pattern. When the column inversion is applied, the power reduction effect is 1.3% in the white pattern, 14.3% in the black pattern, 8.7% in the mosaic pattern, and 7.4% in the H1 by 1 pattern.

On the other hand, when the charge share function and the column inversion function are applied at the same time, the power consumption is increased by 1.7% in the white pattern, 10.6% in the black pattern, 7.1% in the mosaic pattern, and in the H1 by 1 pattern. In addition, when the power control function, charge share function and column inversion are applied simultaneously, power consumption increases by 30-3.9 = 26.1%. However, the use of charge share, column inversion, and white gradation modulation in the H1 by 1 pattern results in a 10% power reduction, and the addition of power control adds 10 + 3.9 = 13.9%. It can be seen that.

As described above, when the power control circuit and the charge share circuit are used, and the column inversion driving method is used, power consumption may be reduced, but a poor image quality may occur in a specific pattern. Therefore, it is necessary to control the operation of the power control circuit and the charge share circuit and change the inversion driving method according to the attributes of the image.

On the other hand, even in grayscale modulation of input video data, the gray scale modulation value needs to be changed by the gray scale modulation unit because the recognition range according to the gray scale modulation may vary according to the property and the resolution of the image.

Referring to FIG. 8, the power control unit 5 in the timing control path includes a power control signal generation unit 51, a charge share signal generation unit 52, an inversion control signal generation unit 53, and a gray scale modulation unit 54. It may include. The storage unit 6 may be included in the timing controller or disposed outside the timing controller.

The storage unit 6 may store information about a range in which image quality defects occur in an image and an amount of defective pixels. The information can be obtained from the measured data.

First, when the data driver 2 operates in the low power driving method by the power control circuit 21, the displayed image is analyzed to determine the defect generation range and the defective pixel allowance. In addition, when the charge share circuit 22 operates, the displayed image is analyzed to determine a defective generation range and a defective pixel allowance. When the data driver 2 operates in the column inversion method, the displayed image is analyzed to determine a defective generation range and an unacceptable pixel allowance. For example, when the data driver 2 operates in the low power driving method by the power control circuit 21, as a result of analyzing the displayed image, the defective generation range corresponds to 15 gray to 40 gray, and the defective pixel allowance is 1000 pixels ( pixel) and stores the defective generation range and the defective pixel allowable amount in the storage unit 6. In this case, the storage unit 6 may be a nonvolatile memory (EEPROM), but is not limited thereto.

In addition, when the charge share circuit 22 operates, the displayed image is analyzed, and as a result, a defective generation range corresponds to 15 gray to 35 gray, and the allowable amount of defective pixels is determined to be 1200 pixels. Save it. In the case of the column inversion method, the displayed image is analyzed and the defective generation range corresponds to 15 gray to 35 gray, and the allowable amount of the defective pixel is 900 pixels, and stored in the storage unit 6.

The power controller 5 analyzes an image of the input video data RGB and calculates the number of defective pixels of the input video data RGB within a range of generating a defective pixel stored in the storage 6. And comparing the calculated result with the allowable number of defective pixels stored in the storage unit 6 and controlling a result according to whether the number of defective pixels included in the input video data RGB exceeds the allowable pixel stored in the storage unit 6. The signal is output to the data driver 2. For example, referring to the power control signal generator 51 in the power control unit 5, if the input video data RGB has a bad number of pixels exceeding 1000 pixels within a range of 15 gray to 40 gray, the data driver ( 2) operates in a normal driving method, and when the number of defective pixels included in the input video data RGB is less than 1000 pixels, a first control signal for operating the data driver 2 in a low power driving method is used. Output to the power control circuit 21 of 2).

Referring to the charge share control signal generation unit 52, if the input video data RGB has a bad number of pixels exceeding 1200 pixels within a range of 15 gray to 35 gray, the charge share circuit 22 is not operated. When the number of defective pixels included in the input video data RGB is less than 1000 pixels, the second control signal for causing the charge share circuit 22 to operate is output to the charge share circuit 22 of the data driver 2.

Referring to the inversion control signal generator 53, when the input video data RGB has a bad number of pixels exceeding 900 pixels within a range of 15 gray to 35 gray, the data driver 2 is a 2-dot inversion driving method. When the number of defective pixels included in the input video data RGB is less than 900 pixels, the third driver outputs a third control signal to the data driver, which causes the data driver 2 to operate in the column inversion driving method. The third control signal may be a polarity control signal POL.

On the other hand, the unrecognized range according to the gradation modulation is measured from the measured data according to the property and the resolution of the image, and the information about this is stored in the storage unit 6. For example, in the case of white gradation, when the unrecognized gradation range corresponds to 242 to 255 gradations, information about the gray scale is stored in the storage unit 6, and the gradation modulator 54 gradations of the input video data RGB. The modulated data (R'G'B ') is modulated by modulating the data value of white gradation corresponding to 242 to 255 gradations to 242 gradation, which is the minimum value within the unknown region range stored in the storage unit 6. Output to the driver (2). Therefore, the power consumption can be reduced by lowering the gray level value of the input video data RGB to a minimum value within a range in which a human is initially notified.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1.LCD panel
2. Data driver
3.gate driver
4. Timing controller
5.Power control section
6.storage department
7.Gradation value calculation section
8. Modulation department
9. Image modulation section
21. Power Control Circuit
22. Charge Share Circuit
51. Power control signal generator
52. Charge share control signal generator
53. Inversion control signal generator
54. Gradation Modulation Unit

Claims (2)

A liquid crystal panel;
A data driver for applying a data signal to the liquid crystal panel;
A gate driver for applying a gate signal to the liquid crystal panel;
A timing controller controlling the data driver and the gate driver and including a power control unit;
A gray scale modulation unit included in the power control unit; And
A storage unit storing an information signal including an unknown gray level area for supplying to the gray level modulation unit,
The gradation modulator determines whether the gradation of each pixel of the video data is included in the unknown gradation region, and modulates the gradation of the pixel according to the result.
And the modulated pixel is applied to the data driver as the data signal. The method of claim 1,
And when the gray level of the pixel is included in the unknown gray area, the gray level of the pixel is modulated to the lowest gray level value of the unknown gray area.

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