KR20110058353A - Photo mask, method of manufacturing the same and method of fabricating array substrate for liquid crystal display device using the same - Google Patents

Abstract

PURPOSE: A photo mask, manufacturing method thereof, and manufacturing method of an array substrate for a liquid crystal display device using the same are provided to form a gate line using a photo mask, thereby preventing the blurring of the screen of the liquid crystal display device. CONSTITUTION: A photo mask(110) includes a first side(110a) in parallel with a first direction and a second side(110b) shorter than the first side. An electron beam(120) scans and exposes the photo mask in the first direction to record pattern data in a photo resist layer of the photo mask. mth to (m+3)th gate lines are separated on a first substrate(130). A data line crosses the mth to (m+3)th gate lines to define first to fourth pixel areas. A gate insulating film is placed on a gate electrode so that a semiconductor layer is formed.

Description

Photomask, its manufacturing method and manufacturing method of array substrate for liquid crystal display device using the same {PHOTO MASK

The present invention relates to a method for fabricating a photomask, and more particularly, to a photomask having a compensation for a line width variation according to a writing direction of a pattern data, and an array for a liquid crystal display device using the photomask manufacturing method and an improved image quality. It relates to a manufacturing method.

In general, a semiconductor device such as a liquid crystal display device is manufactured through a photolithography process.

The photolithography process is performed by first designing a pattern constituting a semiconductor device, and then fabricating a photomask in which a mask pattern corresponding to the designed pattern is formed on a transparent quartz substrate. .

That is, by exposing and developing a photoresist layer formed on the substrate through a photomask using an exposure apparatus, a photoresist pattern corresponding to the designed pattern is formed on the substrate.

Then, a thin film pattern is formed on the substrate through a selective etching process for the thin film under the photoresist pattern.

In general, an electron beam exposure apparatus (e-beam exposure) is used to form the designed pattern into a mask pattern in manufacturing such a photomask.

That is, a metal layer is formed of chromium (Cr) or molybdenum alloy (Mo alloy) on the quartz substrate, a photoresist layer is formed on the metal layer, and then the photoresist layer is selectively selected by an electron beam using an electron beam exposure apparatus. Exposure is performed.

Thereafter, the exposed photoresist layer is developed to form a photoresist pattern, the metal layer under the photoresist pattern is etched, and then the photoresist pattern is removed to form a mask pattern to complete the photomask.

The manufacturing method of such a photomask is demonstrated with reference to drawings.

FIG. 1 is a view for explaining a conventional method of manufacturing a photomask, and FIG. 2 is an enlarged view of a portion A of FIG. 1 and corresponds to a portion of a gate wiring photomask of a liquid crystal display device.

The photomask 10 of FIG. 1 and FIG. 2 is a gate wiring GLm and GLm of the array substrate 30 of each liquid crystal panel in the manufacturing process of the liquid crystal display which forms many liquid crystal panels on one glass substrate. +1, GLm + 2, and GLm + 3).

In addition, the array substrate 30 and the gate wirings GLm, GLm + 1, GLm + 2, and GLm + 3, etc., displayed on the photomask 10 are names of patterns formed on the glass substrate using the photomask 10. However, since the mask pattern formed on the photomask 10 is projected as it is, patterns such as the array substrate 30 and the gate wiring lines GLm, GLm + 1, GLm + 2, and GLm + 3 are formed. The patterns of the substrate 30 and the gate wirings GLm, GLm + 1, GLm + 2, GLm + 3 and the like may be regarded as having the same shape, and thus will be described using the same names for convenience.

1 and 2, in order to form the photomask 10, a metal layer is formed on the quartz substrate, a photoresist layer (not shown) is formed on the metal layer, and then the photoresist layer is formed by electrons. The beam 20 is selectively exposed.

At this time, the electron beam 20 scans and exposes the photomask 10 in the left and right directions so that the pattern data is written in the photoresist layer of the photomask 10, but the write pitch wp of the electron beam 20 is finite. After scanning exposure in the left and right directions, move a predetermined interval in the vertical direction and scan exposure in the left and right directions again to write the pattern data.

Specifically, the electron beam 20 scans a circular or square beam in the vertical direction and exposes an area corresponding to the distance d between adjacent gate lines, wherein the area exposed by the vertical scan of the electron beam is exposed. The write pitch wp of the electron beam is defined as a distance d between adjacent gate lines. (wp = d)

While moving the electron beam 20 in the first direction X1 parallel to the m-th gate line GLm, the exposure of the area corresponding to the writing pitch wp is progressed to correspond to the m-th gate line GLm. Complete the scan exposure for the heat.

After the exposure to the horizontal column corresponding to the mth gate line GLm is completed, the electron beam 20 moves downward by the write pitch wp, and after the downward movement, is opposite to the first direction X1 and the gate line ( By exposing the area corresponding to the write pitch wp while moving in the second direction X2 parallel to GLm, GLm + 1, GLm + 2, GLm + 3, the (m + 1) gate wiring ( Scan exposure is performed on the horizontal column corresponding to GLm + 1).

Thereafter, the scan exposure of the horizontal columns corresponding to the (m + 2) and (m + 3) th gate lines GLm + 2 and GLm + 3 is performed in a similar manner.

In this manner, the entire photomask 10 is scanned to complete exposure for forming a mask pattern of the photomask 10.

However, when the mask pattern is formed, a variation occurs in the line width of the mask pattern, that is, the gate wiring, depending on the writing direction of the electron beam 20 due to the inherent characteristics of the electron beam exposure apparatus.

That is, the m-th and m-th gate lines GLm and GLm + 2 formed by exposing the electron beam 20 in the first direction X1 have a first line width w1, whereas the electron beam 20 has a first line width w1. (M + 1) and (m + 3) -th gate lines GLm + 1 and GLm + 3 formed by exposing (20) in the second direction X2 are different from the first line width w1. It has a line width w2.

For example, the second line width w2 is greater than the first line width w1, and the difference w2-w1 between the first and second line widths w1 and w2 may be about 0.2 μm to about 0.6 μm.

The line width deviation of the gate wiring along the writing direction of the electron beam 20 causes poor image quality of the liquid crystal display, which will be described with reference to the drawings.

FIG. 3 is an equivalent circuit diagram of one pixel region of a conventional liquid crystal display, and FIG. 4 is a waveform diagram showing a gate signal and a voltage of a pixel electrode of the conventional liquid crystal display. Waveform diagram for the frame.

3 and 4, gate wirings and data wirings GL and DL are formed on the array substrate of the liquid crystal display device to intersect each other and define pixel regions P. In each pixel region P, The thin film transistor T is connected to the gate line and the data lines GL and DL, and the storage capacitor Cst and the liquid crystal capacitor Clc are connected to the thin film transistor T.

The liquid crystal capacitor Clc is configured of a pixel electrode (not shown), a liquid crystal layer, and a common electrode connected to the thin film transistor T, and serves to display a gray level corresponding to a data signal applied to the pixel electrode, and the storage capacitor (Cst) serves to keep the voltage of the pixel electrode constant by storing the data signal for one frame.

When the thin film transistor T is turned on by the gate signal Vg applied to the gate line GL, a data signal supplied to the data line DL is applied to the pixel electrode to form a pixel electrode. The voltage, that is, the pixel voltage Vp, is changed as shown in FIG. 4.

Here, in order to prevent light leakage between the gate line GL and the pixel electrode, the pixel electrode is formed to overlap the gate line GL. The overlapping portion of the gate line GL and the pixel electrode forms a parasitic capacitance Cgd. do.

Therefore, the storage capacitor Cst, the liquid crystal capacitor Clc, and the parasitic capacitance Cgd are connected in parallel to the connection node B of the thin film transistor T, the storage capacitor Cst, and the liquid crystal capacitor Clc.

At the end of the pulse of the gate signal Vg, the charges of the capacitors connected to the connection node B are redistributed by the gate signal variation ΔVg, and the pixel voltage Vp is rapidly reduced accordingly. (ΔVp) is also called kickback voltage.

The pixel voltage variation amount ΔVp is determined by the following equation.

ΔVp = (Cgd / (Cst + Clc + Cgd)) * ΔVg

According to the above equation, the pixel voltage variation ΔVp depends on the size of the parasitic capacitance Cgd. The magnitude of the parasitic capacitance is proportional to the area of the overlapping portion of the gate wiring GL and the pixel electrode, and thus the pixel voltage variation ΔVp. Depends on the area of the overlapping portion of the gate wiring GL and the pixel electrode.

In other words, when the area of the overlapping portion of the gate wiring GL and the pixel electrode becomes smaller, the pixel voltage variation ΔVp decreases, and when the area of the overlapping portion of the gate wiring GL and the pixel electrode becomes large, the pixel voltage variation ΔVp increases.

1 and 2, when the photomask 10 is manufactured, when the line width of the gate wiring GL is differently formed according to the moving directions X1 and X2 of the electron beam 20, the gate wiring ( The area of the overlapping portion between the GL and the pixel electrode varies depending on the moving directions X1 and X2 of the electron beam 20, and as a result, the pixel voltage variation amount ΔVp is also the moving direction X1 and X2 of the electron beam 20. Depends on.

That is, the area of the overlapping portion of each of the m-th and m-th gate lines GLm and GLm + 2 having the first line width w1 and the pixel electrode has a second width larger than the first width w1. each of the (m + 1) and (m + 3) -th gate lines GLm + 1 and GLm + 3 having w2 and the overlapping area of the pixel electrode is smaller than the m < th > The pixel voltage variation ΔVp of each of the gate lines GLm and GLm + 2 is the pixel voltage variation ΔVp of each of the (m + 1) and (m + 3) -th gate lines GLm + 1 and GLm + 3. Is less than

The variation in the pixel voltage variation due to the line width variation of the gate line GL causes deterioration in image quality of the liquid crystal display device driven by line inversion and frame inversion. This will be described with reference to the drawings.

5A and 5B illustrate polarities and gray levels of some pixel regions in a s-frame and a (s + 1) frame of a conventional LCD for displaying an image of an intermediate gray scale, respectively. FIG. The pixel voltages of the first and second pixel areas of the conventional liquid crystal display for displaying an image are shown.

5A, 5B, and 6, in the liquid crystal display device driven by frame inversion and line inversion, the m-th and (m + 2) gate lines GLm and GLm + 2 are connected during the s-frame. A positive data signal is applied to the pixel areas including the connected first pixel area P1 and the (m + 1) and (m + 3) gate lines GLm + 1 and GLm + 3. A negative data signal is applied to the pixel areas including the second pixel area P2 connected to the second pixel area P2.

In addition, in the pixel regions including the first pixel region P1 connected to the m-th and (m + 2) th gate lines GLm and GLm + 2 during the (s + 1) th frame, negative polarity (−) may be achieved. Positive polarity (+) in the pixel areas including the second pixel area P2 to which the data signal of the second signal is applied and connected to the (m + 1) th and (m + 3) th gate lines GLm + 1 and GLm + 3. ) Is applied.

When the data signal is applied to the pixel electrode, the pixel voltage fluctuation amount ΔVp due to the parasitic capacitance Cgd described above is reduced and maintained for one frame. Design the voltage of

By the way, since the line width of the gate wiring varies depending on the pattern data writing direction in the photomask, a variation occurs in the pixel voltage variation amount ΔVp depending on the position of the gate wiring, which causes a variation in the final pixel voltage.

For example, the m-th and (m + 1) -th gate lines GLm and GLm + 1 corresponding to the first and second pixel regions P1 and P2 are respectively disposed in the first and second directions (X1 in FIG. 2). 6, the first pixel voltage variation amount ΔVp1 of the first pixel region P1 and the second pixel voltage variation amount ΔVp2 of the second pixel region P2, as shown in FIG. Has a difference D. (D = ΔVp2-ΔVp1)

Therefore, in the s-th frame, the first pixel region P1 displays the 127th grayscale of the positive polarity (+) and the second pixel region P2 displays the 126th grayscale of the negative polarity (−), whereas the first pixel region P1 displays the 127th grayscale. In the (s + 1) frame, the first pixel region P1 displays the 127th grayscale of negative polarity (-) and the second pixel region P2 displays the 128th grayscale of positive polarity (+).

Therefore, the average gradation displayed by all pixel regions in the s-th frame is 126.5 gradations, and the average gradation represented by all pixel regions in the (s + 1) -th frame is 127.5 gradations.

That is, when the liquid crystal display displays an image gray of an intermediate gray level like the 127th gray level, an average gray value vibrates for each frame, and such an average gray level vibration is caused by a defect such as screen shaking in the image display. Appears, deteriorating the image quality of the liquid crystal display device.

The present invention is to solve the above problems, in the manufacturing method of the photomask for the liquid crystal display device driven by the frame inversion and line inversion, it is produced so that the write pitch of the electron beam is an even multiple of the distance between the gate wirings. By forming the gate wiring as a photomask, an object of the present invention is to prevent screen shaking and improve image quality of the liquid crystal display.

Further, in the method of manufacturing a photomask for a liquid crystal display device driven by frame inversion and line inversion, the screen blur of the liquid crystal display device is formed by forming a gate wiring with a photomask manufactured so that the writing direction of the electron beam is perpendicular to the gate wiring. It aims to prevent the phenomenon and to improve the image quality.

In order to achieve the above object, the present invention provides a photomask for forming an m-th to (m + 3) gate wiring of a liquid crystal display device, comprising: a quartz substrate; A mask pattern formed on the quartz substrate and having a first line width and spaced apart from each other in parallel to each other to correspond to the mth and (m + 1) th gate lines; A second line width formed on the quartz substrate and adjacent to a mask pattern corresponding to the mth and (m + 1) th gate lines, and having a second line width different from the first line width, and spaced apart from each other in parallel. A photo mask including a mask pattern corresponding to (m + 2) and (m + 3) -th gate wirings is provided.

Here, the first width may be designed to be smaller than the second width.

Meanwhile, the present invention provides a method of manufacturing a photomask for forming m-th to (m + 3) gate wirings of a liquid crystal display device, the method comprising: sequentially forming a metal layer and a photoresist layer on a quartz substrate; While moving an electron beam having a write pitch that is twice the distance between two adjacent ones of the m-th to m + 3 gate lines in a first direction parallel to the m-th to m + 3 gate lines, Exposing the photoresist layer; Moving the electron beam by the write pitch in a direction perpendicular to the first direction; And exposing the photoresist layer while moving the electron beam in a second direction opposite to the first direction.

The exposing the photoresist while moving the electron beam in the first direction is exposing a portion of the photoresist corresponding to the mth and (m + 1) th gate lines, and the electron beam The exposing the photoresist while moving in the second direction may be exposing a portion of the photoresist corresponding to the (m + 2) and (m + 3) gate lines.

On the other hand, the present invention, the substrate; M-th to (m + 3) gate lines formed on the substrate and spaced apart from each other in parallel; Data lines defining first to fourth pixel regions intersecting the m-th to m-th gate lines; A gate electrode connected to each of the mth to (m + 3) th gate lines; A semiconductor layer formed on the gate electrode; Source and drain electrodes spaced apart from each other on the semiconductor layer; And a pixel electrode connected to the drain electrode and overlapping each of the m th to m th gate gate lines, wherein the m th and m th gate gate lines have a first line width. The m + 2) and (m + 3) gate wirings provide an array substrate for a liquid crystal display device having a second line width different from the first line width.

Here, the first width may be designed to be smaller than the second width.

During the s-frame, a positive data signal is applied to the pixel electrodes of each of the first and third pixel regions, and a negative polarity is applied to the pixel electrodes of each of the second and fourth pixel regions. Data signal of-) is applied, and a negative data signal is applied to the pixel electrode of each of the first and third pixel regions during the (s + 1) frame, and the second and fourth A positive data signal may be applied to the pixel electrode of each pixel area.

In addition, the data signal may be a signal corresponding to an image of halftone.

On the other hand, the present invention, the step of forming a m-th (m + 3) gate wiring and a gate electrode connected to each of the m-th (m + 3) gate wiring spaced parallel to each other on the upper substrate A mask pattern having a first line width and spaced in parallel to each other to correspond to the m-th and (m + 1) -th gate lines, and a mask pattern corresponding to the m-th and (m + 1) -th gate lines. A photomask having a second line width different from the first line width and spaced in parallel to each other, the photo mask including a mask pattern corresponding to the (m + 2) and (m + 3) gate lines; Forming m-th to (m + 3) gate lines; Forming data lines defining first to fourth pixel regions intersecting the m-th to m-th gate lines; Forming a semiconductor layer on the gate electrode; Forming source and drain electrodes spaced apart from each other on the semiconductor layer; A method of manufacturing an array substrate for a liquid crystal display device, the method comprising: forming a pixel electrode connected to the drain electrode and overlapping each of the m-th to m-th gate lines.

The m-th and (m + 1) -th gate lines may have the first line width, and the (m + 2) -th and (m + 3) -th gate lines may have the second line width.

On the other hand, the present invention, in the method for manufacturing a photomask for forming the m-th (m + 3) gate wiring of the liquid crystal display device, the step of sequentially forming a metal layer and a photoresist layer on the quartz substrate Wow; While moving the electron beam having a write pitch corresponding to the distance between two adjacent ones of the m-th (m + 3) gate lines in a first direction perpendicular to the m-th (m + 3) gate lines Exposing the photoresist layer; Moving the electron beam by the write pitch in a direction perpendicular to the first direction; And exposing the photoresist layer while moving the electron beam in a second direction opposite to the first direction.

Here, the photomask has a long side in the form of a rectangle parallel to the first direction, the mask pattern region corresponding to the array substrate for a plurality of liquid crystal display device is disposed on the photomask, the array for the plurality of liquid crystal display device Each of the substrates may be in the form of a rectangle whose short sides are parallel to the first direction.

As described above, in the manufacturing method of the liquid crystal display device using the photomask according to the present invention, the gate wiring is formed by using the photomask fabricated so that the write pitch of the electron beam is an even multiple of the distance between the gate wirings. By maintaining the same frame-by-frame average gradation of the frame inversion and line inversion driving, screen shaking of the LCD is prevented and image quality is improved.

In addition, the gate wiring is formed using a photomask fabricated so that the writing direction of the electron beam is perpendicular to the gate wiring, so that the screen shake phenomenon of the liquid crystal display device is maintained by maintaining the same average gray level of each frame in the frame inversion and line inversion driving. It is prevented and the image quality is improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 7 is a diagram for describing a method of fabricating a photomask according to the first embodiment of the present invention. FIG. 8 is an enlarged view of a portion C of FIG. 7 and corresponds to a part of a photomask for a gate wiring. 7 is a plan view of a part of an array substrate for a liquid crystal display device manufactured by using the photomask of FIG.

The photomask 110 of FIGS. 7 and 8 corresponds to one mother substrate on which a plurality of liquid crystal panels are disposed, which is an array substrate of each liquid crystal panel in the manufacturing process of the liquid crystal display device. The m-th to m-th gate lines GLm, GLm + 1, GLm + 2 and GLm + 3 are spaced apart from each other in parallel on the substrate 130.

In addition, the first substrate 130 and the gate wiring lines GLm, GLm + 1, GLm + 2, and GLm + 3, which are displayed on the photomask 110 of FIGS. 7 and 8, are exposed using the photomask 110. It is the name of the pattern formed on the glass substrate after the photolithography process, but the mask pattern formed on the photomask 110 is projected as it is, so that the first substrate 130 and the gate wiring GLm and GLm + are the same. 1, GLm + 2, GLm + 3), and so on, the mask pattern, the first substrate 130, and the gate wiring patterns GLm, GLm + 1, GLm + 2, and GLm + 3 are the same. It may be considered to be, and for the sake of convenience, the same name will be described.

As shown in FIGS. 7 and 8, in order to form the photomask 110, a metal layer is formed on the quartz substrate, a photoresist layer (not shown) is formed on the metal layer, and then an electron beam exposure apparatus is formed. To selectively expose the photoresist layer.

At this time, the photomask 110 may include a first side 110a parallel to the first direction X1 and a second side 110b perpendicular to the first direction X1 and shorter than the first side 110a. Include.

In the electron beam exposure apparatus loaded with the photomask 110, the electron beam 120 scans and exposes the photomask 110 in the first direction X1 to write pattern data into the photoresist layer of the photomask 110. After scanning exposure in the first direction X1 and moving a predetermined distance in a direction perpendicular to the first direction X1, the pattern is subjected to scan exposure in a second direction X2 opposite to the first direction X1. Write the data.

Specifically, the electron beam 120 scans a circular or square beam in an up and down direction perpendicular to the first and second directions X1 and X2, thereby doubling the distance d between the adjacent gate lines (2d), That is, the area corresponding to the distance 2d between the three gate wires is exposed, so that the write pitch wp of the electron beam defined by the area exposed by the vertical scan of the electron beam is the distance between adjacent gate wires. 2 times (d) of (d). (wp = 2d)

Therefore, a horizontal scan corresponding to the two gate lines is exposed by one scan of the electron beam 120 in the first direction X1 or the second direction X2.

That is, the m-th and (m + 1) -th gate wirings are formed by scanning and exposing the electron beam 120 having the write pitch wp that is twice the distance between the gate wirings along the first direction X1. The scan exposure on the horizontal column corresponding to (GLm, GLm + 1) is completed.

After the exposure to the horizontal column corresponding to the m-th and (m + 1) th gate lines GLm and GLm + 1 is completed, the electron beam 120 is twice the distance between the gate lines having the write pitch wp ( A second beam that is moved downward by 2d) and has an write pitch wp that is twice the distance between the gate lines after the downward movement, in parallel with the first direction X1 and in the opposite direction; By scanning exposure along the direction X2, the scan exposure for the horizontal columns corresponding to the (m + 2) th and (m + 3) th gate lines GLm + 2 and GLm + 3 is completed.

Subsequently, similar scan exposures to horizontal columns corresponding to the (m + 4) and (m + 5) th gate lines (not shown) and the (m + 6) and (m + 7) th gate lines (not shown) are similar. Proceed in a way.

In this manner, the entire photomask 110 is scanned to complete exposure for forming a mask pattern of the photomask 110.

Here, variations in the line width in the vertical direction of the mask pattern, that is, variations in the line width of the gate wiring, occur according to the writing direction of the electron beam 120 due to the inherent characteristics of the electron beam exposure apparatus.

That is, the m-th and m-th gate lines GLm and GLm + 1 formed by exposing the electron beam 120 in the first direction X1 have the first line width w1, whereas the electron beam 120 has the first line width w1. The second (m + 2) and the (m + 3) th gate lines GLm + 2 and GLm + 3 formed by exposing the 120 to the second direction X2 are different from the first line width w1. It has a line width w2.

For example, the second line width w2 is greater than the first line width w1, and the difference w2-w1 between the first and second line widths w1 and w2 may be about 0.2 μm to about 0.6 μm.

Meanwhile, as shown in FIG. 9, the first substrate 130 is formed on the rectangular first substrate 130, which is an array substrate for a liquid crystal display device manufactured by using the photomask 110 to form a gate wiring. The m to (m + 3) gate lines GLm to GLm + 3 parallel to the first side (not shown), which is a long side of, are spaced apart from each other, and the data line DL is formed to the m to (m + 3) gates. The first to fourth pixel regions P1 to P4 are defined to cross the gate lines GLm to GLm + 3.

The gate electrodes 132 are formed in the first to fourth pixel regions P1 to P4, respectively, connected to the m th to m + 3 gate lines GLm to GLm + 3. ), A semiconductor layer 134 is formed through a gate insulating layer (not shown).

A source electrode 136 connected to the data line DL and a drain electrode 138 spaced apart from the source electrode 136 are formed on the semiconductor layer 134.

Here, the gate electrode 132, the semiconductor layer 134, the source electrode 136, and the drain electrode 138 constitute a thin film transistor T.

In addition, a pixel electrode 140 connected to the drain electrode 138 is formed in each of the pixel areas P1 to P4 through a protective layer (not shown) on the drain electrode 138.

In addition, the pixel electrode 140 overlaps each of the mth to (m + 3) gate lines GLm to GLm + 3 to form parasitic capacitances Cgd1 and Cgd3.

The m-th to (m + 3) gate lines GLm to GLm + 3 and the gate electrode 132 are formed using the photomask 110, and the writing direction of the electron beam 120 when the photomask 110 is manufactured. As a result, variations in the line widths of the gate wirings occur, and variations in the capacitance of the parasitic capacitances Cgd1 and Cgd3 also occur due to such variations in the line widths of the gate wirings.

That is, the m-th and m-th gate lines GLm and GLm + 1 formed by moving the electron beam 120 along the first direction X1 have a first line width w1 and the electron beam (M + 2) and (m + 3) -th gate lines GLm + 2 and GLm + 3, which are formed by moving 120 along the second direction X2, are larger than the first line width w1. It has two line widths w2, and as a result, the first overlap width ow1 of the overlapping region of the gate lines GLm and GLm + 1 and the pixel electrode 140 of each of the first and second pixel regions P1 and P2. Is smaller than the second overlap width ow2 of the overlapping regions of the gate lines GLm + 2 and GLm + 4 and the pixel electrode 140 of each of the third and fourth pixel regions P3 and P4.

Therefore, the first parasitic capacitance Cgd1 of the overlapping region having the first overlapping width ow1 of each of the first and second pixel regions P1 and P2 is each of the third and fourth pixel regions P3 and P4. The first and second pixel voltages of the first and second pixel areas P1 and P2 are smaller than the second parasitic capacitance Cgd2 of the overlapping region having a second overlapping width ow2 of Each of the variation amounts ΔVp1 and ΔVp2 is smaller than each of the third and fourth pixel voltage variation amounts ΔVp3 and ΔVp4 of the third and fourth pixel areas P3 and P4.

In the present invention, the deviation of the pixel voltage fluctuation amount is compensated by a pair of adjacent gate wirings having the same line width and another pair of gate wirings having a different line width adjacent to the pair of gate wirings. It will be described with reference to.

10A and 10B illustrate polarities and gray levels of some pixel regions in the s-frame and the (s + 1) -frame of the liquid crystal display according to the first exemplary embodiment of the present invention, respectively. 10A, 10B and 11 illustrate pixel voltages of the third and fourth pixel regions of the liquid crystal display according to the first embodiment of the present invention. The case where the image of Joe is displayed is shown.

As shown in Figs. 10A, 10B and 11, in the liquid crystal display device driven by frame inversion and line inversion, the m-th and (m + 2) gate lines GLm and GLm + 2 are connected during the s-frame. Positive data signals are applied to the connected first and third pixel regions P1 and P3, respectively, and the (m + 1) and (m + 3) gate lines GLm + 1 and GLm + 3 are respectively applied. The negative and negative data signals are applied to the second and fourth pixel areas P2 and P4 connected to the P1 and P4 regions.

In the (s + 1) th frame, the first and third pixel regions P1 and P3 connected to the mth and (m + 2) th gate lines GLm and GLm + 2 are respectively provided with a negative polarity (−). The data signal is applied to the second and fourth pixel areas P2 and P4 connected to the (m + 1) and (m + 3) -th gate lines GLm + 1 and GLm + 3, respectively, to have a positive polarity (+). The data signal is applied.

The data signal applied to the pixel electrode is reduced by the storage voltage Cst, the liquid crystal capacitor Clc, and the parasitic capacitance Cgd of each pixel region P1 to P4 by the amount of change in the pixel voltage ΔVp and maintained for one frame. Therefore, when designing the liquid crystal display, the voltage of the data signal is designed in consideration of the pixel voltage variation ΔVp.

Here, the photomask (110 in FIGS. 7 and 8) used to form the gate wirings has an electron beam (120 in FIGS. 7 and 8) having a write pitch (wp = 2d) corresponding to the distance between the double gate wirings. And the first and second pixel regions P1 and P2 have the same first parasitic capacitance Cgd1 in FIG. 9, and the third and fourth pixel regions P3 and P4 have the same second parasitic It has a capacity (Cgd2 in Fig. 9) and the second parasitic capacity (Cgd2) is larger than the first parasitic capacity (Cgd1).

Accordingly, the first and second pixel voltage variations in the first and second pixel regions P1 and P2 are the same, and the third and fourth pixel voltage variations in the third and fourth pixel regions P3 and P4 ( ΔVp3 and ΔVp4 are the same (D = ΔVp3-ΔVp4 = 0), and the third and fourth pixel voltage fluctuations ΔVp3 and ΔVp4 are larger than the first and second pixel voltage fluctuations.

Therefore, in the s-th frame, the first pixel area P1 displays the 127th gray level of the positive polarity (+), and the second pixel area P2 displays the 127th grayscale of the negative polarity (−) and the third pixel. The region P3 displays the 128th gradation of positive polarity (+) and the fourth pixel region P4 displays the 126th gradation of negative polarity (−), whereas in the (s + 1) th frame, the first The pixel region P1 displays the 127th grayscale of negative polarity (-), the second pixel region P2 displays the 127th grayscale of positive polarity (+), and the third pixel region P3 represents the negative polarity (−). ) 126th gradation and the fourth pixel area P4 displays the 128th gradation of positive polarity (+).

Therefore, the average gradation indicated by the entire pixel region in the s-th frame and the average gradation indicated by the entire pixel region in the (s + 1) th frame are the same as the 127th gradation, respectively.

That is, when the liquid crystal display displays an image gray of the same gray level as the 127th gray level, in each frame, the first and second pixel areas P1 and P2 display the 127th gray level and the third and fourth pixels. The areas P3 and P4 display the 126th or 128th gradations different from the 127th gradations, respectively, but the average gradation of the third and fourth pixel areas P3 and P4 is always the 127th gradation, so that each frame The average gradation of all the pixel areas in is always the 127th gradation.

Therefore, in the liquid crystal display device according to the first embodiment of the present invention, the average gray level value is always the same for each frame, thereby preventing defects such as screen shaking due to gray scale vibration and improving image quality of the liquid crystal display device. .

On the other hand, in the present invention, by setting the writing direction of the electron beam in the direction perpendicular to the gate wiring when fabricating the photomask used for forming the gate wiring, the average gradation of each frame of the liquid crystal display device is eliminated while the line width deviation of the gate wiring is excluded. The same may be maintained, which will be described with reference to the drawings.

12 is a view for explaining a method of manufacturing a photomask according to a second embodiment of the present invention, and FIG. 13 is an enlarged view of part E of FIG. 12 and corresponds to a part of a photomask for a gate wiring.

The photomask 210 of FIGS. 12 and 13 corresponds to one mother substrate on which a plurality of liquid crystal panels are disposed, which is an array substrate of each liquid crystal panel in the manufacturing process of the liquid crystal display device. The gate wirings GLm, GLm + 1, and GLm + 2 are formed in the substrate 230.

12 and 13, the first substrate 230 and the gate lines GLm, GLm + 1, and GLm + 2 shown in the photomask 210 may be exposed by photolithography using the photomask 210. Although the name of the pattern is formed on the glass substrate after the process, the mask pattern formed on the photomask 210 is projected as it is, the first substrate 230 and the gate wiring (GLm, GLm + 1, GLm +) in the same form. 2) and the like, the mask pattern, the first substrate 230 and the gate wiring lines GLm, GLm + 1, and GLm + 2 may be regarded as having the same shape. Explain using

12 and 13, in order to form the photomask 210, a metal layer is formed on the quartz substrate, a photoresist layer (not shown) is formed on the metal layer, and the electron beam exposure apparatus is formed. To selectively expose the photoresist layer.

In this case, the photomask 210 may include a first side 210a parallel to the first direction X1 and a second side 210b perpendicular to the first direction X1 and shorter than the first side 210a. Include.

In the electron beam exposure apparatus loaded with the photomask 210, the electron beam 220 scans and exposes the photomask 210 in the first direction X1 to write pattern data into the photoresist layer of the photomask 210. After scanning exposure in the first direction X1 and moving a predetermined distance in a direction perpendicular to the first direction X1, the pattern is subjected to scan exposure in a second direction X2 opposite to the first direction X1. Write the data.

In this case, the first substrate 230 of each of the plurality of liquid crystal panels has a rectangular shape, and the long side of the first substrate 230 is perpendicular to the first direction X1, and the short side of the first substrate is the first direction X1. Are arranged parallel to).

That is, the m-th to (m + 2) gate lines GLm, GLm + 1, and GLm + 2, which are designed to be parallel to the long side of the first substrate 230, are disposed to be perpendicular to the first direction X1. The electron beam 220 moves vertically to the m-th to (m + 2) th gate lines GLm, GLm + 1, and GLm + 2, thereby scanning and exposing the photoresist.

Since the m-th to (m + 2) th gate lines GLm, GLm + 1, and GLm + 2 are perpendicular to the writing direction, the mth to mth directions in the first direction X1 and the second direction X2 are provided. +2) The line widths of the gate wirings GLm, GLm + 1, and GLm + 2 do not occur, and the mth to m + 2 gate wirings in the first direction X1 and the second direction X2 do not occur. The line widths w of (GLm, GLm + 1, GLm + 2) are all the same.

As a result, the overlapping width of the overlapping region of the gate wiring and the pixel electrode is also the same for all the pixel regions, and the pixel voltage variation of the pixel electrode is also the same for all the pixel regions.

Therefore, when the LCD displays an intermediate gray scale, all pixel areas display the same 127 gray levels in each frame, so that there is no variation in the average gray level for each frame, and a defect such as screen shaking due to gray scale vibration is prevented. And the image quality of the liquid crystal display device is improved.

On the other hand, although not shown in the drawings, the line width deviation of the gate wiring does not occur when the electron beam in the electron beam exposure apparatus moves vertically to the gate wiring so that the first substrate is arranged as shown in FIG. 7. By making the writing direction of the electron beam in the electron beam exposure apparatus in the up-down direction with respect to the used photomask, the line width deviation of the gate wiring can be prevented and defects such as screen shaking can be prevented to improve the image quality of the liquid crystal display device. .

In addition, as shown in FIG. 7, the electron beam exposure apparatus scans and exposes the electron beam along the first direction X1 with respect to the photomask on which the first substrate is disposed, and then moves downward by the writing pitch. When moving to the left side of the photomask at the same time, the scanning exposure can be performed while moving along the first direction X1 in the same horizontal column as well, so that the scanning exposure can be performed while moving the electron beam along the same direction with respect to all the gate wirings. In this case, the line width variation of the gate wiring can be prevented, and defects such as screen shaking can be prevented to improve the image quality of the liquid crystal display.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

1 is a view for explaining a conventional photomask manufacturing method.

2 is an enlarged view of a portion A of FIG. 1.

3 is an equivalent circuit diagram of one pixel area of a conventional liquid crystal display device.

4 is a waveform diagram showing a voltage of a gate signal and a pixel electrode of a conventional liquid crystal display device.

5A and 5B illustrate polarities and gray levels of some pixel regions in a s-frame and a (s + 1) frame of a conventional liquid crystal display for displaying an image of an intermediate gray scale, respectively.

FIG. 6 is a diagram showing pixel voltages of first and second pixel areas of a conventional liquid crystal display for displaying an image of a halftone; FIG.

7 is a view for explaining a photomask manufacturing method according to a first embodiment of the present invention.

8 is an enlarged view of a portion C of FIG. 7.

FIG. 9 is a plan view of a portion of an array substrate for a liquid crystal display device manufactured by using the photomask of FIG. 7 to form a gate wiring; FIG.

10A and 10B illustrate polarities and gray levels of some pixel regions in an s-frame and an (s + 1) frame of the liquid crystal display according to the first exemplary embodiment of the present invention, respectively.

FIG. 11 is a diagram showing pixel voltages of third and fourth pixel areas of a liquid crystal display according to a first embodiment of the present invention; FIG.

12 is a view for explaining a photomask manufacturing method according to a second embodiment of the present invention.

13 is an enlarged view of a portion E of FIG. 12.

Claims (12)

In the photomask for forming the m-th (m + 3) gate wiring of the liquid crystal display device, A quartz substrate; A mask pattern formed on the quartz substrate and having a first line width and spaced apart from each other in parallel to each other to correspond to the mth and (m + 1) th gate lines; A second line width formed on the quartz substrate and adjacent to a mask pattern corresponding to the mth and (m + 1) th gate lines, and having a second line width different from the first line width, and spaced apart from each other in parallel. Mask pattern corresponding to (m + 2) and (m + 3) gate wirings Photo mask comprising a. The method of claim 1, And the first width is smaller than the second width. In the manufacturing method of the photomask for forming the m-th (m + 3) gate wiring of the liquid crystal display device, Sequentially forming a metal layer and a photoresist layer on the quartz substrate; While moving an electron beam having a write pitch that is twice the distance between two adjacent ones of the m-th to m + 3 gate lines in a first direction parallel to the m-th to m + 3 gate lines, Exposing the photoresist layer; Moving the electron beam by the write pitch in a direction perpendicular to the first direction; Exposing the photoresist layer while moving the electron beam in a second direction opposite to the first direction Photomask manufacturing method comprising a. The method of claim 3, wherein Exposing the photoresist while moving the electron beam in the first direction is exposing a portion of the photoresist corresponding to the mth and (m + 1) th gate lines, and exposing the electron beam to the Exposing the photoresist while moving in a second direction is exposing a portion of the photoresist corresponding to the (m + 2) and (m + 3) gate lines. A substrate; M-th to (m + 3) gate lines formed on the substrate and spaced apart from each other in parallel; Data lines defining first to fourth pixel regions intersecting the m-th to m-th gate lines; A gate electrode connected to each of the mth to (m + 3) th gate lines; A semiconductor layer formed on the gate electrode; Source and drain electrodes spaced apart from each other on the semiconductor layer; A pixel electrode connected to the drain electrode and overlapping each of the mth to (m + 3) th gate lines Wherein the mth and (m + 1) gate lines have a first line width, and the (m + 2) and (m + 3) gate lines have a second line width different from the first line width. An array substrate for a liquid crystal display device. The method of claim 5, And the first width is smaller than the second width. The method of claim 5, During the s-frame, a positive data signal is applied to the pixel electrode of each of the first and third pixel regions, and a negative polarity (−) is applied to the pixel electrode of each of the second and fourth pixel regions. Data signal is applied, During the (s + 1) frame, a negative data signal is applied to the pixel electrode of each of the first and third pixel regions, and a positive signal is applied to the pixel electrode of each of the second and fourth pixel regions. An array substrate for a liquid crystal display device, to which a polarity (+) data signal is applied. The method of claim 7, wherein And the data signal corresponds to an image of a half gray scale. In the forming of the m-th (m + 3) gate wiring spaced apart from each other in parallel on the substrate and the gate electrode connected to each of the m-th (m + 3) gate wiring, the first line width, respectively A mask pattern corresponding to the mth and (m + 1) th gate lines and spaced in parallel to each other, and adjacent to a mask pattern corresponding to the mth and mthth gate lines; The mth to mth using a photomask having a second line width different from one line width and spaced in parallel to each other and including a mask pattern corresponding to the (m + 2) and (m + 3) th gate lines. +3) forming a gate wiring; Forming data lines defining first to fourth pixel regions intersecting the m-th to m-th gate lines; Forming a semiconductor layer on the gate electrode; Forming source and drain electrodes spaced apart from each other on the semiconductor layer; Forming a pixel electrode connected to the drain electrode and overlapping each of the mth to (m + 3) th gate lines Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 9, The mth and (m + 1) th gate lines have the first line width, and the (m + 2) th and (m + 3) th gate lines have the second linewidth. Manufacturing method. In the manufacturing method of the photomask for forming the m-th (m + 3) gate wiring of the liquid crystal display device, Sequentially forming a metal layer and a photoresist layer on the quartz substrate; The electron beam having a fill pitch corresponding to the distance between adjacent two of the m-th to (m + 3) gate lines moves along a first direction perpendicular to the m-th to (m + 3) gate lines Exposing the photoresist layer; Moving the electron beam by the write pitch in a direction perpendicular to the first direction; Exposing the photoresist layer while moving the electron beam in a second direction opposite to the first direction Photomask manufacturing method comprising a. The method of claim 11, The photomask has a long side in the form of a rectangle parallel to the first direction, and a mask pattern region corresponding to a plurality of liquid crystal display array substrates is disposed on the photomask, and each of the plurality of liquid crystal display array substrates is disposed. The method of manufacturing a photomask having a short side in the form of a rectangle parallel to the first direction.

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